void ariaDecryptBlock(AriaContext *context, const uint8_t *input, uint8_t *output)
{
uint32_t *dk;
uint32_t p[4];
uint32_t q[4];
//Copy the ciphertext to the buffer
memcpy(p, input, ARIA_BLOCK_SIZE);
//Point to the decryption round keys
dk = context->dk;
//Apply 11 rounds
OF(p, dk + 0);
EF(p, dk + 4);
OF(p, dk + 8);
EF(p, dk + 12);
OF(p, dk + 16);
EF(p, dk + 20);
OF(p, dk + 24);
EF(p, dk + 28);
OF(p, dk + 32);
EF(p, dk + 36);
OF(p, dk + 40);
//128-bit master keys require a total of 12 rounds
if(context->nr == 12)
{
XOR128(p, dk + 44);
SL2(q, p);
XOR128(q, dk + 48);
}
//192-bit master keys require a total of 14 rounds
else if(context->nr == 14)
{
EF(p, dk + 44);
OF(p, dk + 48);
XOR128(p, dk + 52);
SL2(q, p);
XOR128(q, dk + 56);
}
//256-bit master keys require a total of 16 rounds
else
{
EF(p, dk + 44);
OF(p, dk + 48);
EF(p, dk + 52);
OF(p, dk + 56);
XOR128(p, dk + 60);
SL2(q, p);
XOR128(q, dk + 64);
}
//The resulting value is the plaintext
memcpy(output, q, ARIA_BLOCK_SIZE);
}
int
set_add(intset_t* set, val_t val, int transactional)
{
int result = 0;
if (!transactional)
{
return set_seq_add(set, val);
}
#ifdef SEQUENTIAL /* Unprotected */
return set_seq_add(set, val);
#endif
#ifdef EARLY_RELEASE
return set_early_add(set, val);
#endif
#ifdef READ_VALIDATION
return set_readval_add(set, val);
#endif
node_t prev, next;
nxt_t to_store;
TX_START;
#ifdef DEBUG
PRINT("++> set_add(%d)\tretry: %u", (int) val, tm2c_tx->retries);
#endif
to_store = OF(set->head);
TX_LOAD_NODE(prev, set->head);
TX_LOAD_NODE(next, ND(prev.next));
while (next.val < val)
{
to_store = prev.next;
prev.val = next.val;
prev.next = next.next;
TX_LOAD_NODE(next, ND(prev.next));
}
result = (next.val != val);
if (result)
{
node_t* nn = new_node(val, prev.next, 1);
prev.next = OF(nn);
TX_STORE(ND(to_store), prev.to_int64, TYPE_INT);
}
TX_COMMIT_MEM;
return result;
}
//------------------------------------------------------------------------------
IDDC IDDContent::OF_MPZ(const mpz_t &n)
{
IDDC res = zero;
unsigned int i = -1;
while((i=mpz_scan1(n, i+1)) != ULONG_MAX)
res = AMSB(res, OF(i));
return res;
}
static int
set_seq_add(intset_t* set, val_t val)
{
int result;
node_t prev, nnext;
#ifdef LOCKS
global_lock();
#endif
nxt_t to_store = OF(set->head);
/* int seq = 0; */
node_t* hd = set->head;
LOAD_NODE(prev, hd);
/* PRINT("%3d LOAD: head: %10lu val: %10ld %d", seq++, to_store, prev.val, prev.next); */
node_t* nd = ND(prev.next);
LOAD_NODE(nnext, nd);
/* PRINT("%3d LOAD: addr: %10d val: %10ld %d", seq++, prev.next, nnext.val, nnext.next); */
while (nnext.val < val)
{
to_store = prev.next;
prev.val = nnext.val;
prev.next = nnext.next;
node_t* nd = ND(prev.next);
LOAD_NODE(nnext, nd);
/* PRINT("%3d LOAD: addr: %10lu val: %10ld %d", seq++, prev.next, nnext.val, nnext.next); */
}
result = (nnext.val != val);
if (result)
{
node_t *nn = new_node(val, prev.next, 0);
prev.next = OF(nn);
node_t* nd = ND(to_store);
NONTX_STORE(nd, prev.to_int64, TYPE_INT);
/* PRINT("%3d STORE: addr: %10lu val: %10ld %d", seq++, to_store, prev.val, prev.next); */
}
#ifdef LOCKS
global_lock_release();
#endif
return result;
}
bool ESPSerialWiFiManager::_connect_enc(String ssid){
OF("Connect to "); O(ssid); OFL(":");
String pass = _prompt("Password", '*');
_get_advanced();
return _connect(ssid, pass);
}
//------------------------------------------------------------------------------
unsigned int IDDContent::TO(const IDDC &n, int l, bool dec)
{
if(n == zero) return 0;
else if(n == one) return 1;
else if(n->ul_fit()) return n->val();
else
{
if(COMP(AMSB(zero,OF((unsigned int)l)), n) > (dec?0:-1))
{
unsigned int g = TO(n->g, l, dec);
unsigned int p = TO(n->p, l, dec);
unsigned int d = TO(n->d, l, dec);
p = 1 << (1 << p);
return g + p*d;
}
else
return TO(DEC(AMSB(zero,OF((unsigned int)l))), l, dec);
}
}
int main()
{
unsigned short input; // warning : unsigned short
int i;
printf("%d\n", sizeof(unsigned short));
printf("input a number\n");
scanf(" %o", &input);
printf("input the offset\n");
scanf(" %d", &i);
OF(input, i);
printf("%x,%o\n", input, input);
}
void set_delete(intset_t *set) {
node_t node, next;
LOAD_NODE(node, set->head);
nxt_t to_del = OF(set->head);
while (node.next != 0) {
to_del = node.next;
LOAD_NODE(next, ND(node.next));
sys_shfree(ND(to_del));
node.next = next.next;
}
sys_shfree((void*) set);
}
String ESPSerialWiFiManager::_prompt(String prompt, char mask, int timeout){
static char cmd[PROMPT_INPUT_SIZE];
static int count;
static char tmp;
memset(cmd, 0, PROMPT_INPUT_SIZE);
count = 0;
if(timeout > 0){
NL(); OF("Timeout in "); O(timeout); OFL("s...");
}
int start = millis();
O(prompt.c_str());
OF("> ");
while(true){
if(Serial.available() > 0){
tmp = Serial.read();
if(tmp != '\n' && tmp != '\r'){
cmd[count] = tmp;
if(mask==' ')
Serial.write(tmp);
else
Serial.write(mask);
Serial.flush();
count++;
}
else{
_flush_serial();
NL(); NL();
return String(cmd);
}
}
delay(1);
if(timeout > 0 && (millis()-start) > (timeout * 1000)){
return "-1";
}
}
}
int
set_remove(intset_t* set, val_t val, int transactional)
{
int result = 0;
#ifdef DEBUG
PRINT("++> set_remove(%d)", (int) val);
#endif
#ifdef SEQUENTIAL /* Unprotected */
return set_seq_remove(set, val);
#endif
#ifdef EARLY_RELEASE
return set_early_remove(set, val);
#endif
#ifdef READ_VALIDATION
return set_readval_remove(set, val);
#endif
node_t prev, next;
TX_START;
nxt_t to_store = OF(set->head);
TX_LOAD_NODE(prev, set->head);
TX_LOAD_NODE(next, ND(prev.next));
while (val > next.val)
{
to_store = prev.next;
prev.val = next.val;
prev.next = next.next;
TX_LOAD_NODE(next, ND(prev.next));
}
result = (next.val == val);
if (result)
{
TX_SHFREE(ND(prev.next));
prev.next = next.next;
TX_STORE(ND(to_store), prev.to_int64, TYPE_INT);
}
TX_COMMIT_MEM;
return result;
}
intset_t*
set_new()
{
intset_t *set;
node_t *min, *max;
if ((set = (intset_t *) malloc(sizeof (intset_t))) == NULL)
{
perror("malloc");
EXIT(1);
}
node_t** nodes = (node_t**) pgas_app_alloc_rr(2, sizeof(node_t));
min = nodes[0];
max = nodes[1];
write_node(max, VAL_MAX, 0, 0);
write_node(min, VAL_MIN, OF(max), 0);
set->head = min;
return set;
}
void ESPSerialWiFiManager::_disp_network_details(){
OFL("=============================");
OFL("Current Network Details:");
OFL("=============================");
if(status() != WL_CONNECTED){
OFL("\nNot currently connected!\n");
}
else{
OL("SSID: " + WiFi.SSID());
OF("IP Address: ");
OL(WiFi.localIP());
// print your MAC address:
byte mac[6];
WiFi.macAddress(mac);
OF("MAC address: ");
Serial.print(mac[5],HEX);
Serial.print(":");
Serial.print(mac[4],HEX);
Serial.print(":");
Serial.print(mac[3],HEX);
Serial.print(":");
Serial.print(mac[2],HEX);
Serial.print(":");
Serial.print(mac[1],HEX);
Serial.print(":");
Serial.println(mac[0],HEX);
OF("Subnet Mask: ");
OL(WiFi.subnetMask());
OF("Gateway: ");
OL(WiFi.gatewayIP());
OF("DNS 1: ");
OL(WiFi.dnsIP(0));
OF("DNS 2: ");
OL(WiFi.dnsIP(1));
}
OFL("=============================");
}
MCBSP_FMKS(SPCR, DLB, OFF) | // Loopback (Kurschluss) nicht aktiv
MCBSP_FMKS(SPCR, RJUST, RZF) | // rechtsbündige Ausrichtung der Daten im Puffer
MCBSP_FMKS(SPCR, CLKSTP, DISABLE) | // Clock startet ohne Verzögerung auf fallenden Flanke (siehe auch PCR-Register)
MCBSP_FMKS(SPCR, DXENA, OFF) | // DX- Enabler wird nicht verwendet
MCBSP_FMKS(SPCR, RINTM, RRDY) | // Sender Interrupt wird durch "RRDY-Bit" ausgelöst
MCBSP_FMKS(SPCR, RSYNCERR, NO) | // senderseitig keine Überwachung der Synchronisation
MCBSP_FMKS(SPCR, RRST, YES), // Empfänger läuft (kein Reset- Status)
/* Empfangs-Control Register */
MCBSP_FMKS(RCR, RPHASE, SINGLE) | // Nur eine Phase pro Frame
MCBSP_FMKS(RCR, RFRLEN2, DEFAULT) | // Länge in Phase 2, unrelevant
MCBSP_FMKS(RCR, RWDLEN2, DEFAULT) | // Wortlänge in Phase 2, unrelevant
MCBSP_FMKS(RCR, RCOMPAND, MSB) | // kein Compandierung der Daten (MSB first)
MCBSP_FMKS(RCR, RFIG, NO) | // Rahmensynchronisationspulse (nach dem ersten Puls)) startet die Übertragung neu
MCBSP_FMKS(RCR, RDATDLY, 0BIT) | // keine Verzögerung (delay) der Daten
MCBSP_FMKS(RCR, RFRLEN1, OF(1)) | // Länge der Phase 1 --> 1 Wort
MCBSP_FMKS(RCR, RWDLEN1, 16BIT) | //EIGEN!!!: Recieve Word Length on phase 1: 1 Word (vllt 8BIT anstatt OF(1) )
MCBSP_FMKS(RCR, RWDREVRS, DISABLE), // 32-bit Reversal nicht genutzt
/* Sende-Control Register */
MCBSP_FMKS(XCR, XPHASE, SINGLE) | //EIGEN!!!: Nur eine Phase pro Frame
MCBSP_FMKS(XCR, XFRLEN2, DEFAULT) | // Länge in Phase 2, unrelevant
MCBSP_FMKS(XCR, XWDLEN2, DEFAULT) | // Wortlänge in Phase 2, unrelevant
MCBSP_FMKS(XCR, XCOMPAND, MSB) | // kein Compandierung der Daten (MSB first)
MCBSP_FMKS(XCR, XFIG, NO) | // Rahmensynchronisationspulse (nach dem ersten Puls)) startet die Übertragung neu
MCBSP_FMKS(XCR, XDATDLY, 0BIT) | // keine Verzögerung (delay) der Daten
MCBSP_FMKS(XCR, XFRLEN1, OF(1)) | // Länge der Phase 1 --> 1 Wort
MCBSP_FMKS(XCR, XWDLEN1, 16BIT) | // Wortlänge in Phase 1 --> 16 bit
MCBSP_FMKS(XCR, XWDREVRS, DISABLE), // 32-bit Reversal nicht genutzt
/* Sample Rate Generator Register */
int main(int argc, char **argv) {
{
YojsonWriter OF(std::cout);
OF.emitInteger(100000);
}
{
YojsonWriter OF(std::cout);
OF.emitString("Hello");
}
{
YojsonWriter OF(std::cout);
OF.emitBoolean(true);
}
{
YojsonWriter OF(std::cout);
ArrayScope Scope(OF);
OF.emitString("Hello");
OF.emitBoolean(true);
OF.emitInteger(100000);
}
{
YojsonWriter OF(std::cout);
ObjectScope Scope(OF);
OF.emitTag("string");
OF.emitString("Hello");
OF.emitTag("boolean");
OF.emitBoolean(true);
OF.emitTag("integer");
OF.emitInteger(100000);
}
{
YojsonWriter OF(std::cout);
ObjectScope Scope(OF);
OF.emitTag("integer");
OF.emitInteger(100000);
OF.emitTag("array");
{
ArrayScope Scope(OF);
OF.emitInteger(1);
OF.emitInteger(2);
}
}
{
JsonWriter OF(std::cout);
STDTupleScope Scope(OF);
OF.emitSimpleVariant("zero");
{
STDVariantScope Scope(OF, "succ");
{
STDVariantScope Scope(OF, "pred");
OF.emitSimpleVariant("zero");
}
}
}
{
YojsonWriter OF(std::cout);
TupleScope Scope(OF);
OF.emitSimpleVariant("zero");
{
VariantScope Scope(OF, "succ");
{
VariantScope Scope(OF, "pred");
{
VariantScope Scope(OF, "eval");
{
TupleScope Scope(OF);
OF.emitString("f");
OF.emitString("\"3\t4\n\"");
}
}
}
}
}
return 0;
}
I rk(I f,A r,A a,A w)
{
A z=0,*p=0;
if(w)ND2 else ND1;
{
XA;
C *pp=0,*ap,*wp;
I wt=0,wr=0,wn=0,*wd=0;
I n=0,t=0,i,j,k,d[9],rw,ra,ri,ir,iw=0,ia=0,ii=0,
e=!w&&f==MP(9),h=QP(f)&&f!=MP(71)&&!e;
Q(!QA(r),9);
Q(r->t,6);
Q(r->n<1||r->n>3,8);
ar-=ra=raw(ar,*r->p);
if(!w) mv(d,ad,ra),ir=tr(ra,ad),ad+=ra;
else
{
wt=w->t,wr=w->r,wd=w->d;
wr-=rw=raw(wr,r->p[r->n>1]),ri=r->n>2?r->p[2]:9;
Q(ri<0,9);
if(ri>ra)ri=ra;
if(ri>rw)ri=rw;
mv(d,ad,ra-=ri);
ia=tr(ra,ad),mv(d+ra,wd,rw),iw=tr(rw-=ri,wd);
Q(cm(ad+=ra,wd+=rw,ri),11);
ii=tr(ri,ad),ra+=rw+ri,ir=ia*iw*ii,wn=tr(wr,wd+=ri),ad+=ri;
if(h&&ir>iw&&(f==MP(21)||f==MP(25)||f==MP(26)||f==MP(32)||f==MP(33)))
h=0;
}
an=tr(ar,ad);
if(h)
{
g=0;
aw_c[0]=a->c;
aw_c[1]=w&&w->c;
r=(A)fa(f,gC(at,ar,an,ad,a->n?a->p:0),w?gC(wt,wr,wn,wd,w->n?w->p:0):0);
aw_c[0]=aw_c[1]=1;
if(!r)R 0;
r=un(&r);
mv(d+ra,r->d,j=r->r);
if((j+=ra)>MAXR)R q=13,(I)r;
n=r->n;t=r->t;
if(ir<2) R mv(r->d,d,r->r=j),r->n*=ir,(I)r;
dc(r);
if(g==(I (*)())rsh) R rsh(w?w:a,j,d);
if(!g){h=0;}
else
{
if(at=atOnExit,w) wt=wtOnExit;
if(at!=a->t&&!(a=at?ep_cf(1):ci(1))) R 0;
if(w&&wt!=w->t&&!(w=wt?ep_cf(2):ci(2))) R 0;
OF(i,ir,n);
W(ga(t,j,i,d));
pp=(C*)z->p;
}
}
if(!h)
{
W(ga(Et,ra,ir,d));
*--Y=zr(z),p=(A*)z->p;
}
if(!w)
{
for(ap=(C*)a->p;ir--;ap+=Tt(at,an))
if(h) (*(I(*)(C*,C*,I))g)(pp,ap,an),pp+=Tt(t,n);
else a=gc(at,ar,an,ad,(I*)ap),*p++=e?a:(A)fa(f,(I)a,0);
}
else
{
for(i=0;i<ia;++i)for(j=0;j<iw;++j)
for(k=0;k<ii;++k){
ap=(C*)a->p+Tt(at,(i*ii+k)*an);
wp=(C*)w->p+Tt(wt,(j*ii+k)*wn);
if(h)
{
(*(I(*)(C*,C*,C*,I))g)(pp,ap,wp,n),pp+=Tt(t,n);
if(q==1)*--Y=(I)z,aplus_err(q,(A)Y[1]),++Y;
}
else
{
*p++=(A)fa(f,(I)gc(at,ar,an,ad,(I*)ap),(I)gc(wt,wr,wn,wd,(I*)wp));
}
}
}
if(h)R(I)z;
if(!e)z=(A)dis(r=z),dc(r);
R ++Y,(I)z;
}
}
int main(int argc, char **argv) {
{
BiniouWriter OF(std::cout);
OF.emitInteger(-100000);
}
{
BiniouWriter OF(std::cout);
int64_t min_ocaml = -4611686018427387904;
OF.emitInteger(min_ocaml);
}
{
BiniouWriter OF(std::cout);
int64_t max_ocaml = 4611686018427387903;
OF.emitInteger(max_ocaml);
}
{
BiniouWriter OF(std::cout);
OF.emitString("Hello");
}
{
BiniouWriter OF(std::cout);
OF.emitBoolean(true);
}
{
BiniouWriter OF(std::cout);
ArrayScope Scope(OF, 0);
}
{
BiniouWriter OF(std::cout);
ArrayScope Scope(OF, 3);
OF.emitString("Hello, how are you?");
OF.emitString("I'm well, thank you; and you, how are you?");
OF.emitString("I'm fine, thank you.");
}
{
BiniouWriter OF(std::cout);
ArrayScope Scope(OF, 3);
{
ArrayScope Scope(OF, 1);
{
ArrayScope Scope(OF, 1);
OF.emitInteger(1);
}
}
{
ArrayScope Scope(OF, 2);
{
ArrayScope Scope(OF, 0);
}
{
ArrayScope Scope(OF, 2);
OF.emitInteger(2);
OF.emitInteger(3);
}
}
{
ArrayScope Scope(OF, 0);
}
}
{
BiniouWriter OF(std::cout);
ObjectScope Scope(OF, 12); // 12 is larger than the actual size on purpose
OF.emitTag("string");
OF.emitString("Hello");
OF.emitTag("boolean");
OF.emitBoolean(true);
OF.emitTag("integer");
OF.emitInteger(100000);
}
{
BiniouWriter OF(std::cout);
ObjectScope Scope(OF, 2);
OF.emitTag("integer");
OF.emitInteger(100000);
OF.emitTag("array");
{
ArrayScope Scope(OF, 2);
OF.emitInteger(1);
OF.emitInteger(2);
}
}
{
BiniouWriter OF(std::cout);
ObjectScope Scope(OF, 2);
OF.emitTag("string");
OF.emitString("multiply");
OF.emitTag("array");
{
ArrayScope Scope(OF, 2);
{
ObjectScope Scope(OF, 1);
OF.emitTag("integer");
OF.emitInteger(32);
}
{
ObjectScope Scope(OF, 2);
OF.emitTag("integer");
OF.emitInteger(52);
}
}
}
{
BiniouWriter OF(std::cout);
TupleScope Scope(OF, 2);
OF.emitSimpleVariant("zero");
{
VariantScope Scope(OF, "succ");
{
VariantScope Scope(OF, "pred");
OF.emitSimpleVariant("zero");
}
}
}
{
BiniouWriter OF(std::cout);
TupleScope Scope(OF, 2);
OF.emitSimpleVariant("zero");
{
VariantScope Scope(OF, "succ");
{
VariantScope Scope(OF, "pred");
{
VariantScope Scope(OF, "eval");
{
TupleScope Scope(OF, 2);
OF.emitString("f");
OF.emitString("\"3\t4\n\"");
}
}
}
}
}
return 0;
}
int CollectDataFlow(const std::string &DFTBinary, const std::string &DirPath,
const Vector<SizedFile> &CorporaFiles) {
Printf("INFO: collecting data flow: bin: %s dir: %s files: %zd\n",
DFTBinary.c_str(), DirPath.c_str(), CorporaFiles.size());
MkDir(DirPath);
auto Temp = TempPath(".dft");
for (auto &F : CorporaFiles) {
// For every input F we need to collect the data flow and the coverage.
// Data flow collection may fail if we request too many DFSan tags at once.
// So, we start from requesting all tags in range [0,Size) and if that fails
// we then request tags in [0,Size/2) and [Size/2, Size), and so on.
// Function number => DFT.
std::unordered_map<size_t, Vector<uint8_t>> DFTMap;
std::unordered_set<std::string> Cov;
std::queue<std::pair<size_t, size_t>> Q;
Q.push({0, F.Size});
while (!Q.empty()) {
auto R = Q.front();
Printf("\n\n\n********* Trying: [%zd, %zd)\n", R.first, R.second);
Q.pop();
Command Cmd;
Cmd.addArgument(DFTBinary);
Cmd.addArgument(std::to_string(R.first));
Cmd.addArgument(std::to_string(R.second));
Cmd.addArgument(F.File);
Cmd.addArgument(Temp);
Printf("CMD: %s\n", Cmd.toString().c_str());
if (ExecuteCommand(Cmd)) {
// DFSan has failed, collect tags for two subsets.
if (R.second - R.first >= 2) {
size_t Mid = (R.second + R.first) / 2;
Q.push({R.first, Mid});
Q.push({Mid, R.second});
}
} else {
Printf("********* Success: [%zd, %zd)\n", R.first, R.second);
std::ifstream IF(Temp);
std::string L;
while (std::getline(IF, L, '\n')) {
// Data flow collection has succeeded.
// Merge the results with the other runs.
if (L.empty()) continue;
if (L[0] == 'C') {
// Take coverage lines as is, they will be the same in all attempts.
Cov.insert(L);
} else if (L[0] == 'F') {
size_t FunctionNum = 0;
std::string DFTString;
if (ParseDFTLine(L, &FunctionNum, &DFTString)) {
auto &DFT = DFTMap[FunctionNum];
if (DFT.empty()) {
// Haven't seen this function before, take DFT as is.
DFT = DFTStringToVector(DFTString);
} else if (DFT.size() == DFTString.size()) {
// Have seen this function already, merge DFTs.
DFTStringAppendToVector(&DFT, DFTString);
}
}
}
}
}
}
auto OutPath = DirPlusFile(DirPath, Hash(FileToVector(F.File)));
// Dump combined DFT to disk.
Printf("Producing DFT for %s\n", OutPath.c_str());
std::ofstream OF(OutPath);
for (auto &DFT: DFTMap)
OF << "F" << DFT.first << " " << DFT.second << std::endl;
for (auto &C : Cov)
OF << C << std::endl;
}
RemoveFile(Temp);
// Write functions.txt.
Command Cmd;
Cmd.addArgument(DFTBinary);
Cmd.setOutputFile(DirPlusFile(DirPath, "functions.txt"));
ExecuteCommand(Cmd);
return 0;
}
MCBSP_FMKS(SPCR, RINTM, RRDY) | // Sender Interrupt wird durch "RRDY-Bit" ausgelöst
MCBSP_FMKS(SPCR, RSYNCERR, NO) | // keine Überwachung der Synchronisation
MCBSP_FMKS(SPCR, RRST, YES), // Empfänger läuft (kein Reset- Status)
/* Empfangs-Control Register */
MCBSP_FMKS(RCR, RPHASE, DEFAULT) | // Nur eine Phase pro Frame
MCBSP_FMKS(RCR, RFRLEN2, DEFAULT) | // Länge in Phase 2, unrelevant
MCBSP_FMKS(RCR, RWDLEN2, DEFAULT) | // Wortlänge in Phase 2, unrelevant
MCBSP_FMKS(RCR, RCOMPAND, DEFAULT) | // kein Compandierung der Daten
MCBSP_FMKS(RCR, RFIG, DEFAULT) | // Rahmensynchronisationspulse werden nicht ignoriert
MCBSP_FMKS(RCR, RDATDLY, DEFAULT) | // keine Verzögerung (delay) der Daten
MCBSP_FMKS(RCR, RFRLEN1, DEFAULT) | // Länge der Phase 1, unrelevant
MCBSP_FMKS(RCR, RWDLEN1, DEFAULT) | // Wortlänge in Phase 1, unrelevant
MCBSP_FMKS(RCR, RWDREVRS, DEFAULT), // 32-bit Reversal nicht genutzt
/* Sende-Control Register */
MCBSP_FMKS(XCR, XPHASE, SINGLE) | // Nur eine Phase pro Frame
MCBSP_FMKS(XCR, XFRLEN2, OF(0)) | // Länge in Phase 2, unrelevant
MCBSP_FMKS(XCR, XWDLEN2, 8BIT) | // Wortlänge in Phase 2, unrelevant
MCBSP_FMKS(XCR, XCOMPAND, MSB) | // kein Compandierung der Daten
MCBSP_FMKS(XCR, XFIG, NO) | // Rahmensynchronisationspulse werden nicht ignoriert
MCBSP_FMKS(XCR, XDATDLY, 1BIT) | // 1 bit Verzögerung (delay) der Daten
MCBSP_FMKS(XCR, XFRLEN1, OF(0)) | // Länge der Phase 1 --> 1 Wort
MCBSP_FMKS(XCR, XWDLEN1, 16BIT) | // Wortlänge in Phase 1 --> 16 bit
MCBSP_FMKS(XCR, XWDREVRS, DISABLE), // 32-bit Reversal nicht genutzt
/* Sample Rate Generator Register */
MCBSP_FMKS(SRGR, GSYNC, FREE) | // Samplerate-Clock läuft frei
MCBSP_FMKS(SRGR, CLKSP, RISING) | // nicht relevant da interner Clock verwendet wird
MCBSP_FMKS(SRGR, CLKSM, INTERNAL) | // Samplerate-Clock wird vom CPU-Clock abgeleitet
MCBSP_FMKS(SRGR, FSGM, DXR2XSR) | // Framesync- Signal bei jedem DXR zu XSR Kopiervorgang (setzt FPER und FWID ausser Kraft)
MCBSP_FMKS(SRGR, FPER, OF(0)) | // s.o
MCBSP_FMKS(SRGR, FWID, OF(19)) | // s.o
MCBSP_FMKS(SRGR, CLKGDV, OF(99)), // Teilerwert für die CPU-Clock
void WriteToFile(const Unit &U, const std::string &Path) {
std::ofstream OF(Path);
OF.write((const char*)U.data(), U.size());
}
error_t ariaInit(AriaContext *context, const uint8_t *key, size_t keyLength)
{
uint_t i;
uint32_t *ek;
uint32_t *dk;
const uint32_t *ck1;
const uint32_t *ck2;
const uint32_t *ck3;
uint32_t w[16];
//128-bit master key?
if(keyLength == 16)
{
//Select the relevant constants
ck1 = c + 0;
ck2 = c + 4;
ck3 = c + 8;
//The number of rounds depends on the size of the master key
context->nr = 12;
}
//192-bit master key?
else if(keyLength == 24)
{
//Select the relevant constants
ck1 = c + 4;
ck2 = c + 8;
ck3 = c + 0;
//The number of rounds depends on the size of the master key
context->nr = 14;
}
//256-bit master key?
else if(keyLength == 32)
{
//Select the relevant constants
ck1 = c + 8;
ck2 = c + 0;
ck3 = c + 4;
//The number of rounds depends on the size of the master key
context->nr = 16;
}
else
{
//Report an error
return ERROR_INVALID_KEY_LENGTH;
}
//Compute 128-bit values KL and KR
memset(w, 0, sizeof(w));
memcpy(w, key, keyLength);
//Save KR...
MOV128(w + 8, w + 4);
//Compute intermediate values W0, W1, W2, and W3
MOV128(w + 4, w + 0);
OF(w + 4, ck1);
XOR128(w + 4, w + 8);
MOV128(w + 8, w + 4);
EF(w + 8, ck2);
XOR128(w + 8, w + 0);
MOV128(w + 12, w + 8);
OF(w + 12, ck3);
XOR128(w + 12, w + 4);
//Convert from big-endian byte order to host byte order
for(i = 0; i < 16; i++)
w[i] = betoh32(w[i]);
//Point to the encryption round keys
ek = context->ek;
//Compute ek1, ..., ek17 as follow
ROL128(ek + 0, w + 4, 109);
XOR128(ek + 0, w + 0);
ROL128(ek + 4, w + 8, 109);
XOR128(ek + 4, w + 4);
ROL128(ek + 8, w + 12, 109);
XOR128(ek + 8, w + 8);
ROL128(ek + 12, w + 0, 109);
XOR128(ek + 12, w + 12);
ROL128(ek + 16, w + 4, 97);
XOR128(ek + 16, w + 0);
ROL128(ek + 20, w + 8, 97);
XOR128(ek + 20, w + 4);
ROL128(ek + 24, w + 12, 97);
XOR128(ek + 24, w + 8);
ROL128(ek + 28, w + 0, 97);
XOR128(ek + 28, w + 12);
ROL128(ek + 32, w + 4, 61);
XOR128(ek + 32, w + 0);
ROL128(ek + 36, w + 8, 61);
XOR128(ek + 36, w + 4);
ROL128(ek + 40, w + 12, 61);
XOR128(ek + 40, w + 8);
ROL128(ek + 44, w + 0, 61);
XOR128(ek + 44, w + 12);
ROL128(ek + 48, w + 4, 31);
XOR128(ek + 48, w + 0);
ROL128(ek + 52, w + 8, 31);
XOR128(ek + 52, w + 4);
ROL128(ek + 56, w + 12, 31);
XOR128(ek + 56, w + 8);
ROL128(ek + 60, w + 0, 31);
XOR128(ek + 60, w + 12);
ROL128(ek + 64, w + 4, 19);
XOR128(ek + 64, w + 0);
//Convert from host byte order to big-endian byte order
for(i = 0; i < 68; i++)
ek[i] = htobe32(ek[i]);
//Decryption round keys are derived from the encryption round keys
dk = context->dk;
//Compute dk1
MOV128(dk + 0, ek + context->nr * 4);
//Compute dk2, ..., dk(n)
for(i = 1; i < context->nr; i++)
A(dk + i * 4, ek + (context->nr - i) * 4);
//Compute dk(n + 1)
MOV128(dk + i * 4, ek + 0);
//No error to report
return NO_ERROR;
}
// 0 8 bits // 1 12 bits // 2 16 bits // 3 20 bits // 4 24 bits // 5 32 bits // 6-7 RESERVED // 4 RWDREVRS Receive 32 bit reversal enable. If set 32-bit reversal enabled. RWDLEN1/2 should be 0x5 and RCOMPAND should be 0x1 // 3-0 RESERVED MCBSP_FMKS(RCR, RPHASE, SINGLE) | //Single Phase MCBSP_FMKS(RCR, RFRLEN2, DEFAULT) | //1 word MCBSP_FMKS(RCR, RWDLEN2, DEFAULT) | //8 bits MCBSP_FMKS(RCR, RCOMPAND, MSB) | //No companding, 8 bit MSB first MCBSP_FMKS(RCR, RFIG, NO) | //Receive frame does not restart transfer MCBSP_FMKS(RCR, RDATDLY, 0BIT) | //0 bit delay MCBSP_FMKS(RCR, RFRLEN1, OF(0)) | //1 word MCBSP_FMKS(RCR, RWDLEN1, 32BIT) | //32 bits MCBSP_FMKS(RCR, RWDREVRS, DISABLE), //32 bit reversal disabled //XCR - Transmit Control Register // 31 XPHASE Transmit phases // 0 Single Phase // 1 Dual Phase // 30-24 XFRLEN2 Phase 2 transmit word length // 0 1 word // 1 2 words // 2 3 words // ... ... // 0x7F 128 words // 23-21 XWDLEN2 Phase 2 transmit word length // 0 8 bits
MCBSP_FMKS(SPCR, XRST, YES) |
MCBSP_FMKS(SPCR, DLB, OFF) |
MCBSP_FMKS(SPCR, RJUST, RZF) |
MCBSP_FMKS(SPCR, CLKSTP, DISABLE) |
MCBSP_FMKS(SPCR, DXENA, OFF) |
MCBSP_FMKS(SPCR, RINTM, RRDY) |
MCBSP_FMKS(SPCR, RSYNCERR, NO) |
MCBSP_FMKS(SPCR, RRST, YES),
MCBSP_FMKS(RCR, RPHASE, SINGLE) |
MCBSP_FMKS(RCR, RFRLEN2, DEFAULT) |
MCBSP_FMKS(RCR, RWDLEN2, DEFAULT) |
MCBSP_FMKS(RCR, RCOMPAND, MSB) |
MCBSP_FMKS(RCR, RFIG, NO) |
MCBSP_FMKS(RCR, RDATDLY, 0BIT) |
MCBSP_FMKS(RCR, RFRLEN1, OF(0)) | // This changes to 1 FRAME
MCBSP_FMKS(RCR, RWDLEN1, 32BIT) | // This changes to 32 bits per frame
MCBSP_FMKS(RCR, RWDREVRS, DISABLE),
MCBSP_FMKS(XCR, XPHASE, SINGLE) |
MCBSP_FMKS(XCR, XFRLEN2, DEFAULT) |
MCBSP_FMKS(XCR, XWDLEN2, DEFAULT) |
MCBSP_FMKS(XCR, XCOMPAND, MSB) |
MCBSP_FMKS(XCR, XFIG, NO) |
MCBSP_FMKS(XCR, XDATDLY, 0BIT) |
MCBSP_FMKS(XCR, XFRLEN1, OF(0)) | // This changes to 1 FRAME
MCBSP_FMKS(XCR, XWDLEN1, 32BIT) | // This changes to 32 bits per frame
MCBSP_FMKS(XCR, XWDREVRS, DISABLE),
MCBSP_FMKS(SRGR, GSYNC, DEFAULT) |
MCBSP_FMKS(SRGR, CLKSP, DEFAULT) |
/*
* EDMA Config data structure
*/
/* Transmit side EDMA configuration */
EDMA_Config gEdmaConfigXmt = {
EDMA_FMKS(OPT, PRI, HIGH) | // Priority
EDMA_FMKS(OPT, ESIZE, 16BIT) | // Element size
EDMA_FMKS(OPT, 2DS, NO) | // 2 dimensional source?
EDMA_FMKS(OPT, SUM, INC) | // Src update mode
EDMA_FMKS(OPT, 2DD, NO) | // 2 dimensional dest
EDMA_FMKS(OPT, DUM, NONE) | // Dest update mode
EDMA_FMKS(OPT, TCINT, YES) | // Cause EDMA interrupt?
EDMA_FMKS(OPT, TCC, OF(0)) | // Transfer complete code
EDMA_FMKS(OPT, LINK, YES) | // Enable link parameters?
EDMA_FMKS(OPT, FS, NO), // Use frame sync?
(Uint32)&gBufferXmtPing, // Src address
EDMA_FMK (CNT, FRMCNT, NULL) | // Frame count
EDMA_FMK (CNT, ELECNT, BUFFSIZE), // Element count
EDMA_FMKS(DST, DST, OF(0)), // Dest address
EDMA_FMKS(IDX, FRMIDX, DEFAULT) | // Frame index value
EDMA_FMKS(IDX, ELEIDX, DEFAULT), // Element index value
EDMA_FMK (RLD, ELERLD, NULL) | // Reload element
EDMA_FMK (RLD, LINK, NULL) // Reload link
void conf_EDMA(){
/*
* Open EDMA channels to the REVT1 and XEVT1 interrupts
* issued from the MCBSP periphery. The channels still
* need to be configured properly with a parameterset
* and another parameterset that fills the pong Buffer.
*/
hEDMATrx = EDMA_open(EDMA_CHA_XEVT1, EDMA_OPEN_RESET);
/*
* Aquire EDMA tables that hold the reload tables for both,
* transmit and receive side bufferswitch.
*/
hEDMATrxPing = EDMA_allocTable(-1);
hEDMATrxPong = EDMA_allocTable(-1);
/*
* Set the EDMA source address. On the receive side we use
* the MCBSP source address and save it in the EDMA config
* handle. For the transmit side we will have a fixed
* destination but a variable source address, so we need to
* set the destination to a fixed address!
*/
conf_EDMA_oBuf.dst = MCBSP_getXmtAddr(hMcBsp);
/*
* The next step is to find free Transfer complete codes,
* save them to a variable so the EDMA hardware interrupt
* is able to distinguish between the RX and TX complete
* code. We *could* assign those as static codes, but it
* is better coding practice to make it variable to allow
* future expansion of the code.
*/
tccTrxPing = EDMA_intAlloc(-1);
conf_EDMA_oBuf.opt |= EDMA_FMK(OPT, TCC, tccTrxPing);
/*
* Configure the transmit and receive channel to write in the
* ping buffers. The function copies the struct into the
* EDMA parameter RAM. This allows us to reuse the configs
* to set up the reload configuration for the pong buffers.
*/
EDMA_config(hEDMATrx, &conf_EDMA_oBuf);
EDMA_config(hEDMATrxPing, &conf_EDMA_oBuf);
/*
* Now we are ready to configure the reload parametersets
* that will write to the pong buffers after the ping
* buffer is filled with data.
*/
/*
* First we need to set the destination and source of the
* corresponding pong buffers for both sides.
*/
conf_EDMA_oBuf.src = (uint32_t)oBufPong;
/*
* We also need a transfer complete code for the second
* configuration set to show that we indeed have finished
* the transfer to the pong buffers and switch to ping.
* To overwrite the ones written before we need to
* overwrite the whole 32 OPT bits
*/
tccTrxPong = EDMA_intAlloc(-1);
conf_EDMA_oBuf.opt = EDMA_FMKS(OPT, PRI, HIGH) |
EDMA_FMKS(OPT, ESIZE, 32BIT) |
EDMA_FMKS(OPT, 2DS, NO) |
EDMA_FMKS(OPT, SUM, INC) |
EDMA_FMKS(OPT, 2DD, NO) |
EDMA_FMKS(OPT, DUM, NONE) |
EDMA_FMKS(OPT, TCINT, YES) |
EDMA_FMKS(OPT, TCC, OF(0)) |
EDMA_FMKS(OPT, LINK, YES) |
EDMA_FMKS(OPT, FS, NO);
conf_EDMA_oBuf.opt |= EDMA_FMK(OPT, TCC, tccTrxPong);
/*
* Now we can write the pong buffer configs to the parameter RAM
* tables we aquired before by using EDMA_config()..
*/
EDMA_config(hEDMATrxPong, &conf_EDMA_oBuf);
/*
* We now need to link the transfers so the EDMA fires an interrupt
* whenever we finished a job and immediately starts to
* fill the other buffer (ping -> pong -> ping).
*/
EDMA_link(hEDMATrx, hEDMATrxPing);
EDMA_link(hEDMATrxPing, hEDMATrxPong);
EDMA_link(hEDMATrxPong, hEDMATrxPing);
/*
* Now we take precautions and clear all
* the interrupt sources so no interrupt
* can fire because of some wiggling bits
* caused by an unstable supply.
*/
EDMA_intClear(tccTrxPing);
EDMA_intClear(tccTrxPong);
/*
* Lets enable the interrupts, but we aren't
* done yet: There's still the global interrupt
* switch to be toggled by enable_INT() after
* we started the EDMA transfers.
*/
EDMA_intEnable(tccTrxPing);
EDMA_intEnable(tccTrxPong);
}
