static int
nexus_ofw_map_intr(device_t dev, device_t child, phandle_t iparent, int icells,
pcell_t *intr)
{
fdt_pic_decode_t intr_decode;
phandle_t intr_offset;
int i, rv, interrupt, trig, pol;
intr_offset = OF_xref_phandle(iparent);
for (i = 0; i < icells; i++)
intr[i] = cpu_to_fdt32(intr[i]);
for (i = 0; fdt_pic_table[i] != NULL; i++) {
intr_decode = fdt_pic_table[i];
rv = intr_decode(intr_offset, intr, &interrupt, &trig, &pol);
if (rv == 0) {
/* This was recognized as our PIC and decoded. */
interrupt = FDT_MAP_IRQ(intr_parent, interrupt);
return (interrupt);
}
}
/* Not in table, so guess */
interrupt = FDT_MAP_IRQ(intr_parent, fdt32_to_cpu(intr[0]));
return (interrupt);
}
/*
* Map an interrupt using the firmware reg, interrupt-map and
* interrupt-map-mask properties.
* The interrupt property to be mapped must be of size intrsz, and pointed to
* by intr. The regs property of the node for which the mapping is done must
* be passed as regs. This property is an array of register specifications;
* the size of the address part of such a specification must be passed as
* physsz. Only the first element of the property is used.
* imap and imapsz hold the interrupt mask and it's size.
* imapmsk is a pointer to the interrupt-map-mask property, which must have
* a size of physsz + intrsz; it may be NULL, in which case a full mask is
* assumed.
* maskbuf must point to a buffer of length physsz + intrsz.
* The interrupt is returned in result, which must point to a buffer of length
* rintrsz (which gives the expected size of the mapped interrupt).
* Returns 1 if a mapping was found, 0 otherwise.
*/
int
ofw_bus_search_intrmap(void *intr, int intrsz, void *regs, int physsz,
void *imap, int imapsz, void *imapmsk, void *maskbuf, void *result,
int rintrsz, phandle_t *iparent)
{
phandle_t parent;
uint8_t *ref = maskbuf;
uint8_t *uiintr = intr;
uint8_t *uiregs = regs;
uint8_t *uiimapmsk = imapmsk;
uint8_t *mptr;
pcell_t pintrsz;
int i, rsz, tsz;
rsz = -1;
if (imapmsk != NULL) {
for (i = 0; i < physsz; i++)
ref[i] = uiregs[i] & uiimapmsk[i];
for (i = 0; i < intrsz; i++)
ref[physsz + i] = uiintr[i] & uiimapmsk[physsz + i];
} else {
bcopy(regs, ref, physsz);
bcopy(intr, ref + physsz, intrsz);
}
mptr = imap;
i = imapsz;
while (i > 0) {
bcopy(mptr + physsz + intrsz, &parent, sizeof(parent));
if (OF_searchencprop(OF_xref_phandle(parent),
"#interrupt-cells", &pintrsz, sizeof(pintrsz)) == -1)
pintrsz = 1; /* default */
pintrsz *= sizeof(pcell_t);
/* Compute the map stride size. */
tsz = physsz + intrsz + sizeof(phandle_t) + pintrsz;
KASSERT(i >= tsz, ("ofw_bus_search_intrmap: truncated map"));
/*
* XXX: Apple hardware uses a second cell to set information
* on the interrupt trigger type. This information should
* be used somewhere to program the PIC.
*/
if (bcmp(ref, mptr, physsz + intrsz) == 0) {
bcopy(mptr + physsz + intrsz + sizeof(parent),
result, rintrsz);
if (iparent != NULL)
*iparent = parent;
return (1);
}
mptr += tsz;
i -= tsz;
}
return (0);
}
static struct ofwbus_devinfo *
ofwbus_setup_dinfo(device_t dev, phandle_t node)
{
struct ofwbus_softc *sc;
struct ofwbus_devinfo *ndi;
uint32_t *reg, *intr, icells;
uint64_t phys, size;
phandle_t iparent;
int i, j;
int nintr;
int nreg;
sc = device_get_softc(dev);
ndi = malloc(sizeof(*ndi), M_DEVBUF, M_WAITOK | M_ZERO);
if (ofw_bus_gen_setup_devinfo(&ndi->ndi_obdinfo, node) != 0) {
free(ndi, M_DEVBUF);
return (NULL);
}
if (OFWBUS_EXCLUDED(ndi->ndi_obdinfo.obd_name,
ndi->ndi_obdinfo.obd_type)) {
ofw_bus_gen_destroy_devinfo(&ndi->ndi_obdinfo);
free(ndi, M_DEVBUF);
return (NULL);
}
resource_list_init(&ndi->ndi_rl);
nreg = OF_getencprop_alloc(node, "reg", sizeof(*reg), (void **)®);
if (nreg == -1)
nreg = 0;
if (nreg % (sc->acells + sc->scells) != 0) {
if (bootverbose)
device_printf(dev, "Malformed reg property on <%s>\n",
ndi->ndi_obdinfo.obd_name);
nreg = 0;
}
for (i = 0; i < nreg; i += sc->acells + sc->scells) {
phys = size = 0;
for (j = 0; j < sc->acells; j++) {
phys <<= 32;
phys |= reg[i + j];
}
for (j = 0; j < sc->scells; j++) {
size <<= 32;
size |= reg[i + sc->acells + j];
}
/* Skip the dummy reg property of glue devices like ssm(4). */
if (size != 0)
resource_list_add(&ndi->ndi_rl, SYS_RES_MEMORY, i,
phys, phys + size - 1, size);
}
free(reg, M_OFWPROP);
nintr = OF_getencprop_alloc(node, "interrupts", sizeof(*intr),
(void **)&intr);
if (nintr > 0) {
iparent = 0;
OF_searchencprop(node, "interrupt-parent", &iparent,
sizeof(iparent));
OF_searchencprop(OF_xref_phandle(iparent), "#interrupt-cells",
&icells, sizeof(icells));
for (i = 0; i < nintr; i+= icells) {
intr[i] = ofw_bus_map_intr(dev, iparent, icells,
&intr[i]);
resource_list_add(&ndi->ndi_rl, SYS_RES_IRQ, i, intr[i],
intr[i], 1);
}
free(intr, M_OFWPROP);
}
return (ndi);
}
static int
tsec_fdt_attach(device_t dev)
{
struct tsec_softc *sc;
phandle_t phy;
int error = 0;
sc = device_get_softc(dev);
sc->dev = dev;
sc->node = ofw_bus_get_node(dev);
/* Get phy address from fdt */
if (OF_getencprop(sc->node, "phy-handle", &phy, sizeof(phy)) <= 0) {
device_printf(dev, "PHY not found in device tree");
return (ENXIO);
}
phy = OF_xref_phandle(phy);
OF_decode_addr(OF_parent(phy), 0, &sc->phy_bst, &sc->phy_bsh);
OF_getencprop(phy, "reg", &sc->phyaddr, sizeof(sc->phyaddr));
/* Init timer */
callout_init(&sc->tsec_callout, 1);
/* Init locks */
mtx_init(&sc->transmit_lock, device_get_nameunit(dev), "TSEC TX lock",
MTX_DEF);
mtx_init(&sc->receive_lock, device_get_nameunit(dev), "TSEC RX lock",
MTX_DEF);
mtx_init(&sc->ic_lock, device_get_nameunit(dev), "TSEC IC lock",
MTX_DEF);
/* Allocate IO memory for TSEC registers */
sc->sc_rrid = 0;
sc->sc_rres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rrid,
RF_ACTIVE);
if (sc->sc_rres == NULL) {
device_printf(dev, "could not allocate IO memory range!\n");
goto fail1;
}
sc->sc_bas.bsh = rman_get_bushandle(sc->sc_rres);
sc->sc_bas.bst = rman_get_bustag(sc->sc_rres);
/* TSEC attach */
if (tsec_attach(sc) != 0) {
device_printf(dev, "could not be configured\n");
goto fail2;
}
/* Set up interrupts (TX/RX/ERR) */
sc->sc_transmit_irid = TSEC_RID_TXIRQ;
error = tsec_setup_intr(sc, &sc->sc_transmit_ires,
&sc->sc_transmit_ihand, &sc->sc_transmit_irid,
tsec_transmit_intr, "TX");
if (error)
goto fail2;
sc->sc_receive_irid = TSEC_RID_RXIRQ;
error = tsec_setup_intr(sc, &sc->sc_receive_ires,
&sc->sc_receive_ihand, &sc->sc_receive_irid,
tsec_receive_intr, "RX");
if (error)
goto fail3;
sc->sc_error_irid = TSEC_RID_ERRIRQ;
error = tsec_setup_intr(sc, &sc->sc_error_ires,
&sc->sc_error_ihand, &sc->sc_error_irid,
tsec_error_intr, "ERR");
if (error)
goto fail4;
return (0);
fail4:
tsec_release_intr(sc, sc->sc_receive_ires, sc->sc_receive_ihand,
sc->sc_receive_irid, "RX");
fail3:
tsec_release_intr(sc, sc->sc_transmit_ires, sc->sc_transmit_ihand,
sc->sc_transmit_irid, "TX");
fail2:
bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rrid, sc->sc_rres);
fail1:
mtx_destroy(&sc->receive_lock);
mtx_destroy(&sc->transmit_lock);
return (ENXIO);
}
static int
ofw_pcibus_assign_interrupt(device_t dev, device_t child)
{
ofw_pci_intr_t intr[2];
phandle_t node, iparent;
int isz, icells;
node = ofw_bus_get_node(child);
if (node == -1) {
/* Non-firmware enumerated child, use standard routing */
intr[0] = pci_get_intpin(child);
return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
intr[0]));
}
/*
* Try to determine the node's interrupt parent so we know which
* PIC to use.
*/
iparent = -1;
if (OF_getprop(node, "interrupt-parent", &iparent, sizeof(iparent)) < 0)
iparent = -1;
icells = 1;
if (iparent != -1)
OF_getprop(OF_xref_phandle(iparent), "#interrupt-cells",
&icells, sizeof(icells));
/*
* Any AAPL,interrupts property gets priority and is
* fully specified (i.e. does not need routing)
*/
isz = OF_getprop(node, "AAPL,interrupts", intr, sizeof(intr));
if (isz == sizeof(intr[0])*icells)
return ((iparent == -1) ? intr[0] : ofw_bus_map_intr(dev,
iparent, icells, intr));
isz = OF_getprop(node, "interrupts", intr, sizeof(intr));
if (isz == sizeof(intr[0])*icells) {
if (iparent != -1)
intr[0] = ofw_bus_map_intr(dev, iparent, icells, intr);
} else {
/* No property: our best guess is the intpin. */
intr[0] = pci_get_intpin(child);
}
/*
* If we got intr from a property, it may or may not be an intpin.
* For on-board devices, it frequently is not, and is completely out
* of the valid intpin range. For PCI slots, it hopefully is,
* otherwise we will have trouble interfacing with non-OFW buses
* such as cardbus.
* Since we cannot tell which it is without violating layering, we
* will always use the route_interrupt method, and treat exceptions
* on the level they become apparent.
*/
return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, intr[0]));
}
static void
ofw_pcibus_enum_devtree(device_t dev, u_int domain, u_int busno)
{
device_t pcib;
struct ofw_pci_register pcir;
struct ofw_pcibus_devinfo *dinfo;
phandle_t node, child;
u_int func, slot;
int intline;
pcib = device_get_parent(dev);
node = ofw_bus_get_node(dev);
for (child = OF_child(node); child != 0; child = OF_peer(child)) {
if (OF_getprop(child, "reg", &pcir, sizeof(pcir)) == -1)
continue;
slot = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi);
func = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi);
/* Some OFW device trees contain dupes. */
if (pci_find_dbsf(domain, busno, slot, func) != NULL)
continue;
/*
* The preset in the intline register is usually bogus. Reset
* it such that the PCI code will reroute the interrupt if
* needed.
*/
intline = PCI_INVALID_IRQ;
if (OF_getproplen(child, "interrupts") > 0)
intline = 0;
PCIB_WRITE_CONFIG(pcib, busno, slot, func, PCIR_INTLINE,
intline, 1);
/*
* Now set up the PCI and OFW bus layer devinfo and add it
* to the PCI bus.
*/
dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib,
domain, busno, slot, func, sizeof(*dinfo));
if (dinfo == NULL)
continue;
if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, child) !=
0) {
pci_freecfg((struct pci_devinfo *)dinfo);
continue;
}
dinfo->opd_dma_tag = NULL;
pci_add_child(dev, (struct pci_devinfo *)dinfo);
/*
* Some devices don't have an intpin set, but do have
* interrupts. These are fully specified, and set in the
* interrupts property, so add that value to the device's
* resource list.
*/
if (dinfo->opd_dinfo.cfg.intpin == 0) {
ofw_pci_intr_t intr[2];
phandle_t iparent;
int icells;
if (OF_getprop(child, "interrupts", &intr,
sizeof(intr)) > 0) {
iparent = 0;
icells = 1;
OF_getprop(child, "interrupt-parent", &iparent,
sizeof(iparent));
if (iparent != 0) {
OF_getprop(OF_xref_phandle(iparent),
"#interrupt-cells", &icells,
sizeof(icells));
intr[0] = ofw_bus_map_intr(dev, iparent,
icells, intr);
}
resource_list_add(&dinfo->opd_dinfo.resources,
SYS_RES_IRQ, 0, intr[0], intr[0], 1);
}
}
}
}
