/*--------------------------------------------
| Name: kernel_sem_timedwait
| Description:
| Parameters: none
| Return Type: none
| Comments:
| See:
----------------------------------------------*/
int kernel_sem_timedwait(kernel_sem_t* kernel_sem, int flag, const struct timespec * abs_timeout){
int timeout=0;
//
if(!kernel_sem)
return -1;
//
if(flag==TIMER_ABSTIME && abs_timeout) { //warning: on 16bit architecture use ldiv instead '/' for division with long type.
OS_DI();
timeout = kernel_clock_timeout(CLOCK_REALTIME,abs_timeout);
} if(!flag && abs_timeout) {
timeout = __time_s_to_ms(abs_timeout->tv_sec)+__time_ns_to_ms(abs_timeout->tv_nsec);
}
//
#ifdef __KERNEL_UCORE_EMBOS
if(abs_timeout && timeout) {
if(!OS_WaitCSemaTimed(&kernel_sem->sem, timeout)) {
return -1;
}
}else if(abs_timeout && !timeout) {
if(!OS_WaitCSemaTimed(&kernel_sem->sem, 0)) //try to get sem
return -EBUSY;
}else{
OS_WaitCSema(&kernel_sem->sem);
}
#endif
return 0;
}
/*********************************************************************
*
* _FillTxBuf
*
* Function description
* Stores bytes in the sending buffer.
*/
static void _FillTxBuf(U8 Data) {
int Cnt = 0;
OS_INT Byte;
U8 *pBuf;
pBuf = _pTxBuf;
*pBuf = Data;
++pBuf;
++Cnt;
if (_pfGetNextChar != NULL) {
/* Get more bytes from the communication state machine
* until the sending buffer is full.
*/
while (1) {
if (Cnt >= TX_BUF_SIZE) {
break;
}
Byte = _pfGetNextChar();
if (Byte < 0) {
break;
}
*pBuf = (U8)Byte;
++pBuf;
++Cnt;
}
}
OS_DI();
_RetriggerTimer();
TX_CNT = (U8)Cnt;
OS_RestoreI();
}
/*-------------------------------------------
| Name :dev_at91sam9261_uart_x_write
| Description: Write buffer
| Called by Write Posix Interface
| Parameters : descriptor (desc_t)
| buffer adress (char *)
| buffer size
| Return Type: Integer
| Comments : Use DMA or not (byte per byte)
| See : -
---------------------------------------------*/
int dev_at91sam9261_uart_x_write(desc_t desc, const char* buf,int size)
{
unsigned char snd_data;
//
board_inf_uart_t *p_inf_uart;
AT91_REG *p_adr;
p_inf_uart = (board_inf_uart_t *)ofile_lst[desc].p;
p_adr = (AT91_REG *)p_inf_uart->base_adr;
kernel_pthread_mutex_lock (&p_inf_uart->mutex);
// truncated size
if (size >= UART_OUTPUT_BUFFER_SIZE)
size = UART_OUTPUT_BUFFER_SIZE-1;
memcpy(p_inf_uart->output_buffer, buf, size);
//buffer ready
snd_data = p_inf_uart->output_buffer[0];
while (!(*(p_adr+US_CSR) & (0x00000002))) ; // Wait until THR empty
p_inf_uart->output_r = 0;
p_inf_uart->output_w = size;
#if defined(__KERNEL_UCORE_EMBOS) || defined(__KERNEL_UCORE_FREERTOS)
OS_DI();
#elif defined(__KERNEL_UCORE_ECOS)
__clr_irq();
#endif
p_inf_uart->XMIT = 1;
#if defined (USE_DMA_UART_SND)
// TXTEN/PDC Enable
*(p_adr+US_IER) = 0x10; // ENDTX
*(p_adr+US_PDC_TPR) = (unsigned long)&p_inf_uart->output_buffer[0];
*(p_adr+US_PDC_TCR) = size;
#else
// Byte per byte
*(p_adr+US_THR) = snd_data;
*(p_adr+US_IER) = 0x02;
#endif
#if defined(__KERNEL_UCORE_EMBOS) || defined(__KERNEL_UCORE_FREERTOS)
OS_EI();
#elif defined(__KERNEL_UCORE_ECOS)
__set_irq();
#endif
kernel_pthread_mutex_unlock(&p_inf_uart->mutex);
return size;
}
void OS_EnterCriticalSection (void)
{
OST_UINT temp;
temp = OS_DI();
_OS_Flags.bInCriticalSection = 1;
_OS_Flags.bGIE_CTemp = 0;
if (temp & 0x80) _OS_Flags.bGIE_CTemp = 1;
}
void OS_InitHW(void) {
OS_DI();
_InitVIC(); /* Initialize interrupt controller */
/* Initialize PIT as embOS timer, enable timer + timer interrupt */
__PIT_MR = ((OS_TIMER_RELOAD & 0x000FFFFF) | (1 << 25) | (1 << 24));
OS_ARM_InstallISRHandler(_SYSTEM_IRQ_ID, _OS_SystemIrqhandler);
OS_ARM_EnableISR(_SYSTEM_IRQ_ID);
OS_COM_Init();
OS_RestoreI();
}
/*********************************************************************
*
* _LockTxBuf
*
* Function description
* Gains exclusive access to sending buffer.
*
* Return value
* 1 Sending buffer locked
* 0 Sending buffer couldn't be locked as already in use.
*/
static int _LockTxBuf(void) {
int Locked = 0;
OS_DI();
if (!_TxBufLocked) {
_TxBufLocked = 1;
Locked = 1;
}
OS_RestoreI();
return Locked;
}
void OS_EnterCriticalSection (void)
{
OST_UINT temp;
temp = OS_DI();
_OS_Flags.bInCriticalSection = 1;
_OS_Flags.cIPL_Temp = (temp >> 5);
}
void _OS_Dtimer_Create (OST_DTIMER *dtimer)
{
_OS_Temp = OS_DI();
dtimer->Next = _OS_DTimers.Next;
dtimer->Flags = _OS_DTimers.Flags;
dtimer->Timer = 0;
_OS_DTimers.Next = (OST_DTIMER*)dtimer;
_OS_DTimers.Flags.bNextEnable = 1;
OS_RI(_OS_Temp);
}
void _OS_Dtimer_Create (OST_DTIMER *dtimer)
{
_OS_Temp = OS_DI();
dtimer->Next = _OS_DTimers.Next;
dtimer->Timer = 0;
// Perform "dtimer->Flags = _OS_DTimers.Flags;":
*(unsigned char*)dtimer = *(unsigned char*)&_OS_DTimers.Flags;
_OS_DTimers.Next = (OST_DTIMER*)dtimer;
OS_DTIMER_ATOMIC_WRITE_A(_OS_DTimers.Flags.bNextEnable = 1);
OS_RI(_OS_Temp);
}
BOOL OS_Read(FIFO f, int *val) {
fifo_t *fifo = &Fifos[f];
BOOL I;
/* If there is nothing in the FIFO, fail at reading */
if(!fifo->nElems) {
return FALSE;
}
I = CheckInterruptMask();
if (!I) { OS_DI(); }
*val = fifo->elems[fifo->read];
/* Circularly increment the read position */
incrementFifoRead(fifo);
fifo->nElems--;
if (!I) { OS_EI(); }
return TRUE;
}
void OS_Write(FIFO f, int val) {
fifo_t *fifo;
BOOL I;
fifo = &Fifos[f];
I = CheckInterruptMask();
OS_DI();
fifo->elems[fifo->write] = val;
/* Increment the write counter. */
incrementFifoWrite(fifo);
if(fifo->nElems >= FIFOSIZE) { incrementFifoRead(fifo); }
else { fifo->nElems++; }
if (!I) { OS_EI(); }
}
FIFO OS_InitFiFo() {
int i;
FIFO id = INVALIDFIFO;
BOOL I;
I = CheckInterruptMask();
if (!I) { OS_DI(); }
for(i = 0; i < MAXFIFO; i++) {
if(INVALIDFIFO == Fifos[i].fid) {
Fifos[i].fid = id = i + 1;
Fifos[i].write = 0;
Fifos[i].read = 0;
Fifos[i].nElems = 0;
break;
}
}
if (!I) { OS_EI(); }
return id;
}
/*-------------------------------------------
| Name : dev_at91sam9261_uart_x_read
| Description: Called by Read Posix interface
| Parameters : desc : descriptor
| buf : pointer on read buffer
| size : size
| Return Type: integer cb: number of bytes readed
| Comments : -
| See : -
---------------------------------------------*/
int dev_at91sam9261_uart_x_read(desc_t desc, char* buf,int size)
{
board_inf_uart_t *p_inf_uart = (board_inf_uart_t *)ofile_lst[desc].p;
AT91_REG *p_adr = (AT91_REG *)p_inf_uart->base_adr;
int r = p_inf_uart->input_r;
int _buf_in_rcv_no = p_inf_uart->buf_in_rcv_no;
int _buf_in_dma_no = -1;
int cb = 0, w;
kernel_pthread_mutex_lock (&p_inf_uart->mutex);
#if defined(__KERNEL_UCORE_EMBOS) || defined(__KERNEL_UCORE_FREERTOS)
OS_DI();
#elif defined(__KERNEL_UCORE_ECOS)
__clr_irq();
#endif
_buf_in_dma_no = p_inf_uart->buf_in_dma_no; //p_inf_uart->buf_in_rcv_no;
#if defined(__KERNEL_UCORE_EMBOS) || defined(__KERNEL_UCORE_FREERTOS)
OS_EI();
#elif defined(__KERNEL_UCORE_ECOS)
__set_irq();
#endif
do
{
w=0;
if ( !p_inf_uart->fifo_buf_pool[_buf_in_rcv_no].cb ||
cb == size)
break;
w = (size < (cb + p_inf_uart->fifo_buf_pool[_buf_in_rcv_no].cb)
? (size-cb)
: p_inf_uart->fifo_buf_pool[_buf_in_rcv_no].cb);
memcpy (buf+cb,
p_inf_uart->fifo_buf_pool[_buf_in_rcv_no].p,
w);
cb += w;
p_inf_uart->fifo_buf_pool[_buf_in_rcv_no].cb -= w;
p_inf_uart->fifo_buf_pool[_buf_in_rcv_no].p += w;
if (p_inf_uart->fifo_buf_pool[_buf_in_rcv_no].cb <= 0)
{
p_inf_uart->fifo_buf_pool[_buf_in_rcv_no].p =
(uchar8_t *)&p_inf_uart->fifo_input_buffer[
_buf_in_rcv_no*MAX_POOL_BUF_SZ];
_buf_in_rcv_no = ((_buf_in_rcv_no+1)&(~MAX_POOL));
}
} while( _buf_in_rcv_no != _buf_in_dma_no);
//si tout à été lu reconnecter la reception si au cas elle à été deconnecté
if((_buf_in_rcv_no==_buf_in_dma_no)&&p_inf_uart->fifo_buf_pool[_buf_in_rcv_no].cb==0)
{
*(p_adr+US_CR) = AT91C_US_RXEN;
p_inf_uart->flag_overrun = 0;
}
#if defined(__KERNEL_UCORE_EMBOS) || defined(__KERNEL_UCORE_FREERTOS)
OS_DI();
#elif defined(__KERNEL_UCORE_ECOS)
__clr_irq();
#endif
p_inf_uart->input_r = ((p_inf_uart->input_r+cb) & (~UART_FIFO_INPUT_BUFFER_SZ));
p_inf_uart->buf_in_rcv_no = _buf_in_rcv_no;
#if defined(__KERNEL_UCORE_EMBOS) || defined(__KERNEL_UCORE_FREERTOS)
OS_EI();
#elif defined(__KERNEL_UCORE_ECOS)
__set_irq();
#endif
kernel_pthread_mutex_unlock (&p_inf_uart->mutex);
return cb;
}