/*!
*
* @param mmio
* @param pipe_reg
* @param time_interval
*
* @return 0 on success
* @return 1 on failure
*/
int wait_for_vblank_timeout_plb(
unsigned char *mmio,
unsigned long pipe_reg,
unsigned long time_interval)
{
int ret;
unsigned long pipe_status_reg = pipe_reg + PIPE_STATUS_OFFSET;
unsigned long tmp;
os_alarm_t timeout;
unsigned long request_for;
EMGD_TRACE_ENTER;
EMGD_DEBUG("Parameters: MMIO = %p, pipe_reg = %lx, time_interval = %lx",
mmio, pipe_reg, time_interval);
/* If pipe is off then just return */
if(!((1L<<31) & EMGD_READ32(EMGD_MMIO(mmio) + pipe_reg))) {
EMGD_DEBUG("Pipe disabled/Off");
EMGD_TRACE_EXIT;
return 1;
}
/*
* When VGA plane is on the normal wait for vblank won't work
* so just skip it.
*/
if(!(EMGD_READ32(EMGD_MMIO(mmio) + 0x71400) & 0x80000000)) {
EMGD_DEBUG("VGA Plane On");
EMGD_TRACE_EXIT;
return 1;
}
/* 1. Request the interrupt handler to record the next VBlank: */
request_for = VBINT_REQUEST(VBINT_WAIT,
(pipe_status_reg == PIPEA_STAT) ? VBINT_PORT2 : VBINT_PORT4);
mode_context->dispatch->full->request_vblanks(request_for, mmio);
/* 2. Wait & poll for the next VBlank: */
timeout = OS_SET_ALARM(time_interval);
do {
OS_SCHEDULE();
tmp = mode_context->dispatch->full->vblank_occured(request_for);
} while ((tmp == 0x00) && (!OS_TEST_ALARM(timeout)));
if (tmp == 0) {
EMGD_ERROR_EXIT("Timeout waiting for VBLANK");
ret = 0;
} else {
ret = 1;
}
/* 3. End our request for the next VBlank: */
mode_context->dispatch->full->end_request(request_for, mmio);
EMGD_TRACE_EXIT;
return ret;
} /* wait_for_vblank_timeout_plb */
/*!
* Function to sleep in micro seconds. This can be called with millisecond
* ranges.
*
* @param usec
*
* @return void
*/
void igd_pd_usleep(unsigned long usec)
{
if (usec <= 1000) {
OS_SLEEP(usec);
} else {
os_alarm_t alarm = OS_SET_ALARM((usec+999)/1000);
do {
OS_SCHEDULE();
} while (!OS_TEST_ALARM(alarm));
}
} /* end igd_pd_usleep() */
int query_ovl2_tnc(igd_display_h display_h,
unsigned int flags)
{
igd_display_context_t *display = (igd_display_context_t *)display_h;
inter_module_dispatch_t *md;
platform_context_tnc_t * platform;
os_alarm_t timeout;
int ret;
unsigned long pipe_reg, pipe_num;
EMGD_TRACE_ENTER;
switch (flags) {
case IGD_OVL_QUERY_IS_HW_SUPPORTED:
/* This is the second overlay, so HW overlay is not supported */
break;
case IGD_OVL_QUERY_IS_LAST_FLIP_DONE:
/* If there no sync to wait on, then the last flip is done, and the
* Register Update has occured, simply return TRUE (Flip done).
*/
if (!ovl_context->sync2) {
EMGD_DEBUG("Overlay already synced");
EMGD_TRACE_EXIT;
return TRUE;
}
/* According to the PBL B-spec, there doesnt seem to exist any bit
* for Sprite C Flip-Pending status. Testing 0x20AC in code during
* virt queue's REG write shows nothing changed for Bit8. Thus, we
* are using state of the VBLANK ISR bit as ovl2 flip status.
* Assumption is that if were running 2nd overlay, its either clone
* display or VEXT in WinCE. In either case, were not doing full screen
* FB flipping, so this check should be 'statefully' accurate
*/
md = &display->context->mod_dispatch;
platform = (platform_context_tnc_t *)display->context->
platform_context;
pipe_num = PIPE(display)->pipe_num;
if(pipe_num){
pipe_reg = PIPEB_STAT;
} else {
pipe_reg = PIPEA_STAT;
}
if(md && md->check_flip_pending){
ret = OS_PTHREAD_MUTEX_LOCK(&platform->flip_mutex);
if(md->check_flip_pending(MMIO(display), pipe_reg)){
OS_PTHREAD_MUTEX_UNLOCK(&platform->flip_mutex);
EMGD_DEBUG("Overlay2 Sync done but Flip not done");
return FALSE;
}
OS_PTHREAD_MUTEX_UNLOCK(&platform->flip_mutex);
}
/* Now that we know the last flip is done and the register update is
* complete, set the sync to 0 and return TRUE (Flip done). */
ovl_context->sync2 = FLIP_DONE;
break;
case IGD_OVL_QUERY_WAIT_LAST_FLIP_DONE:
/* Wait for 200 milliseconds for the last flip to complete. If not
* done in that time, there is likely a hardware problem so return
* FALSE. */
timeout = OS_SET_ALARM(200);
do {
if (TRUE ==
query_ovl2_tnc(display_h, IGD_OVL_QUERY_IS_LAST_FLIP_DONE)) {
EMGD_TRACE_EXIT;
return TRUE;
}
} while (!OS_TEST_ALARM(timeout));
EMGD_ERROR_EXIT("Timeout waiting for last flip done");
return FALSE;
break;
case IGD_OVL_QUERY_IS_GAMMA_SUPPORTED:
return TRUE;
break;
case IGD_OVL_QUERY_IS_VIDEO_PARAM_SUPPORTED:
return TRUE;
break;
}
EMGD_TRACE_EXIT;
return TRUE;
}
