コード例 #1
0
ファイル: cyberblade_vid.c プロジェクト: Caught/openpliPC
int vixConfigPlayback(vidix_playback_t *info)
{
	int src_w, drw_w;
	int src_h, drw_h;
	int hscale,vscale;
	long base0;
	int y_pitch = 0, uv_pitch = 0;
	int protect=0;
	int layout=0;
	unsigned int i;

	if(!is_supported_fourcc(info->fourcc))
		return -1;

	src_w = info->src.w;
	src_h = info->src.h;

	drw_w = info->dest.w;
	drw_h = info->dest.h;

	switch(info->fourcc)
	{
		case IMGFMT_YUY2:
		case IMGFMT_BGR16:
			y_pitch = (src_w*2 + 15) & ~15;
			uv_pitch = 0;
			YOffs=VOffs=UOffs=info->offset.y = info->offset.v = info->offset.u = 0;
			info->frame_size = y_pitch*src_h;
			layout=0x0; /* packed */
			break;
		case IMGFMT_YV12:
		case IMGFMT_I420:
			y_pitch = (src_w+15) & ~15;
			uv_pitch = ((src_w/2)+7) & ~7;
			YOffs=info->offset.y = 0;
			VOffs=info->offset.v = y_pitch*src_h;
			UOffs=info->offset.u = info->offset.v+(uv_pitch)*(src_h/2);
			info->frame_size = y_pitch*src_h + 2*uv_pitch*(src_h/2);
			layout=0x1; /* planar, 4:1:1 */
			break;
		case IMGFMT_YVU9:
			y_pitch = (src_w+15) & ~15;
			uv_pitch = ((src_w/4)+3) & ~3;
			YOffs=info->offset.y = 0;
			VOffs=info->offset.v = y_pitch*src_h;
			UOffs=info->offset.u = info->offset.v+(uv_pitch)*(src_h/4);
			info->frame_size = y_pitch*src_h + 2*uv_pitch*(src_h/4);
			layout=0x51; /* planar, 16:1:1 */
			break;
	}

	/* Assume we have 2 MB to play with */
	info->num_frames = 0x200000 / info->frame_size;
	if(info->num_frames > VID_PLAY_MAXFRAMES)
		info->num_frames = VID_PLAY_MAXFRAMES;

	/* Start at 6 MB. Let's hope it's not in use. */
	base0 = 0x600000;
	info->dga_addr = cyberblade_mem + base0;

	info->dest.pitch.y = 16;
	info->dest.pitch.u = 16;
	info->dest.pitch.v = 16;

	for(i = 0; i < info->num_frames; i++)
	{
		info->offsets[i] = info->frame_size * i;
		frames[i] = base0+info->offsets[i];
	}

	OUTPORT8(0x3d4,0x39);
	OUTPORT8(0x3d5,INPORT(0x3d5)|1);

	SRINB(0x0b); /* Select new mode */

	/* Unprotect hardware registers... */
	protect=SRINB(0x11);
	SROUTB(0x11, 0x92);

	SROUTB(0x57, 0xc0); /* Playback key function */
	SROUTB(0x21, 0x34); /* Signature control */
	SROUTB(0x37, 0x30); /* Video key mode */

        vixSetGrKeys(&cyberblade_grkey);

	/* compute_scale_factor(&src_w, &drw_w, &shrink, &zoom); */
	{
		int HTotal,VTotal,HSync,VSync,Overflow,HDisp,VDisp;
		int HWinStart,VWinStart;
		int tx1,ty1,tx2,ty2;

		HTotal=CRINB(0x00);
		HSync=CRINB(0x04);
		VTotal=CRINB(0x06);
		VSync=CRINB(0x10);
		Overflow=CRINB(0x07);
		HTotal <<=3;
		HSync <<=3;
		VTotal |= (Overflow & 1) <<8;
		VTotal |= (Overflow & 0x20) <<4;
		VTotal +=4;
		VSync |= (Overflow & 4) <<6;
		VSync |= (Overflow & 0x80) <<2;

		if(CRINB(0xd1)&0x80)
		{
			int TVHTotal,TVVTotal,TVHSyncStart,TVVSyncStart,TVOverflow;
			LOGWRITE("[cyberblade] Using TV-CRTC\n");

    			HDisp=(1+CRINB(0x01))*8;
    			VDisp=1+CRINB(0x12);
    			Overflow=CRINB(0x07);
    			VDisp |= (Overflow & 2) <<7;
    			VDisp |= (Overflow & 0x40) << 3;
 
    			TVHTotal=CRINB(0xe0)*8;
    			TVVTotal=CRINB(0xe6);
    			TVOverflow=CRINB(0xe7);
    			if(TVOverflow&0x20) TVVTotal|=512;
    			if(TVOverflow&0x01) TVVTotal|=256;
    			TVHTotal+=40; TVVTotal+=2;
 
    			TVHSyncStart=CRINB(0xe4)*8;
    			TVVSyncStart=CRINB(0xf0);
    			if(TVOverflow&0x80) TVVSyncStart|=512;
			if(TVOverflow&0x04) TVVSyncStart|=256;
 
			HWinStart=(TVHTotal-HDisp)&15;
			HWinStart|=(HTotal-HDisp)&15;
			HWinStart+=(TVHTotal-TVHSyncStart)-49;
		}
		else
		{
			LOGWRITE("[cyberblade] Using Standard CRTC\n");
			HWinStart=(HTotal-HSync)+15;
		}
                VWinStart=(VTotal-VSync)-8;

		printf("[cyberblade] HTotal: 0x%x, HSStart: 0x%x\n",HTotal,HSync); 
		printf("  VTotal: 0x%x, VStart: 0x%x\n",VTotal,VSync);
		tx1=HWinStart+info->dest.x;
		ty1=VWinStart+info->dest.y;
		tx2=tx1+info->dest.w;
		ty2=ty1+info->dest.h;

		CROUTW(0x86,tx1);
		CROUTW(0x88,ty1);
		CROUTW(0x8a,tx2);
		CROUTW(0x8c,ty2+3);
	}

	if(src_w==drw_w)
		hscale=0;
	else if(src_w<drw_w)
	{
		hscale=((src_w<<10)/(drw_w-2)) & 0x1fff;
	}
	else
	{
		hscale=0x8000 | ((((src_w/drw_w)-1)&7)<<10) | (((drw_w<<10)/src_w) & 0x3ff);
	}

	vscale=(src_h<<10)/(drw_h);
	if(drw_h<src_h)
		vscale=0x8000|((drw_h<<10)/(src_h));

	/* Write scale factors to hardware */

	CROUTW(0x80,hscale); /* Horizontal Scale */
	CROUTW(0x82,vscale); /* Vertical Scale */

	/* Now set the start address and data layout */
	{
		int lb = (y_pitch+2) >> 2;
		CROUTB(0x95, ((lb & 0x100)>>1) | 0x08 ); /* Linebuffer level bit 8 & threshold */
		CROUTB(0x96, (lb & 0xFF)); /* Linebuffer level */

		CROUTB(0x97, 0x00); /* VDE Flags */
		CROUTB(0xBA, 0x00); /* Chroma key */
		CROUTB(0xBB, 0x00); /* Chroma key */
		CROUTB(0xBC, 0xFF); /* Chroma key */
		CROUTB(0xBD, 0xFF); /* Chroma key */
		CROUTB(0xBE, 0x04); /* Capture control */

		if(src_w > 384)
			layout|=4; /* 2x line buffers */
		SROUTB(0x97, layout);

		CROUTW(0x90,y_pitch); /* Y Bytes per row */
		SROUTW(0x9A,uv_pitch); /* UV Bytes per row */

		switch(info->fourcc)
		{
			case IMGFMT_BGR16:
				CROUTB(0x8F, 0x24); /* VDE Flags - Edge Recovery & CSC Bypass */
				CROUTB(0xBF, 0x02); /* Video format - RGB16 */
				SROUTB(0xBE, 0x0); /* HSCB disabled */
				break;
			default:
				CROUTB(0x8F, 0x20); /* VDE Flags - Edge Recovery */
				CROUTB(0xBF, 0x00); /* Video format - YUV */
				SROUTB(0xBE, 0x00); /* HSCB disable - was 0x03*/
				break;
		}

		CROUTB(0x92, ((base0+info->offset.y) >> 3) &0xff); /* Lower 8 bits of start address */
		CROUTB(0x93, ((base0+info->offset.y) >> 11) &0xff); /* Mid 8 bits of start address */
		CROUTB(0x94, ((base0+info->offset.y) >> 19) &0xf); /* Upper 4 bits of start address */
		SROUTB(0x80, ((base0+info->offset.v) >> 3) &0xff); /* Lower 8 bits of start address */
		SROUTB(0x81, ((base0+info->offset.v) >> 11) &0xff); /* Mid 8 bits of start address */
		SROUTB(0x82, ((base0+info->offset.v) >> 19) &0xf); /* Upper 4 bits of start address */
		SROUTB(0x83, ((base0+info->offset.u) >> 3) &0xff); /* Lower 8 bits of start address */
		SROUTB(0x84, ((base0+info->offset.u) >> 11) &0xff); /* Mid 8 bits of start address */
		SROUTB(0x85, ((base0+info->offset.u) >> 19) &0xf); /* Upper 4 bits of start address */
	}

	vixPlaybackSetEq(&equal);

	/* Protect hardware registers again */
	SROUTB(0x11, protect);
	return 0;
}
コード例 #2
0
ファイル: pci.c プロジェクト: laoyouji/wince6.0-1b
//------------------------------------------------------------------------------
//
//  Function:  OALPCIInit
//
BOOL OALPCIInit()
{
    VRC5477_REGS *pVRC5477Regs = OALPAtoUA(VRC5477_REG_PA);
    M1535_CFG_REGS *pM1535Regs = OALPAtoUA(BSP_REG_PA_M1535_CFG);
    OAL_PCI_LOCATION pciLoc;
    UINT32 u32;

    //----------------------------------------------------------------------
    // External PCI
    //----------------------------------------------------------------------

    // Cold reset
    OUTREG32(&pVRC5477Regs->PCICTL0H, PCI_CTRL_CRST);
    OALStall(100000);
    OUTREG32(&pVRC5477Regs->PCICTL0H, 0);
    OALStall(100000);
    
    // Setup windows
    OUTREG32(&pVRC5477Regs->PCIINIT00, BSP_PCI_INIT00);
    OUTREG32(&pVRC5477Regs->PCIW0, BSP_PCI_W0);
    OUTREG32(&pVRC5477Regs->PCIINIT10, BSP_PCI_INIT10);
    OUTREG32(&pVRC5477Regs->PCIW1, BSP_PCI_W1);

    // Setup control & arbiter registers
    OUTREG32(&pVRC5477Regs->PCICTL0L, BSP_PCI_CTL0L);
    OUTREG32(&pVRC5477Regs->PCICTL0H, BSP_PCI_CTL0H);
    OUTREG32(&pVRC5477Regs->PCIARB0L, BSP_PCI_ARB0L);
    OUTREG32(&pVRC5477Regs->PCIARB0H, BSP_PCI_ARB0H);
        
    // Setup configuration space
    OUTREG16(&pVRC5477Regs->PCICMD0, BSP_PCI_CMD0);
    OUTREG8(&pVRC5477Regs->MLTIM0, BSP_PCI_MLTIM0);
    OUTREG32(&pVRC5477Regs->BARC0, BSP_PCI_BARC0);
    OUTREG32(&pVRC5477Regs->BARM010, BSP_PCI_BARM010);
    OUTREG32(&pVRC5477Regs->BARM230, BSP_PCI_BARM230);
    OUTREG32(&pVRC5477Regs->BAR00, BSP_PCI_BAR00);
    OUTREG32(&pVRC5477Regs->BAR10, BSP_PCI_BAR10);
    OUTREG32(&pVRC5477Regs->BAR20, BSP_PCI_BAR20);
    OUTREG32(&pVRC5477Regs->BARB0, BSP_PCI_BARB0);
    OUTREG32(&pVRC5477Regs->BARP00, BSP_PCI_BARP00);
    OUTREG32(&pVRC5477Regs->BARP10, BSP_PCI_BARP10);

    //----------------------------------------------------------------------
    // Internal PCI
    //----------------------------------------------------------------------

    OUTREG32(&pVRC5477Regs->PCICTL1H, PCI_CTRL_CRST);
    OALStall(100000);
    OUTREG32(&pVRC5477Regs->PCICTL1H, 0);
    OALStall(100000);

    // Setup internal PCI windows
    OUTREG32(&pVRC5477Regs->PCIINIT01, BSP_PCI_INIT01);
    OUTREG32(&pVRC5477Regs->IOPCIW0, BSP_IOPCI_W0);
    OUTREG32(&pVRC5477Regs->PCIINIT11, BSP_PCI_INIT11);
    OUTREG32(&pVRC5477Regs->IOPCIW1, BSP_IOPCI_W1);

    // Setup control & arbiter registers
    OUTREG32(&pVRC5477Regs->PCICTL1L, BSP_PCI_CTL1L);
    OUTREG32(&pVRC5477Regs->PCICTL1H, BSP_PCI_CTL1H);
    OUTREG32(&pVRC5477Regs->PCIARB1L, BSP_PCI_ARB1L);
    OUTREG32(&pVRC5477Regs->PCIARB1H, BSP_PCI_ARB1H);
    
    // Setup configuration space
    OUTREG16(&pVRC5477Regs->PCICMD1, BSP_PCI_CMD1);
    OUTREG8(&pVRC5477Regs->MLTIM1, BSP_PCI_MLTIM1);
    OUTREG32(&pVRC5477Regs->BARC1, BSP_PCI_BARC1);
    OUTREG32(&pVRC5477Regs->BARM011, BSP_PCI_BARM011);
    OUTREG32(&pVRC5477Regs->BARM231, BSP_PCI_BARM231);
    OUTREG32(&pVRC5477Regs->BAR01, BSP_PCI_BAR01);
    OUTREG32(&pVRC5477Regs->BAR11, BSP_PCI_BAR11);
    OUTREG32(&pVRC5477Regs->BAR21, BSP_PCI_BAR21);
    OUTREG32(&pVRC5477Regs->BARB1, BSP_PCI_BARB1);
    OUTREG32(&pVRC5477Regs->BARP01, BSP_PCI_BARP01);
    OUTREG32(&pVRC5477Regs->BARP11, BSP_PCI_BARP11);

    OALStall(10000);

    //----------------------------------------------------------------------
    // ALI M1535+ South Bridge
    //----------------------------------------------------------------------
    // Is there ALI M1535+ bridge = CPU board is inserted to SG2 mother board,
    // in such case we must do some initialization --- default config address
    // lines for some ALI M1535+ internal devices colide with PCI slot config
    // address lines.
    pciLoc.bus = 0;
    pciLoc.dev = 8;
    pciLoc.fnc = 0;
    OALPCICfgRead(0, pciLoc, 0, sizeof(u32), &u32);
    if (u32 != 0x153310B9) goto cleanUp;

    //----------------------------------------------------------------------
    // PCI-ISA bridge initialize
    //----------------------------------------------------------------------

    OALLog(L"INFO: OALPCIInit: ALI M1535+ Bridge detected\r\n");

    u32 = 0x0000C119;   // I/O control, select PS2 keyboad/mouse
    OALPCICfgWrite(0, pciLoc, 0x40, sizeof(u32), &u32);
    u32 = 0x0000025D;   // Primary IDE IRQ14
    OALPCICfgWrite(0, pciLoc, 0x44, sizeof(u32), &u32);
    u32 = 0x70000009;   // Audio->IRQ6, PCI INTC->IRQ11
    OALPCICfgWrite(0, pciLoc, 0x48, sizeof(u32), &u32);
    u32 = 0x00000000;   // USB1 enable
    OALPCICfgWrite(0, pciLoc, 0x50, sizeof(u32), &u32);
    u32 = 0x00000000;   // PCSJ
    OALPCICfgWrite(0, pciLoc, 0x54, sizeof(u32), &u32);
    u32 = 0x0000007C;   // IDE IDSEL(AD15), INTR
    OALPCICfgWrite(0, pciLoc, 0x58, sizeof(u32), &u32);
    u32 = 0x00004000;   // Document recommend???
    OALPCICfgWrite(0, pciLoc, 0x6C, sizeof(u32), &u32);
    u32 = 0x002600D2;   // PMU IDSEL(AD14), USB IDSEL(AD13)
    OALPCICfgWrite(0, pciLoc, 0x70, sizeof(u32), &u32);
    u32 = 0x40801F01;   // No modem, USB INTR(IRQ09), 2nd IDE IRQ15, AC97 IDSEL(AD17)
    OALPCICfgWrite(0, pciLoc, 0x74, sizeof(u32), &u32);
    u32 = 0x00000000;   // USB2 disable
    OALPCICfgWrite(0, pciLoc, 0x7C, sizeof(u32), &u32);

    //---------------------------
    // Configure super I/O chip
    //---------------------------
    
    OUTPORT8(&pM1535Regs->config, 0x51);    // Enter config mode
    OUTPORT8(&pM1535Regs->config, 0x23);    
    
    // Enable parallel port
    OUTPORT8(&pM1535Regs->index, 0x07);
    OUTPORT8(&pM1535Regs->data,  0x03);     // Select logical device 3
    OUTPORT8(&pM1535Regs->index, 0x30);
    OUTPORT8(&pM1535Regs->data,  0x01);     // Enable device
    OUTPORT8(&pM1535Regs->index, 0x60);
    OUTPORT8(&pM1535Regs->data,  0x03);     // I/O address: 378h
    OUTPORT8(&pM1535Regs->index, 0x61);
    OUTPORT8(&pM1535Regs->data,  0x78);     // I/O address: 378h
    OUTPORT8(&pM1535Regs->index, 0x70);
    OUTPORT8(&pM1535Regs->data,  0x07);     // Irq: 7
    
    // Enable UART1
    OUTPORT8(&pM1535Regs->index, 0x07);
    OUTPORT8(&pM1535Regs->data,  0x04);     // Select logical device 4
    OUTPORT8(&pM1535Regs->index, 0x30);
    OUTPORT8(&pM1535Regs->data,  0x01);     // Enable device
    OUTPORT8(&pM1535Regs->index, 0x60);
    OUTPORT8(&pM1535Regs->data,  0x03);     // I/O address: 3F8h
    OUTPORT8(&pM1535Regs->index, 0x61);
    OUTPORT8(&pM1535Regs->data,  0xF8);     // I/O address: 3F8h
    OUTPORT8(&pM1535Regs->index, 0x70);
    OUTPORT8(&pM1535Regs->data,  0x04);     // Irq: 4
    
    // Enable UART2/INFRA
    OUTPORT8(&pM1535Regs->index, 0x07);
    OUTPORT8(&pM1535Regs->data,  0x05);     // Select logical device 5
    OUTPORT8(&pM1535Regs->index, 0x30);
    OUTPORT8(&pM1535Regs->data,  0x01);     // Enable device
    OUTPORT8(&pM1535Regs->index, 0x60);
    OUTPORT8(&pM1535Regs->data,  0x03);     // I/O address: 3E8h
    OUTPORT8(&pM1535Regs->index, 0x61);
    OUTPORT8(&pM1535Regs->data,  0xE8);     // I/O address: 3E8h
    OUTPORT8(&pM1535Regs->index, 0x70);
    OUTPORT8(&pM1535Regs->data,  0x05);     // Irq: 5
    
    // Enable PS/2 controller
    OUTPORT8(&pM1535Regs->index, 0x07);
    OUTPORT8(&pM1535Regs->data,  0x07);     // Select logical device 7.
    OUTPORT8(&pM1535Regs->index, 0x30);
    OUTPORT8(&pM1535Regs->data,  0x01);     // Enable device
    OUTPORT8(&pM1535Regs->index, 0x70);
    OUTPORT8(&pM1535Regs->data,  0x01);     // Irq: 1 - keyboard
    OUTPORT8(&pM1535Regs->index, 0x72);
    OUTPORT8(&pM1535Regs->data,  0x0C);     // Irq: 12 - mouse
    
    // Enable UART3
    OUTPORT8(&pM1535Regs->index, 0x07);
    OUTPORT8(&pM1535Regs->data,  0x0B);     // Select logical device 11
    OUTPORT8(&pM1535Regs->index, 0x30);
    OUTPORT8(&pM1535Regs->data,  0x01);     // Enable device
    OUTPORT8(&pM1535Regs->index, 0x60);
    OUTPORT8(&pM1535Regs->data,  0x02);     // I/O address: 2F8h
    OUTPORT8(&pM1535Regs->index, 0x61);
    OUTPORT8(&pM1535Regs->data,  0xF8);     // I/O address: 2F8h
    OUTPORT8(&pM1535Regs->index, 0x70);
    OUTPORT8(&pM1535Regs->data,  0x03);     // Irq: 3
    
    // Exit config mode
    OUTPORT8(&pM1535Regs->config, 0xBB);
  
cleanUp:
    return TRUE;
}
コード例 #3
0
ファイル: pci.c プロジェクト: Caught/openpliPC
/*main(int argc, char *argv[])*/
static int __pci_scan(pciinfo_t *pci_list,unsigned *num_pci)
{
    unsigned int idx;
    struct pci_config_reg pcr;
    int do_mode1_scan = 0, do_mode2_scan = 0;
    int func, hostbridges=0;
    int ret = -1;
    
    pci_lst = pci_list;
    pcicards = 0;
 
    ret = enable_app_io();
    if (ret != 0)
	return(ret);

    if((pcr._configtype = pci_config_type()) == 0xFFFF) return ENODEV;
 
    /* Try pci config 1 probe first */
 
    if ((pcr._configtype == 1) || do_mode1_scan) {
    /*printf("\nPCI probing configuration type 1\n");*/
 
    pcr._ioaddr = 0xFFFF;
 
    pcr._pcibuses[0] = 0;
    pcr._pcinumbus = 1;
    pcr._pcibusidx = 0;
    idx = 0;
 
    do {
        /*printf("Probing for devices on PCI bus %d:\n\n", pcr._pcibusidx);*/
 
        for (pcr._cardnum = 0x0; pcr._cardnum < MAX_PCI_DEVICES_PER_BUS;
		pcr._cardnum += 0x1) {
	  func = 0;
	  do { /* loop over the different functions, if present */
	    pcr._device_vendor = pci_get_vendor(pcr._pcibuses[pcr._pcibusidx], pcr._cardnum,
						func);
            if ((pcr._vendor == 0xFFFF) || (pcr._device == 0xFFFF))
                break;   /* nothing there */
 
	    /*printf("\npci bus 0x%x cardnum 0x%02x function 0x%04x: vendor 0x%04x device 0x%04x\n",
	        pcr._pcibuses[pcr._pcibusidx], pcr._cardnum, func,
		pcr._vendor, pcr._device);*/
	    pcibus = pcr._pcibuses[pcr._pcibusidx];
	    pcicard = pcr._cardnum;
	    pcifunc = func;
 
	    pcr._status_command = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
					pcr._cardnum,func,PCI_CMD_STAT_REG);
	    pcr._class_revision = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
					pcr._cardnum,func,PCI_CLASS_REG);
	    pcr._bist_header_latency_cache = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
					pcr._cardnum,func,PCI_HEADER_MISC);
	    pcr._base0 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
					pcr._cardnum,func,PCI_MAP_REG_START);
	    pcr._base1 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
					pcr._cardnum,func,PCI_MAP_REG_START+4);
	    pcr._base2 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
					pcr._cardnum,func,PCI_MAP_REG_START+8);
	    pcr._base3 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
					pcr._cardnum,func,PCI_MAP_REG_START+0x0C);
	    pcr._base4 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
					pcr._cardnum,func,PCI_MAP_REG_START+0x10);
	    pcr._base5 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
					pcr._cardnum,func,PCI_MAP_REG_START+0x14);
	    pcr._baserom = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
					pcr._cardnum,func,PCI_MAP_ROM_REG);
#if 0
	    pcr._int_pin = pci_config_read_byte(pcr._pcibuses[pcr._pcibusidx],
					pcr._cardnum,func,PCI_INTERRUPT_PIN);
	    pcr._int_line = pci_config_read_byte(pcr._pcibuses[pcr._pcibusidx],
					pcr._cardnum,func,PCI_INTERRUPT_REG);
	    pcr._min_gnt = pci_config_read_byte(pcr._pcibuses[pcr._pcibusidx],
					pcr._cardnum,func,PCI_MIN_GNT);
	    pcr._max_lat = pci_config_read_byte(pcr._pcibuses[pcr._pcibusidx],
					pcr._cardnum,func,PCI_MAX_LAT);
#else
	    pcr._max_min_ipin_iline = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
					pcr._cardnum,func,PCI_INTERRUPT_REG);
#endif
	    pcr._user_config = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx],
					pcr._cardnum,func,PCI_REG_USERCONFIG);
            /* check for pci-pci bridges */
#define PCI_CLASS_MASK 		0xff000000
#define PCI_SUBCLASS_MASK 	0x00ff0000
#define PCI_CLASS_BRIDGE 	0x06000000
#define PCI_SUBCLASS_BRIDGE_PCI	0x00040000
	    switch(pcr._class_revision & (PCI_CLASS_MASK|PCI_SUBCLASS_MASK)) {
		case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI:
		    if (pcr._secondary_bus_number > 0) {
		        pcr._pcibuses[pcr._pcinumbus++] = pcr._secondary_bus_number;
		    }
			break;
		case PCI_CLASS_BRIDGE:
		    if ( ++hostbridges > 1) {
			pcr._pcibuses[pcr._pcinumbus] = pcr._pcinumbus;
			pcr._pcinumbus++;
		    }
			break;
		default:
			break;
	    }
	    if((func==0) && ((pcr._header_type & PCI_MULTIFUNC_DEV) == 0)) {
	        /* not a multi function device */
		func = 8;
	    } else {
	        func++;
	    }
 
	    if (idx++ >= MAX_PCI_DEVICES)
	        continue;
 
	    identify_card(&pcr);
	  } while( func < 8 );
        }
    } while (++pcr._pcibusidx < pcr._pcinumbus);
    }
 
#if !defined(__alpha__) && !defined(__powerpc__)
    /* Now try pci config 2 probe (deprecated) */
 
    if ((pcr._configtype == 2) || do_mode2_scan) {
    OUTPORT8(PCI_MODE2_ENABLE_REG, 0xF1);
    OUTPORT8(PCI_MODE2_FORWARD_REG, 0x00); /* bus 0 for now */
 
    /*printf("\nPCI probing configuration type 2\n");*/
 
    pcr._pcibuses[0] = 0;
    pcr._pcinumbus = 1;
    pcr._pcibusidx = 0;
    idx = 0;
 
    do {
        for (pcr._ioaddr = 0xC000; pcr._ioaddr < 0xD000; pcr._ioaddr += 0x0100){
	    OUTPORT8(PCI_MODE2_FORWARD_REG, pcr._pcibuses[pcr._pcibusidx]); /* bus 0 for now */
            pcr._device_vendor = INPORT32(pcr._ioaddr);
	    OUTPORT8(PCI_MODE2_FORWARD_REG, 0x00); /* bus 0 for now */
 
            if ((pcr._vendor == 0xFFFF) || (pcr._device == 0xFFFF))
                continue;
            if ((pcr._vendor == 0xF0F0) || (pcr._device == 0xF0F0))
                continue;  /* catch ASUS P55TP4XE motherboards */
 
	    /*printf("\npci bus 0x%x slot at 0x%04x, vendor 0x%04x device 0x%04x\n",
	        pcr._pcibuses[pcr._pcibusidx], pcr._ioaddr, pcr._vendor,
                pcr._device);*/
	    pcibus = pcr._pcibuses[pcr._pcibusidx] ;
	    pcicard = pcr._ioaddr ; pcifunc = 0 ;
 
	    OUTPORT8(PCI_MODE2_FORWARD_REG, pcr._pcibuses[pcr._pcibusidx]); /* bus 0 for now */
            pcr._status_command = INPORT32(pcr._ioaddr + 0x04);
            pcr._class_revision = INPORT32(pcr._ioaddr + 0x08);
            pcr._bist_header_latency_cache = INPORT32(pcr._ioaddr + 0x0C);
            pcr._base0 = INPORT32(pcr._ioaddr + 0x10);
            pcr._base1 = INPORT32(pcr._ioaddr + 0x14);
            pcr._base2 = INPORT32(pcr._ioaddr + 0x18);
            pcr._base3 = INPORT32(pcr._ioaddr + 0x1C);
            pcr._base4 = INPORT32(pcr._ioaddr + 0x20);
            pcr._base5 = INPORT32(pcr._ioaddr + 0x24);
            pcr._baserom = INPORT32(pcr._ioaddr + 0x30);
            pcr._max_min_ipin_iline = INPORT8(pcr._ioaddr + 0x3C);
            pcr._user_config = INPORT32(pcr._ioaddr + 0x40);
	    OUTPORT8(PCI_MODE2_FORWARD_REG, 0x00); /* bus 0 for now */
 
            /* check for pci-pci bridges (currently we only know Digital) */
            if ((pcr._vendor == 0x1011) && (pcr._device == 0x0001))
                if (pcr._secondary_bus_number > 0)
                    pcr._pcibuses[pcr._pcinumbus++] = pcr._secondary_bus_number;
 
	    if (idx++ >= MAX_PCI_DEVICES)
	        continue;
 
	    identify_card(&pcr);
	}
    } while (++pcr._pcibusidx < pcr._pcinumbus);
 
    OUTPORT8(PCI_MODE2_ENABLE_REG, 0x00);
    }
 
#endif /* __alpha__ */
 
    disable_app_io();
    *num_pci = pcicards;
 
    return 0 ;
 
}