/*
* Get chip out of power-saving mode, init registers
*/
void
re_cardbus_setup(struct rl_softc *sc)
{
struct re_cardbus_softc *csc = (struct re_cardbus_softc *)sc;
cardbus_devfunc_t ct = csc->ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
pci_chipset_tag_t pc = csc->sc_pc;
pcireg_t reg, command;
int pmreg;
/* Handle power management nonsense */
if (pci_get_capability(pc, csc->sc_tag,
PCI_CAP_PWRMGMT, &pmreg, 0)) {
command = pci_conf_read(pc, csc->sc_tag,
pmreg + PCI_PMCSR);
if (command & RL_PSTATE_MASK) {
pcireg_t iobase, membase, irq;
/* Save important PCI config data */
iobase = pci_conf_read(pc, csc->sc_tag, RL_PCI_LOIO);
membase = pci_conf_read(pc, csc->sc_tag, RL_PCI_LOMEM);
irq = pci_conf_read(pc, csc->sc_tag, RL_PCI_INTLINE);
/* Reset the power state */
printf("%s: chip is in D%d power mode "
"-- setting to D0\n", sc->sc_dev.dv_xname,
command & RL_PSTATE_MASK);
command &= RL_PSTATE_MASK;
pci_conf_write(pc, csc->sc_tag, pmreg + PCI_PMCSR,
command);
/* Restore PCI config data */
pci_conf_write(pc, csc->sc_tag, RL_PCI_LOIO, iobase);
pci_conf_write(pc, csc->sc_tag, RL_PCI_LOMEM, membase);
pci_conf_write(pc, csc->sc_tag, RL_PCI_INTLINE, irq);
}
}
/* Make sure the right access type is on the Cardbus bridge */
(*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cben);
(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
/* Program the BAR */
pci_conf_write(pc, csc->sc_tag, csc->sc_bar_reg, csc->sc_bar_val);
/* Enable proper bits in CARDBUS CSR */
reg = pci_conf_read(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG);
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
reg |= csc->sc_csr;
pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
/* Make sure the latency timer is set to some reasonable value */
reg = pci_conf_read(pc, csc->sc_tag, PCI_BHLC_REG);
if (PCI_LATTIMER(reg) < 0x20) {
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
reg |= (0x20 << PCI_LATTIMER_SHIFT);
pci_conf_write(pc, csc->sc_tag, PCI_BHLC_REG, reg);
}
}
void
rtw_cardbus_setup(struct rtw_cardbus_softc *csc)
{
struct rtw_softc *sc = &csc->sc_rtw;
cardbus_devfunc_t ct = csc->sc_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
pci_chipset_tag_t pc = csc->sc_pc;
pcireg_t reg;
int pmreg;
if (pci_get_capability(pc, csc->sc_tag,
PCI_CAP_PWRMGMT, &pmreg, 0)) {
reg = pci_conf_read(pc, csc->sc_tag, pmreg + 4) & 0x03;
#if 1 /* XXX Probably not right for CardBus. */
if (reg == 3) {
/*
* The card has lost all configuration data in
* this state, so punt.
*/
printf("%s: unable to wake up from power state D3\n",
sc->sc_dev.dv_xname);
return;
}
#endif
if (reg != 0) {
printf("%s: waking up from power state D%d\n",
sc->sc_dev.dv_xname, reg);
pci_conf_write(pc, csc->sc_tag,
pmreg + 4, 0);
}
}
/* Program the BAR. */
pci_conf_write(pc, csc->sc_tag, csc->sc_bar_reg,
csc->sc_bar_val);
/* Make sure the right access type is on the CardBus bridge. */
(*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cben);
(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
/* Enable the appropriate bits in the PCI CSR. */
reg = pci_conf_read(pc, csc->sc_tag,
PCI_COMMAND_STATUS_REG);
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
reg |= csc->sc_csr;
pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG,
reg);
/*
* Make sure the latency timer is set to some reasonable
* value.
*/
reg = pci_conf_read(pc, csc->sc_tag, PCI_BHLC_REG);
if (PCI_LATTIMER(reg) < 0x20) {
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
reg |= (0x20 << PCI_LATTIMER_SHIFT);
pci_conf_write(pc, csc->sc_tag, PCI_BHLC_REG, reg);
}
}
void
atw_cardbus_setup(struct atw_cardbus_softc *csc)
{
#ifdef notyet
struct atw_softc *sc = &csc->sc_atw;
#endif
cardbus_devfunc_t ct = csc->sc_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
pci_chipset_tag_t pc = csc->sc_pc;
pcireg_t reg;
#ifdef notyet
(void)cardbus_setpowerstate(sc->sc_dev.dv_xname, ct, csc->sc_tag,
PCI_PWR_D0);
#endif
/* Program the BAR. */
pci_conf_write(pc, csc->sc_tag, csc->sc_bar_reg,
csc->sc_bar_val);
/* Make sure the right access type is on the CardBus bridge. */
(*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cben);
(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
/* Enable the appropriate bits in the PCI CSR. */
reg = pci_conf_read(pc, csc->sc_tag,
PCI_COMMAND_STATUS_REG);
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
reg |= csc->sc_csr;
pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG,
reg);
/*
* Make sure the latency timer is set to some reasonable
* value.
*/
reg = pci_conf_read(pc, csc->sc_tag, PCI_BHLC_REG);
if (PCI_LATTIMER(reg) < 0x20) {
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
reg |= (0x20 << PCI_LATTIMER_SHIFT);
pci_conf_write(pc, csc->sc_tag, PCI_BHLC_REG, reg);
}
}
void
dc_cardbus_attach(struct device *parent, struct device *self, void *aux)
{
struct dc_cardbus_softc *csc = (struct dc_cardbus_softc *)self;
struct dc_softc *sc = &csc->sc_dc;
struct cardbus_attach_args *ca = aux;
struct cardbus_devfunc *ct = ca->ca_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
pci_chipset_tag_t pc = ca->ca_pc;
cardbus_function_tag_t cf = ct->ct_cf;
pcireg_t reg;
bus_addr_t addr;
sc->sc_dmat = ca->ca_dmat;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
csc->sc_pc = ca->ca_pc;
Cardbus_function_enable(ct);
if (Cardbus_mapreg_map(ct, PCI_CBIO,
PCI_MAPREG_TYPE_IO, 0, &sc->dc_btag, &sc->dc_bhandle, &addr,
&csc->sc_mapsize) == 0) {
csc->sc_actype = CARDBUS_IO_ENABLE;
} else if (Cardbus_mapreg_map(ct, PCI_CBMEM,
PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
&sc->dc_btag, &sc->dc_bhandle, &addr, &csc->sc_mapsize) == 0) {
csc->sc_actype = CARDBUS_MEM_ENABLE;
} else {
printf(": can't map device registers\n");
return;
}
csc->sc_intrline = ca->ca_intrline;
sc->dc_cachesize = pci_conf_read(csc->sc_pc, ca->ca_tag, DC_PCI_CFLT)
& 0xFF;
dc_cardbus_setup(csc);
/* Get the eeprom width */
if ((PCI_VENDOR(ca->ca_id) == PCI_VENDOR_XIRCOM &&
PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_XIRCOM_X3201_3_21143))
; /* XIRCOM has non-standard eeprom */
else
dc_eeprom_width(sc);
switch (PCI_VENDOR(ca->ca_id)) {
case PCI_VENDOR_DEC:
if (PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_DEC_21142) {
sc->dc_type = DC_TYPE_21143;
sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
sc->dc_flags |= DC_REDUCED_MII_POLL;
dc_read_srom(sc, sc->dc_romwidth);
dc_parse_21143_srom(sc);
}
break;
case PCI_VENDOR_XIRCOM:
if (PCI_PRODUCT(ca->ca_id) ==
PCI_PRODUCT_XIRCOM_X3201_3_21143) {
sc->dc_type = DC_TYPE_XIRCOM;
sc->dc_flags |= DC_TX_INTR_ALWAYS|DC_TX_COALESCE |
DC_TX_ALIGN;
sc->dc_pmode = DC_PMODE_MII;
}
break;
case PCI_VENDOR_ADMTEK:
case PCI_VENDOR_ACCTON:
case PCI_VENDOR_ABOCOM:
case PCI_VENDOR_DLINK:
case PCI_VENDOR_LINKSYS:
case PCI_VENDOR_HAWKING:
case PCI_VENDOR_MICROSOFT:
if (PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ADMTEK_AN985 ||
PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ACCTON_EN2242 ||
PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ABOCOM_FE2500 ||
PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ABOCOM_FE2500MX ||
PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_ABOCOM_PCM200 ||
PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_DLINK_DRP32TXD ||
PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_LINKSYS_PCMPC200 ||
PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_LINKSYS_PCM200 ||
PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_HAWKING_PN672TX ||
PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_MICROSOFT_MN120) {
sc->dc_type = DC_TYPE_AN983;
sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_ADMTEK_WAR |
DC_64BIT_HASH;
sc->dc_pmode = DC_PMODE_MII;
/* Don't read SROM for - auto-loaded on reset */
}
break;
default:
printf(": unknown device\n");
return;
}
/*
* set latency timer, do we really need this?
*/
reg = pci_conf_read(pc, ca->ca_tag, PCI_BHLC_REG);
if (PCI_LATTIMER(reg) < 0x20) {
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
reg |= (0x20 << PCI_LATTIMER_SHIFT);
pci_conf_write(pc, ca->ca_tag, PCI_BHLC_REG, reg);
}
sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_NET,
dc_intr, csc, sc->sc_dev.dv_xname);
if (sc->sc_ih == NULL) {
printf(": can't establish interrupt at %d\n",
ca->ca_intrline);
return;
}
printf(": irq %d", ca->ca_intrline);
dc_reset(sc);
sc->dc_revision = PCI_REVISION(ca->ca_class);
dc_attach(sc);
}
void
ahc_cardbus_attach(device_t parent, device_t self, void *aux)
{
struct cardbus_attach_args *ca = aux;
struct ahc_cardbus_softc *csc = device_private(self);
struct ahc_softc *ahc = &csc->sc_ahc;
cardbus_devfunc_t ct = ca->ca_ct;
bus_space_tag_t bst;
bus_space_handle_t bsh;
pcireg_t reg;
u_int sxfrctl1 = 0;
u_char sblkctl;
ahc->sc_dev = self;
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
printf(": Adaptec ADP-1480 SCSI\n");
/*
* Map the device.
*/
csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
if (Cardbus_mapreg_map(csc->sc_ct, AHC_CARDBUS_MMBA,
PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
&bst, &bsh, NULL, &csc->sc_size) == 0) {
csc->sc_bar = AHC_CARDBUS_MMBA;
csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
} else if (Cardbus_mapreg_map(csc->sc_ct, AHC_CARDBUS_IOBA,
PCI_MAPREG_TYPE_IO, 0, &bst, &bsh, NULL, &csc->sc_size) == 0) {
csc->sc_bar = AHC_CARDBUS_IOBA;
csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
} else {
csc->sc_bar = 0;
aprint_error("%s: unable to map device registers\n",
ahc_name(ahc));
return;
}
/* Enable the appropriate bits in the PCI CSR. */
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
reg |= csc->sc_csr;
Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
/*
* Make sure the latency timer is set to some reasonable
* value.
*/
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_BHLC_REG);
if (PCI_LATTIMER(reg) < 0x20) {
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
reg |= (0x20 << PCI_LATTIMER_SHIFT);
Cardbus_conf_write(ct, ca->ca_tag, PCI_BHLC_REG, reg);
}
ahc_set_name(ahc, device_xname(ahc->sc_dev));
ahc->parent_dmat = ca->ca_dmat;
ahc->tag = bst;
ahc->bsh = bsh;
/*
* ADP-1480 is always an AIC-7860.
*/
ahc->chip = AHC_AIC7860 | AHC_PCI;
ahc->features = AHC_AIC7860_FE|AHC_REMOVABLE;
ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
if (PCI_REVISION(ca->ca_class) >= 1)
ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
if (ahc_softc_init(ahc) != 0)
return;
/*
* On all CardBus adapters, we allow SCB paging.
*/
ahc->flags = AHC_PAGESCBS;
ahc->channel = 'A';
ahc_intr_enable(ahc, FALSE);
ahc_reset(ahc);
/*
* Establish the interrupt.
*/
ahc->ih = Cardbus_intr_establish(ct, IPL_BIO, ahc_intr, ahc);
if (ahc->ih == NULL) {
aprint_error("%s: unable to establish interrupt\n",
ahc_name(ahc));
return;
}
ahc->seep_config = malloc(sizeof(*ahc->seep_config),
M_DEVBUF, M_NOWAIT);
if (ahc->seep_config == NULL)
return;
ahc_check_extport(ahc, &sxfrctl1);
/*
* Take the LED out of diagnostic mode.
*/
sblkctl = ahc_inb(ahc, SBLKCTL);
ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
/*
* I don't know where this is set in the SEEPROM or by the
* BIOS, so we default to 100%.
*/
ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
if (ahc->flags & AHC_USEDEFAULTS) {
int our_id;
/*
* Assume only one connector and always turn
* on termination.
*/
our_id = AHC_CARDBUS_DEFAULT_SCSI_ID;
sxfrctl1 = STPWEN;
ahc_outb(ahc, SCSICONF, our_id | ENSPCHK | RESET_SCSI);
ahc->our_id = our_id;
}
printf("%s: aic7860", ahc_name(ahc));
/*
* Record our termination setting for the
* generic initialization routine.
*/
if ((sxfrctl1 & STPWEN) != 0)
ahc->flags |= AHC_TERM_ENB_A;
if (ahc_init(ahc)) {
ahc_free(ahc);
return;
}
ahc_attach(ahc);
}
static void
cs4280_attach(device_t parent, device_t self, void *aux)
{
struct cs428x_softc *sc;
struct pci_attach_args *pa;
pci_chipset_tag_t pc;
const struct cs4280_card_t *cs_card;
char const *intrstr;
const char *vendor, *product;
pcireg_t reg;
uint32_t mem;
int error;
char intrbuf[PCI_INTRSTR_LEN];
sc = device_private(self);
sc->sc_dev = self;
pa = (struct pci_attach_args *)aux;
pc = pa->pa_pc;
pci_aprint_devinfo(pa, "Audio controller");
cs_card = cs4280_identify_card(pa);
if (cs_card != NULL) {
vendor = pci_findvendor(cs_card->id);
product = pci_findproduct(cs_card->id);
if (vendor == NULL)
aprint_normal_dev(sc->sc_dev,
"vendor 0x%04x product 0x%04x\n",
PCI_VENDOR(cs_card->id),
PCI_PRODUCT(cs_card->id));
else if (product == NULL)
aprint_normal_dev(sc->sc_dev, "%s product 0x%04x\n",
vendor, PCI_PRODUCT(cs_card->id));
else
aprint_normal_dev(sc->sc_dev, "%s %s\n",
vendor, product);
sc->sc_flags = cs_card->flags;
} else {
sc->sc_flags = CS428X_FLAG_NONE;
}
sc->sc_pc = pa->pa_pc;
sc->sc_pt = pa->pa_tag;
/* Map I/O register */
if (pci_mapreg_map(pa, PCI_BA0,
PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
&sc->ba0t, &sc->ba0h, NULL, NULL)) {
aprint_error_dev(sc->sc_dev, "can't map BA0 space\n");
return;
}
if (pci_mapreg_map(pa, PCI_BA1,
PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
&sc->ba1t, &sc->ba1h, NULL, NULL)) {
aprint_error_dev(sc->sc_dev, "can't map BA1 space\n");
return;
}
sc->sc_dmatag = pa->pa_dmat;
/* power up chip */
if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self,
pci_activate_null)) && error != EOPNOTSUPP) {
aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error);
return;
}
/* Enable the device (set bus master flag) */
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
reg | PCI_COMMAND_MASTER_ENABLE);
/* LATENCY_TIMER setting */
mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
if ( PCI_LATTIMER(mem) < 32 ) {
mem &= 0xffff00ff;
mem |= 0x00002000;
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem);
}
/* CLKRUN hack initialization */
cs4280_clkrun_hack_init(sc);
/* Map and establish the interrupt. */
if (pci_intr_map(pa, &sc->intrh)) {
aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n");
return;
}
intrstr = pci_intr_string(pc, sc->intrh, intrbuf, sizeof(intrbuf));
mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO);
sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO,
cs4280_intr, sc);
if (sc->sc_ih == NULL) {
aprint_error_dev(sc->sc_dev, "couldn't establish interrupt");
if (intrstr != NULL)
aprint_error(" at %s", intrstr);
aprint_error("\n");
mutex_destroy(&sc->sc_lock);
mutex_destroy(&sc->sc_intr_lock);
return;
}
aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
/* Initialization */
if(cs4280_init(sc, 1) != 0) {
mutex_destroy(&sc->sc_lock);
mutex_destroy(&sc->sc_intr_lock);
return;
}
sc->type = TYPE_CS4280;
sc->halt_input = cs4280_halt_input;
sc->halt_output = cs4280_halt_output;
/* setup buffer related parameters */
sc->dma_size = CS4280_DCHUNK;
sc->dma_align = CS4280_DALIGN;
sc->hw_blocksize = CS4280_ICHUNK;
/* AC 97 attachment */
sc->host_if.arg = sc;
sc->host_if.attach = cs428x_attach_codec;
sc->host_if.read = cs4280_read_codec;
sc->host_if.write = cs4280_write_codec;
#if 0
sc->host_if.reset = cs4280_reset_codec;
#else
sc->host_if.reset = NULL;
#endif
sc->host_if.flags = cs4280_flags_codec;
if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) {
aprint_error_dev(sc->sc_dev, "ac97_attach failed\n");
return;
}
audio_attach_mi(&cs4280_hw_if, sc, sc->sc_dev);
#if NMIDI > 0
midi_attach_mi(&cs4280_midi_hw_if, sc, sc->sc_dev);
#endif
if (!pmf_device_register(self, cs4280_suspend, cs4280_resume))
aprint_error_dev(self, "couldn't establish power handler\n");
}
static void
njata_cardbus_attach(device_t parent, device_t self, void *aux)
{
struct cardbus_attach_args *ca = aux;
struct njata32_cardbus_softc *csc = device_private(self);
struct njata32_softc *sc = &csc->sc_njata32;
const struct njata32_cardbus_product *prod;
cardbus_devfunc_t ct = ca->ca_ct;
pcireg_t reg;
int csr;
uint8_t latency = 0x20;
sc->sc_wdcdev.sc_atac.atac_dev = self;
if ((prod = njata_cardbus_lookup(ca)) == NULL)
panic("njata_cardbus_attach");
aprint_normal(": Workbit NinjaATA-32 IDE controller\n");
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
/*
* Map the device.
*/
csr = PCI_COMMAND_MASTER_ENABLE;
/*
* Map registers.
* Try memory map first, and then try I/O.
*/
if ((prod->p_flags & NJATA32_FL_IOMAP_ONLY) == 0 &&
Cardbus_mapreg_map(csc->sc_ct, NJATA32_CARDBUS_BASEADDR_MEM,
PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
&NJATA32_REGT(sc), &csc->sc_regmaph, NULL, &csc->sc_regmap_size)
== 0) {
if (bus_space_subregion(NJATA32_REGT(sc), csc->sc_regmaph,
NJATA32_MEMOFFSET_REG, NJATA32_REGSIZE, &NJATA32_REGH(sc))
!= 0) {
/* failed -- undo map and try I/O */
Cardbus_mapreg_unmap(csc->sc_ct,
NJATA32_CARDBUS_BASEADDR_MEM, NJATA32_REGT(sc),
csc->sc_regmaph, csc->sc_regmap_size);
goto try_io;
}
#ifdef NJATA32_DEBUG
aprint_normal("%s: memory space mapped, size %u\n",
NJATA32NAME(sc), (unsigned)csc->sc_regmap_size);
#endif
csr |= PCI_COMMAND_MEM_ENABLE;
sc->sc_flags = NJATA32_MEM_MAPPED;
} else {
try_io:
if (Cardbus_mapreg_map(csc->sc_ct, NJATA32_CARDBUS_BASEADDR_IO,
PCI_MAPREG_TYPE_IO, 0, &NJATA32_REGT(sc),
&NJATA32_REGH(sc), NULL, &csc->sc_regmap_size) == 0) {
#ifdef NJATA32_DEBUG
aprint_normal("%s: io space mapped, size %u\n",
NJATA32NAME(sc), (unsigned)csc->sc_regmap_size);
#endif
csr |= PCI_COMMAND_IO_ENABLE;
sc->sc_flags = NJATA32_IO_MAPPED;
} else {
aprint_error("%s: unable to map device registers\n",
NJATA32NAME(sc));
return;
}
}
/* Enable the appropriate bits in the PCI CSR. */
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
reg |= csr;
Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
/*
* Make sure the latency timer is set to some reasonable
* value.
*/
reg = Cardbus_conf_read(ct, ca->ca_tag, PCI_BHLC_REG);
if (PCI_LATTIMER(reg) < latency) {
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
reg |= (latency << PCI_LATTIMER_SHIFT);
Cardbus_conf_write(ct, ca->ca_tag, PCI_BHLC_REG, reg);
}
sc->sc_dmat = ca->ca_dmat;
/*
* Establish the interrupt.
*/
sc->sc_ih = Cardbus_intr_establish(ct, IPL_BIO, njata32_intr, sc);
if (sc->sc_ih == NULL) {
aprint_error("%s: unable to establish interrupt\n",
NJATA32NAME(sc));
return;
}
/* attach */
njata32_attach(sc);
}
void
adv_cardbus_attach(struct device *parent, struct device *self,
void *aux)
{
struct cardbus_attach_args *ca = aux;
struct adv_cardbus_softc *csc = device_private(self);
struct asc_softc *sc = &csc->sc_adv;
cardbus_devfunc_t ct = ca->ca_ct;
cardbus_chipset_tag_t cc = ct->ct_cc;
cardbus_function_tag_t cf = ct->ct_cf;
bus_space_tag_t iot;
bus_space_handle_t ioh;
pcireg_t reg;
u_int8_t latency = 0x20;
sc->sc_flags = 0;
if (PCI_VENDOR(ca->ca_id) == PCI_VENDOR_ADVSYS) {
switch (PCI_PRODUCT(ca->ca_id)) {
case PCI_PRODUCT_ADVSYS_1200A:
printf(": AdvanSys ASC1200A SCSI adapter\n");
latency = 0;
break;
case PCI_PRODUCT_ADVSYS_1200B:
printf(": AdvanSys ASC1200B SCSI adapter\n");
latency = 0;
break;
case PCI_PRODUCT_ADVSYS_ULTRA:
switch (PCI_REVISION(ca->ca_class)) {
case ASC_PCI_REVISION_3050:
printf(": AdvanSys ABP-9xxUA SCSI adapter\n");
break;
case ASC_PCI_REVISION_3150:
printf(": AdvanSys ABP-9xxU SCSI adapter\n");
break;
}
break;
default:
printf(": unknown model!\n");
return;
}
}
csc->sc_ct = ct;
csc->sc_tag = ca->ca_tag;
csc->sc_intrline = ca->ca_intrline;
csc->sc_cbenable = 0;
/*
* Map the device.
*/
csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
#ifdef ADV_CARDBUS_ALLOW_MEMIO
if (Cardbus_mapreg_map(csc->sc_ct, ADV_CARDBUS_MMBA,
PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
&iot, &ioh, NULL, &csc->sc_size) == 0) {
#ifdef ADV_CARDBUS_DEBUG
printf("%s: memio enabled\n", DEVNAME(sc));
#endif
csc->sc_cbenable = CARDBUS_MEM_ENABLE;
csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
} else
#endif
if (Cardbus_mapreg_map(csc->sc_ct, ADV_CARDBUS_IOBA,
PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, &csc->sc_size) == 0) {
#ifdef ADV_CARDBUS_DEBUG
printf("%s: io enabled\n", DEVNAME(sc));
#endif
csc->sc_cbenable = CARDBUS_IO_ENABLE;
csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
} else {
aprint_error_dev(&sc->sc_dev, "unable to map device registers\n");
return;
}
/* Make sure the right access type is on the CardBus bridge. */
(*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cbenable);
(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
/* Enable the appropriate bits in the PCI CSR. */
reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG);
reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
reg |= csc->sc_csr;
cardbus_conf_write(cc, cf, ca->ca_tag, PCI_COMMAND_STATUS_REG, reg);
/*
* Make sure the latency timer is set to some reasonable
* value.
*/
reg = cardbus_conf_read(cc, cf, ca->ca_tag, PCI_BHLC_REG);
if (PCI_LATTIMER(reg) < latency) {
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
reg |= (latency << PCI_LATTIMER_SHIFT);
cardbus_conf_write(cc, cf, ca->ca_tag, PCI_BHLC_REG, reg);
}
ASC_SET_CHIP_CONTROL(iot, ioh, ASC_CC_HALT);
ASC_SET_CHIP_STATUS(iot, ioh, 0);
sc->sc_iot = iot;
sc->sc_ioh = ioh;
sc->sc_dmat = ca->ca_dmat;
sc->pci_device_id = ca->ca_id;
sc->bus_type = ASC_IS_PCI;
sc->chip_version = ASC_GET_CHIP_VER_NO(iot, ioh);
/*
* Initialize the board
*/
if (adv_init(sc)) {
printf("adv_init failed\n");
return;
}
/*
* Establish the interrupt.
*/
sc->sc_ih = cardbus_intr_establish(cc, cf, ca->ca_intrline, IPL_BIO,
adv_intr, sc);
if (sc->sc_ih == NULL) {
aprint_error_dev(&sc->sc_dev,
"unable to establish interrupt\n");
return;
}
/*
* Attach.
*/
adv_attach(sc);
}
void
cs4280_attach(struct device *parent, struct device *self, void *aux)
{
struct cs4280_softc *sc = (struct cs4280_softc *) self;
struct pci_attach_args *pa = (struct pci_attach_args *) aux;
pci_chipset_tag_t pc = pa->pa_pc;
char const *intrstr;
pci_intr_handle_t ih;
u_int32_t mem;
/* Map I/O register */
if (pci_mapreg_map(pa, CSCC_PCI_BA0,
PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
&sc->ba0t, &sc->ba0h, NULL, NULL, 0)) {
printf(": can't map BA0 space\n");
return;
}
if (pci_mapreg_map(pa, CSCC_PCI_BA1,
PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
&sc->ba1t, &sc->ba1h, NULL, NULL, 0)) {
printf(": can't map BA1 space\n");
return;
}
sc->sc_dmatag = pa->pa_dmat;
/* Get out of power save mode if needed. */
pci_set_powerstate(pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
/* LATENCY_TIMER setting */
mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
if ( PCI_LATTIMER(mem) < 32 ) {
mem &= 0xffff00ff;
mem |= 0x00002000;
pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem);
}
/* Map and establish the interrupt. */
if (pci_intr_map(pa, &ih)) {
printf(": couldn't map interrupt\n");
return;
}
intrstr = pci_intr_string(pc, ih);
sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO | IPL_MPSAFE,
cs4280_intr, sc, sc->sc_dev.dv_xname);
if (sc->sc_ih == NULL) {
printf(": couldn't establish interrupt");
if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
return;
}
printf(": %s\n", intrstr);
/* Initialization */
if (cs4280_init(sc, 1) != 0)
return;
mountroothook_establish(cs4280_attachhook, sc);
/* AC 97 attachement */
sc->host_if.arg = sc;
sc->host_if.attach = cs4280_attach_codec;
sc->host_if.read = cs4280_read_codec;
sc->host_if.write = cs4280_write_codec;
sc->host_if.reset = cs4280_reset_codec;
if (ac97_attach(&sc->host_if) != 0) {
printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname);
return;
}
}