static void __init
bamboo_setup_pci(void)
{
void *pci_reg_base;
unsigned long memory_size;
memory_size = ppc_md.find_end_of_memory();
pci_reg_base = ioremap64(BAMBOO_PCIL0_BASE, BAMBOO_PCIL0_SIZE);
/* Enable PCI I/O, Mem, and Busmaster cycles */
PCI_WRITEW(PCI_READW(PCI_COMMAND) |
PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER, PCI_COMMAND);
/* Disable region first */
PCI_WRITEL(0, BAMBOO_PCIL0_PMM0MA);
/* PLB starting addr: 0x00000000A0000000 */
PCI_WRITEL(BAMBOO_PCI_PHY_MEM_BASE, BAMBOO_PCIL0_PMM0LA);
/* PCI start addr, 0xA0000000 (PCI Address) */
PCI_WRITEL(BAMBOO_PCI_MEM_BASE, BAMBOO_PCIL0_PMM0PCILA);
PCI_WRITEL(0, BAMBOO_PCIL0_PMM0PCIHA);
/* Enable no pre-fetch, enable region */
PCI_WRITEL(((0xffffffff -
(BAMBOO_PCI_UPPER_MEM - BAMBOO_PCI_MEM_BASE)) | 0x01),
BAMBOO_PCIL0_PMM0MA);
/* Disable region one */
PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
PCI_WRITEL(0, BAMBOO_PCIL0_PMM1LA);
PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCILA);
PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCIHA);
PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
/* Disable region two */
PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
PCI_WRITEL(0, BAMBOO_PCIL0_PMM2LA);
PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCILA);
PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCIHA);
PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
/* Now configure the PCI->PLB windows, we only use PTM1
*
* For Inbound flow, set the window size to all available memory
* This is required because if size is smaller,
* then Eth/PCI DD would fail as PCI card not able to access
* the memory allocated by DD.
*/
PCI_WRITEL(0, BAMBOO_PCIL0_PTM1MS); /* disabled region 1 */
PCI_WRITEL(0, BAMBOO_PCIL0_PTM1LA); /* begin of address map */
memory_size = 1 << fls(memory_size - 1);
/* Size low + Enabled */
PCI_WRITEL((0xffffffff - (memory_size - 1)) | 0x1, BAMBOO_PCIL0_PTM1MS);
eieio();
iounmap(pci_reg_base);
}
static void __init sequoia_setup_pci(void)
{
void *pci_reg_base;
void *pci_cfg_base;
unsigned long memory_size;
memory_size = ppc_md.find_end_of_memory();
pci_reg_base = ioremap64(SEQUOIA_PCIL0_BASE, SEQUOIA_PCIL0_SIZE);
pci_cfg_base = ioremap64(SEQUOIA_PCI_CFGREGS_BASE, 64);
PCI_CFG_OUT(SEQUOIA_PCI_CFGA_OFFSET,
0x80000000 | (PCI_COMMAND & 0xfc));
PCI_CFG_OUT(SEQUOIA_PCI_CFGD_OFFSET,
( PCI_CFG_IN(SEQUOIA_PCI_CFGD_OFFSET) |
PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER));
/* Disable region first */
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM0MA);
/* PLB starting addr: 0x0000000180000000 */
PCI_WRITEL(SEQUOIA_PCI_PHY_MEM_BASE, SEQUOIA_PCIL0_PMM0LA);
/* PCI start addr, 0x80000000 (PCI Address) */
PCI_WRITEL(SEQUOIA_PCI_MEM_BASE, SEQUOIA_PCIL0_PMM0PCILA);
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM0PCIHA);
/* Enable no pre-fetch, enable region */
PCI_WRITEL(((0xffffffff -
(SEQUOIA_PCI_UPPER_MEM - SEQUOIA_PCI_MEM_BASE)) | 0x01),
SEQUOIA_PCIL0_PMM0MA);
/* Disable region one */
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM1MA);
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM1LA);
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM1PCILA);
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM1PCIHA);
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM1MA);
/* Disable region two */
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM2MA);
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM2LA);
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM2PCILA);
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM2PCIHA);
PCI_WRITEL(0, SEQUOIA_PCIL0_PMM2MA);
/* Now configure the PCI->PLB windows, we only use PTM1
*
* For Inbound flow, set the window size to all available memory
* This is required because if size is smaller,
* then Eth/PCI DD would fail as PCI card not able to access
* the memory allocated by DD.
*/
PCI_WRITEL(0, SEQUOIA_PCIL0_PTM1MS); /* disabled region 1 */
PCI_WRITEL(0, SEQUOIA_PCIL0_PTM1LA); /* begin of address map */
memory_size = 1 << fls(memory_size - 1);
/* Size low + Enabled */
PCI_WRITEL((0xffffffff - (memory_size - 1)) | 0x1, SEQUOIA_PCIL0_PTM1MS);
eieio();
iounmap(pci_reg_base);
}
