uint32_t _kuart_mix_install ( /* [IN] A string that identifies the device for fopen */ char * identifier, /* [IN] The I/O init data void * */ KUART_INIT_STRUCT_CPTR init_data_ptr, /* [IN] The I/O queue size to use */ uint32_t oqueue_size, uint32_t iqueue_size ) { /* Body */ #if PE_LDD_VERSION if (PE_PeripheralUsed((uint32_t)_bsp_get_serial_base_address(init_data_ptr->DEVICE))) { return IO_ERROR; } #endif return _io_serial_mix_install(identifier, (uint32_t (_CODE_PTR_)(void *, char *_))_kuart_mix_init, (uint32_t (_CODE_PTR_)(void *))_kuart_mix_enable, (uint32_t (_CODE_PTR_)(void *,void *))_kuart_mix_deinit, (void (_CODE_PTR_)(void *, char))_kuart_mix_int_putc, (uint32_t (_CODE_PTR_)(void *, uint32_t, void *))_kuart_polled_ioctl, (void *)init_data_ptr, oqueue_size, iqueue_size); } /* Endbody */
uint_32 _kuart_int_install ( /* [IN] A string that identifies the device for fopen */ char_ptr identifier, /* [IN] The I/O init data pointer */ KUART_INIT_STRUCT_CPTR init_data_ptr, /* [IN] The I/O queue size to use */ uint_32 queue_size ) { /* Body */ #if PE_LDD_VERSION if (PE_PeripheralUsed((uint_32)_bsp_get_serial_base_address(init_data_ptr->DEVICE))) { return IO_ERROR; } #endif return _io_serial_int_install(identifier, (uint_32 (_CODE_PTR_)(pointer, char _PTR_))_kuart_int_init, (uint_32 (_CODE_PTR_)(pointer))_kuart_int_enable, (uint_32 (_CODE_PTR_)(pointer,pointer))_kuart_int_deinit, (void (_CODE_PTR_)(pointer, char))_kuart_int_putc, (uint_32 (_CODE_PTR_)(pointer, uint_32, pointer))_kuart_polled_ioctl, (pointer)init_data_ptr, queue_size); } /* Endbody */
uint32_t _ki2c_polled_install ( /* [IN] A string that identifies the device for fopen */ char *identifier, /* [IN] The I/O init data pointer */ KI2C_INIT_STRUCT_CPTR init_data_ptr ) { /* Body */ #if PE_LDD_VERSION if (PE_PeripheralUsed((uint32_t)_bsp_get_i2c_base_address(init_data_ptr->CHANNEL))) { /* IO Device used by PE Component*/ return IO_DEVICE_EXISTS; } #endif return _io_i2c_polled_install(identifier, (_mqx_uint (_CODE_PTR_)(void *, void **, char *))_ki2c_polled_init, (_mqx_uint (_CODE_PTR_)(void *, void *))_ki2c_polled_deinit, (_mqx_int (_CODE_PTR_)(void *, char *, _mqx_int))_ki2c_polled_rx, (_mqx_int (_CODE_PTR_)(void *, char *, _mqx_int))_ki2c_polled_tx, (_mqx_int (_CODE_PTR_)(void *, _mqx_uint, _mqx_uint_ptr))_ki2c_polled_ioctl, (void *)init_data_ptr); } /* Endbody */
uint32_t _kusb_dcd_polled_install ( /* [IN] A string that identifies the device for fopen */ char *identifier, /* [IN] The I/O init data pointer */ KUSB_DCD_INIT_STRUCT_CPTR init_data_ptr ) { /* Body */ #if PE_LDD_VERSION if (PE_PeripheralUsed((uint32_t)_bsp_get_usb_dcd_base_address())) { /* IO Device used by PE Component*/ return IO_DEVICE_EXISTS; } #endif return _io_usb_dcd_polled_install(identifier, (uint32_t (_CODE_PTR_)(void *, void **, char *))_kusb_dcd_polled_init, (uint32_t (_CODE_PTR_)(void *, void *))_kusb_dcd_polled_deinit, (int32_t (_CODE_PTR_)(void *, char *, int32_t))_kusb_dcd_polled_read, (int32_t (_CODE_PTR_)(void *, char *, int32_t))_kusb_dcd_polled_write, (int32_t (_CODE_PTR_)(void *, uint32_t, uint32_t *))_kusb_dcd_polled_ioctl, (void *)init_data_ptr); } /* Endbody */
_mqx_int _bsp_usb_io_init ( void ) { #if PE_LDD_VERSION /* USB clock is configured using CPU component */ /* Check if peripheral is not used by Processor Expert USB_LDD component */ if (PE_PeripheralUsed((uint32_t)USB0_BASE_PTR) == TRUE) { /* IO Device used by PE Component*/ return IO_ERROR; } /** * Workaround for Processor Expert as USB clock divider settings has been removed * from __pe_initialize_hardware() and Cpu_SetClockConfiguration() functions * Needs to be replaced by dynamic calculation of dividers. * SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */ SIM_CLKDIV2 = (uint32_t)((SIM_CLKDIV2 & (uint32_t)~0x0DUL) | (uint32_t)0x02UL); /* Update USB clock prescalers */ #endif #if BSPCFG_USB_USE_IRC48M /* * Configure SIM_CLKDIV2: USBDIV = 0, USBFRAC = 0 */ SIM_CLKDIV2 = (uint32_t)0x0UL; /* Update USB clock prescalers */ /* Configure USB to be clocked from IRC 48MHz */ SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL(3); /* Enable USB-OTG IP clocking */ SIM_SCGC4_REG(SIM_BASE_PTR) |= SIM_SCGC4_USBOTG_MASK; /* Enable IRC 48MHz for USB module */ USB0_CLK_RECOVER_IRC_EN = 0x03; #else /* Configure USB to be clocked from PLL */ SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL(1); /* Enable USB-OTG IP clocking */ SIM_SCGC4_REG(SIM_BASE_PTR) |= SIM_SCGC4_USBOTG_MASK; /* USB D+ and USB D- are standalone not multiplexed one-purpose pins */ /* VREFIN for device is standalone not multiplexed one-purpose pin */ #endif #if BSP_USB_TWR_SER2 /* TWR-SER2 board has 2 connectors: on channel A, there is Micro-USB connector, ** which is not routed to TWRK64 board. On channel B, there is standard ** A-type host connector routed to the USB0 peripheral on TWRK64. To enable ** power to this connector, GPIO PB8 must be set as GPIO output */ PORT_PCR_REG(PORTB_BASE_PTR, 8) = PORT_PCR_MUX(0x01); GPIO_PDDR_REG(PTB_BASE_PTR) |= 1 << 8; // PB8 as output GPIO_PDOR_REG(PTB_BASE_PTR) |= 1 << 8; // PB8 in high level #endif return MQX_OK; }
_mqx_int _bsp_usb_io_init ( void ) { #if PE_LDD_VERSION /* USB clock is configured using CPU component */ /* Check if peripheral is not used by Processor Expert USB_LDD component */ if (PE_PeripheralUsed((uint32_t)USB0_BASE_PTR) == TRUE) { /* IO Device used by PE Component*/ return IO_ERROR; } /** * Workaround for Processor Expert as USB clock divider settings has been removed * from __pe_initialize_hardware() and Cpu_SetClockConfiguration() functions * Needs to be replaced by dynamic calculation of dividers. * SIM_CLKDIV2: USBDIV=1,USBFRAC=0 */ SIM_CLKDIV2 = (uint32_t)((SIM_CLKDIV2 & (uint32_t)~0x0DUL) | (uint32_t)0x02UL); /* Update USB clock prescalers */ #endif /* Configure USB to be clocked from PLL */ SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK; /* Enable USB-OTG IP clocking */ SIM_SCGC4_REG(SIM_BASE_PTR) |= SIM_SCGC4_USBOTG_MASK; /* USB D+ and USB D- are standalone not multiplexed one-purpose pins */ /* VREFIN for device is standalone not multiplexed one-purpose pin */ /** If we need the USB working as a host we have to provide ** power to the USB connector. To do this PTC9 has to be set ** as a GPIO output in high level. ** If USB should work as a device, the J26 jumper should be removed. */ PORT_PCR_REG(PORTC_BASE_PTR, 9) = PORT_PCR_MUX(0x01) | PORT_PCR_PE_MASK; GPIO_PDDR_REG(PTC_BASE_PTR) |= 0x00000200; // PTC9 as output GPIO_PDOR_REG(PTC_BASE_PTR) |= 0x00000200; // PTC9 in high level return MQX_OK; }
_mqx_int _bsp_rtc_io_init ( void ) { #if PE_LDD_VERSION /* Check if peripheral is not used by Processor Expert RTC_LDD component */ if (PE_PeripheralUsed((uint32_t)RTC_BASE_PTR) == TRUE) { /* IO Device used by PE Component*/ return IO_ERROR; } #endif /* Enable the clock gate to the RTC module. */ SIM_SCGC6 |= SIM_SCGC6_RTC_MASK; return MQX_OK; }
_mqx_int _bsp_usb_io_init ( void ) { #if PE_LDD_VERSION /* USB clock is configured using CPU component */ /* Check if peripheral is not used by Processor Expert USB_LDD component */ if (PE_PeripheralUsed((uint_32)USB0_BASE_PTR) == TRUE) { /* IO Device used by PE Component*/ return IO_ERROR; } #endif /* Configure USB to be clocked from PLL */ SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK; /* Enable USB-OTG IP clocking */ SIM_SCGC4_REG(SIM_BASE_PTR) |= SIM_SCGC4_USBOTG_MASK; /* USB D+ and USB D- are standalone not multiplexed one-purpose pins */ /* VREFIN for device is standalone not multiplexed one-purpose pin */ #if BSP_USB_TWR_SER2 /* TWR-SER2 board has 2 connectors: on channel A, there is Micro-USB connector, ** which is not routed to TWRK60 board. On channel B, there is standard ** A-type host connector routed to the USB0 peripheral on TWRK60. To enable ** power to this connector, GPIO PB8 must be set as GPIO output */ PORT_PCR_REG(PORTB_BASE_PTR, 8) = PORT_PCR_MUX(0x01) | PORT_PCR_PE_MASK; GPIO_PDDR_REG(PTB_BASE_PTR) |= 0x00000100; // PB8 as output GPIO_PDOR_REG(PTB_BASE_PTR) |= 0x00000100; // PB8 in high level #endif return MQX_OK; }
/*! * \cond DOXYGEN_PRIVATE * * \brief This function initializes caller allocated structure according to given * numerical identifier of the timer. * * Called by hwtimer_init(). * Initializes the HWTIMER structure. * Sets interrupt priority and registers ISR. * * \param hwtimer[in] Returns initialized hwtimer structure handle. * \param pit_id[in] Determines PIT modul and pit channel. * \param isr_prior[in] Interrupt priority for PIT * * \return MQX_OK Success. * \return MQX_INVALID_PARAMETER When channel number does not exist in pit module. * \return MQX_INVALID_COMPONENT_HANDLE Doesnt have any interrupt vectors, or pit does not exist. * \return -1 When pit is used byt PE or when _int_install_isr faild. * * \see hwtimer_pit_deinit * \see hwtimer_pit_set_div * \see hwtimer_pit_start * \see hwtimer_pit_stop * \see hwtimer_pit_get_time * \see hwtimer_pit_isr * \see hwtimer_pit_isr_shared */ static _mqx_int hwtimer_pit_init(HWTIMER_PTR hwtimer, uint32_t pit_id, uint32_t isr_prior) { HWTIMER_PTR * pit_hwtimers_array = NULL; uint32_t pit_hwtimers_array_size; PSP_INTERRUPT_TABLE_INDEX vector; PIT_MemMapPtr pit_base; uint32_t pit_number; uint32_t pit_channel; uint32_t pit_channels_count; uint32_t pit_vectors_count; _mqx_uint i; const _mqx_uint *pit_vectors = NULL; PIT_MemMapPtr pit; /* Count of chanels is computed, because this information missing in generated iomap file */ pit_channels_count = sizeof(pit->CHANNEL) / sizeof(pit->CHANNEL[0]); #if MQX_CHECK_ERRORS if (pit_channels_count <= pit_id) { return MQX_INVALID_PARAMETER; } #endif /* We need to store pit_id of timer in context struct */ hwtimer->ll_context[0] = (uint32_t)PIT_BASE_PTR; hwtimer->ll_context[1] = pit_id; pit_base = (PIT_MemMapPtr) hwtimer->ll_context[0]; pit_channel = GET_PIT_CHANNEL_FROM_PITID(hwtimer->ll_context[1]); pit_number = GET_PIT_NUMBER_FROM_PITID(hwtimer->ll_context[1]); #if PE_LDD_VERSION if (PE_PeripheralUsed((uint32_t)pit_base)) { return -1; } #endif /* Enable PIT Module Clock */ pit_io_init(0); /* workaround, add delay to pit clk gating and pit module enabling */ for (i = 0; i <= 50; i++) { ; } /* Enable PIT module */ PIT_MCR_REG(pit_base) = 0; #if BSPCFG_HWTIMER_PIT_FREEZE /* Allows the timers to be stopped when the device enters the Debug mode. */ PIT_MCR_REG(pit_base) |= PIT_MCR_FRZ_MASK; #endif /* Disable timer and interrupt */ PIT_TCTRL_REG(pit_base, pit_channel) = 0; /* Clear any pending interrupt */ PIT_TFLG_REG(pit_base, pit_channel) = PIT_TFLG_TIF_MASK; /* Set isr for timer*/ pit_vectors_count = pit_get_vectors(pit_number, &pit_vectors); #if MQX_CHECK_ERRORS if ((NULL == pit_vectors) || (0 == pit_vectors_count)) { return MQX_INVALID_COMPONENT_HANDLE; //doesnt have any interrupt vectors, or pit does not exist } #endif if (pit_channels_count <= pit_vectors_count) { /* Every channel has own interrupt vector */ vector = (PSP_INTERRUPT_TABLE_INDEX) (pit_vectors[pit_channel]); if (NULL == _int_install_isr(vector, (INT_ISR_FPTR) hwtimer_pit_isr, (void *) hwtimer)) { return -1; } _bsp_int_init(vector, isr_prior, 0, TRUE); } else { pit_hwtimers_array_size = pit_get_hwtimers_array(&pit_hwtimers_array); #if MQX_CHECK_ERRORS if ((NULL == pit_hwtimers_array) || (0 == pit_hwtimers_array_size)) { return MQX_INVALID_COMPONENT_HANDLE; } #endif /* Pit has shared interrupt vectors */ pit_hwtimers_array[pit_channel] = hwtimer; for (i = 0; i < pit_vectors_count; i++) { vector = (PSP_INTERRUPT_TABLE_INDEX) (pit_vectors[i]); if (NULL == _int_install_isr(vector, (INT_ISR_FPTR) hwtimer_pit_isr_shared, NULL)) { return -1; } _bsp_int_init(vector, isr_prior, 0, TRUE); } } return MQX_OK; }
static _mqx_int _bsp_usb_io_init ( _mqx_uint i ) { if (i == 0) { #if PE_LDD_VERSION /* USB clock is configured using CPU component */ /* Check if peripheral is not used by Processor Expert USB_LDD component */ if (PE_PeripheralUsed((uint_32)USB0_BASE_PTR) == TRUE) { /* IO Device used by PE Component*/ return IO_ERROR; } #endif /* Configure USB to be clocked from PLL0 */ SIM_SOPT2_REG(SIM_BASE_PTR) &= ~(SIM_SOPT2_USBFSRC_MASK); SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBFSRC(1); /* Configure USB to be clocked from clock divider */ SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBF_CLKSEL_MASK; /* Configure USB divider to be 120MHz * 2 / 5 = 48 MHz */ SIM_CLKDIV2_REG(SIM_BASE_PTR) &= ~(SIM_CLKDIV2_USBFSDIV_MASK | SIM_CLKDIV2_USBFSFRAC_MASK); SIM_CLKDIV2_REG(SIM_BASE_PTR) |= SIM_CLKDIV2_USBFSDIV(4) | SIM_CLKDIV2_USBFSFRAC_MASK; /* Enable USB-OTG IP clocking */ SIM_SCGC4_REG(SIM_BASE_PTR) |= SIM_SCGC4_USBFS_MASK; /* USB D+ and USB D- are standalone not multiplexed one-purpose pins */ /* VREFIN for device is standalone not multiplexed one-purpose pin */ #if BSP_USB_TWR_SER2 /* TWR-SER2 board has 2 connectors: on channel A, there is Micro-USB connector, ** which is not routed to TWRK60 board. On channel B, there is standard ** A-type host connector routed to the USB0 peripheral on TWRK60. To enable ** power to this connector, GPIO PB8 must be set as GPIO output */ PORT_PCR_REG(PORTB_BASE_PTR, 8) = PORT_PCR_MUX(0x01); GPIO_PDDR_REG(PTB_BASE_PTR) |= 0x00000100; // PB8 as output GPIO_PDOR_REG(PTB_BASE_PTR) |= 0x00000100; // PB8 in high level #endif } else if (i == 1) { //Disable MPU so the module can access RAM MPU_CESR &= ~MPU_CESR_VLD_MASK; //Enable clock to the module SIM_SCGC6 |= SIM_SCGC6_USBHS_MASK; // SIM_MCR &= (uint32_t)~0x40000000UL; /* Disconnect internal generated ULPI clock from pin */ // SIM_CLKDIV2 |= SIM_CLKDIV2_USBHSFRAC_MASK | SIM_CLKDIV2_USBHSDIV_MASK; // Divide reference clock to obtain 60MHz // SIM_SOPT2 |= SIM_SOPT2_USBHSRC(1); // MCGPLLCLK for the USB 60MHz CLKC source //Select external clock for USBH controller SIM_SOPT2 |= SIM_SOPT2_USBH_CLKSEL_MASK; PORTA_PCR7 = PORT_PCR_MUX(2); //ULPI DIR PORTA_PCR8 = PORT_PCR_MUX(2); //ULPI NXT PORTA_PCR10 = PORT_PCR_MUX(2); //ULPI DATA0 PORTA_PCR11 = PORT_PCR_MUX(2); //ULPI DATA1 PORTA_PCR24 = PORT_PCR_MUX(2); //ULPI DATA2 PORTA_PCR25 = PORT_PCR_MUX(2); //ULPI DATA3 PORTA_PCR26 = PORT_PCR_MUX(2); //ULPI DATA4 PORTA_PCR27 = PORT_PCR_MUX(2); //ULPI DATA5 PORTA_PCR28 = PORT_PCR_MUX(2); //ULPI DATA6 PORTA_PCR29 = PORT_PCR_MUX(2); //ULPI DATA7 PORTA_PCR6 = PORT_PCR_MUX(2); //ULPI CLK PORTA_PCR9 = PORT_PCR_MUX(2); //ULPI STP } else { return IO_ERROR; //unknow controller } return MQX_OK; }