void zrc_cmd_disc_indication(uint8_t PairingRef)
{
/**
* Reset QT600-Interface board
*/
int i;
RESET_QT600_OFF();
for (i = 0; i < 100 ; i++)
asm("nop");
/* Send back the response */
uint8_t cec_cmds[32];
#if (PAL_GENERIC_TYPE == AVR32)
PGM_READ_BLOCK(cec_cmds, supported_cec_cmds, 32);
#else
PGM_READ_BLOCK(cec_cmds, supported_cec_cmds, 32);
#endif
zrc_cmd_disc_response(PairingRef, cec_cmds);
node_status = IDLE;
#if CHANNEL_AGILITY_ENABLE
/* Enable Channel Agility */
node_status = CH_AGILITY_EXECUTION;
nwk_ch_agility_request(AG_PERIODIC);
#endif
}
static void zrc_cmd_disc_indication(uint8_t PairingRef)
{
/* Send back the response */
uint8_t cec_cmds[32];
PGM_READ_BLOCK(cec_cmds, supported_cec_cmds, 32);
zrc_cmd_disc_response(PairingRef, cec_cmds);
}
/**
* @brief Configures RF according FSK
*
* @param mod_type Modulation order / type; i.e. F2FSK or F4FSK
* @param srate Data rate
* @param mod_idx Modulation index
* @param trx_id Transceiver identifier
*/
retval_t fsk_rfcfg(fsk_mod_type_t mod_type, fsk_data_rate_t srate,
mod_idx_t mod_idx, trx_id_t trx_id)
{
retval_t status = MAC_SUCCESS;
uint16_t reg_offset = RF_BASE_ADDR_OFFSET * trx_id;
uint8_t srate_midx = (srate << 3) + mod_idx;
/* TX configuration: */
/* - PA ramp time + TX-SSBF fcut */
/* - DFE sampling rate reduction + TX-DFE fcut */
{
uint8_t temp[2];
PGM_READ_BLOCK(temp, (uint8_t *)&fsk_params_tbl[srate_midx][0],
2);
rf_blk_write(reg_offset + RG_RF09_TXCUTC, temp, 2);
}
/* - Transmit Power*/
#ifdef IQ_RADIO
pal_dev_reg_write(RF215_RF, reg_offset + RG_RF09_PAC,
((3 <<
PAC_PACUR_SHIFT) |
(DEFAULT_TX_PWR_REG << PAC_TXPWR_SHIFT)));
#else
trx_reg_write(reg_offset + RG_RF09_PAC,
((3 <<
PAC_PACUR_SHIFT) |
(DEFAULT_TX_PWR_REG << PAC_TXPWR_SHIFT)));
#endif
/* RX configuration: */
/* - RX-SSBF bandwidth + RX-SSBF IF shift */
/* - DFE sampling rate reduction + RX-DFE cut-off ratio */
if (trx_id == RF09) {
uint8_t temp[2];
PGM_READ_BLOCK(temp, (uint8_t *)&fsk_params_tbl[srate_midx][5],
2);
rf_blk_write(RG_RF09_RXBWC, temp, 2);
} else {
uint8_t temp[2];
PGM_READ_BLOCK(temp, (uint8_t *)&fsk_params_tbl[srate_midx][7],
2);
rf_blk_write(RG_RF24_RXBWC, temp, 2);
}
/* - AGC input + AGC average period */
/* - AGC target */
{
uint8_t temp[2];
PGM_READ_BLOCK(temp, (uint8_t *)&fsk_params_tbl[srate_midx][9],
2);
rf_blk_write(reg_offset + RG_RF09_AGCC, temp, 2);
}
#ifndef FWNAME
uint8_t agcc = (uint8_t)PGM_READ_BYTE(&fsk_params_tbl[srate_midx][9]);
uint8_t agci = (agcc & AGCC_AGCI_MASK) >> AGCC_AGCI_SHIFT;
uint8_t avgs = (agcc & AGCC_AVGS_MASK) >> AGCC_AVGS_SHIFT;
uint8_t rxdfe;
if (trx_id == RF09) {
rxdfe = (uint8_t)PGM_READ_BYTE(&fsk_params_tbl[srate_midx][6]);
} else {
rxdfe = (uint8_t)PGM_READ_BYTE(&fsk_params_tbl[srate_midx][8]);
}
uint8_t sr = rxdfe & RXDFE_SR_MASK;
tal_pib[trx_id].agc_settle_dur
= get_agc_settling_period(sr, avgs, agci);
#endif
#if (!defined RF215v2)
/* Keep compiler happy */
mod_type = mod_type;
#endif
return status;
}