static void odm_FastAntTrainingInit(struct odm_dm_struct *dm_odm) { struct adapter *adapter = dm_odm->Adapter; u32 value32, i; struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; u32 AntCombination = 2; ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_FastAntTrainingInit()\n")); if (*(dm_odm->mp_mode) == 1) { ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("dm_odm->AntDivType: %d\n", dm_odm->AntDivType)); return; } for (i = 0; i < 6; i++) { dm_fat_tbl->Bssid[i] = 0; dm_fat_tbl->antSumRSSI[i] = 0; dm_fat_tbl->antRSSIcnt[i] = 0; dm_fat_tbl->antAveRSSI[i] = 0; } dm_fat_tbl->TrainIdx = 0; dm_fat_tbl->FAT_State = FAT_NORMAL_STATE; /* MAC Setting */ value32 = PHY_QueryBBReg(adapter, 0x4c, bMaskDWord); PHY_SetBBReg(adapter, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ value32 = PHY_QueryBBReg(adapter, 0x7B4, bMaskDWord); PHY_SetBBReg(adapter, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */ /* Match MAC ADDR */ PHY_SetBBReg(adapter, 0x7b4, 0xFFFF, 0); PHY_SetBBReg(adapter, 0x7b0, bMaskDWord, 0); PHY_SetBBReg(adapter, 0x870, BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */ PHY_SetBBReg(adapter, 0x864, BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */ PHY_SetBBReg(adapter, 0xb2c, BIT22, 0); /* Regb2c[22]=1'b0 disable CS/CG switch */ PHY_SetBBReg(adapter, 0xb2c, BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */ PHY_SetBBReg(adapter, 0xca4, bMaskDWord, 0x000000a0); /* antenna mapping table */ if (AntCombination == 2) { if (!dm_odm->bIsMPChip) { /* testchip */ PHY_SetBBReg(adapter, 0x858, BIT10|BIT9|BIT8, 1); /* Reg858[10:8]=3'b001 */ PHY_SetBBReg(adapter, 0x858, BIT13|BIT12|BIT11, 2); /* Reg858[13:11]=3'b010 */ } else { /* MPchip */ PHY_SetBBReg(adapter, 0x914, bMaskByte0, 1); PHY_SetBBReg(adapter, 0x914, bMaskByte1, 2); } } else if (AntCombination == 7) { if (!dm_odm->bIsMPChip) { /* testchip */ PHY_SetBBReg(adapter, 0x858, BIT10|BIT9|BIT8, 0); /* Reg858[10:8]=3'b000 */ PHY_SetBBReg(adapter, 0x858, BIT13|BIT12|BIT11, 1); /* Reg858[13:11]=3'b001 */ PHY_SetBBReg(adapter, 0x878, BIT16, 0); PHY_SetBBReg(adapter, 0x858, BIT15|BIT14, 2); /* Reg878[0],Reg858[14:15])=3'b010 */ PHY_SetBBReg(adapter, 0x878, BIT19|BIT18|BIT17, 3);/* Reg878[3:1]=3b'011 */ PHY_SetBBReg(adapter, 0x878, BIT22|BIT21|BIT20, 4);/* Reg878[6:4]=3b'100 */ PHY_SetBBReg(adapter, 0x878, BIT25|BIT24|BIT23, 5);/* Reg878[9:7]=3b'101 */ PHY_SetBBReg(adapter, 0x878, BIT28|BIT27|BIT26, 6);/* Reg878[12:10]=3b'110 */ PHY_SetBBReg(adapter, 0x878, BIT31|BIT30|BIT29, 7);/* Reg878[15:13]=3b'111 */ } else { /* MPchip */ PHY_SetBBReg(adapter, 0x914, bMaskByte0, 0); PHY_SetBBReg(adapter, 0x914, bMaskByte1, 1); PHY_SetBBReg(adapter, 0x914, bMaskByte2, 2); PHY_SetBBReg(adapter, 0x914, bMaskByte3, 3); PHY_SetBBReg(adapter, 0x918, bMaskByte0, 4); PHY_SetBBReg(adapter, 0x918, bMaskByte1, 5); PHY_SetBBReg(adapter, 0x918, bMaskByte2, 6); PHY_SetBBReg(adapter, 0x918, bMaskByte3, 7); } } /* Default Ant Setting when no fast training */ PHY_SetBBReg(adapter, 0x80c, BIT21, 1); /* Reg80c[21]=1'b1 from TX Info */ PHY_SetBBReg(adapter, 0x864, BIT5|BIT4|BIT3, 0); /* Default RX */ PHY_SetBBReg(adapter, 0x864, BIT8|BIT7|BIT6, 1); /* Optional RX */ /* Enter Traing state */ PHY_SetBBReg(adapter, 0x864, BIT2|BIT1|BIT0, (AntCombination-1)); /* Reg864[2:0]=3'd6 ant combination=reg864[2:0]+1 */ PHY_SetBBReg(adapter, 0xc50, BIT7, 1); /* RegC50[7]=1'b1 enable HW AntDiv */ }
static void odm_RX_HWAntDivInit(struct odm_dm_struct *dm_odm) { struct adapter *adapter = dm_odm->Adapter; u32 value32; if (*(dm_odm->mp_mode) == 1) { dm_odm->AntDivType = CGCS_RX_SW_ANTDIV; PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); /* disable HW AntDiv */ PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); /* 1:CG, 0:CS */ return; } ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_RX_HWAntDivInit()\n")); /* MAC Setting */ value32 = PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ /* Pin Settings */ PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */ PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */ PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 1); /* Regb2c[22]=1'b0 disable CS/CG switch */ PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */ /* OFDM Settings */ PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0); /* CCK Settings */ PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); /* Fix CCK PHY status report issue */ PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); /* CCK complete HW AntDiv within 64 samples */ ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT); PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201); /* antenna mapping table */ }
VOID rtl8192c_PHY_RF6052SetCckTxPower( IN PADAPTER Adapter, IN u8* pPowerlevel) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; struct dm_priv *pdmpriv = &pHalData->dmpriv; struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; //PMGNT_INFO pMgntInfo=&Adapter->MgntInfo; u32 TxAGC[2]={0, 0}, tmpval=0; BOOLEAN TurboScanOff = _FALSE; u8 idx1, idx2; u8* ptr; // 2010/10/18 MH Accorsing to SD3 eechou's suggestion, we need to disable turbo scan for RU. // Otherwise, external PA will be broken if power index > 0x20. #ifdef CONFIG_USB_HCI if (pHalData->EEPROMRegulatory != 0 || pHalData->ExternalPA) #else if (pHalData->EEPROMRegulatory != 0) #endif { //DbgPrint("TurboScanOff=1 EEPROMRegulatory=%d ExternalPA=%d\n", pHalData->EEPROMRegulatory, pHalData->ExternalPA); TurboScanOff = _TRUE; } if(pmlmeext->sitesurvey_res.state == SCAN_PROCESS) { TxAGC[RF_PATH_A] = 0x3f3f3f3f; TxAGC[RF_PATH_B] = 0x3f3f3f3f; TurboScanOff = _TRUE;//disable turbo scan if(TurboScanOff) { for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++) { TxAGC[idx1] = pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); #ifdef CONFIG_USB_HCI // 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA) TxAGC[idx1] = 0x20; #endif } } } else { // 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. // Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. // In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) { TxAGC[RF_PATH_A] = 0x10101010; TxAGC[RF_PATH_B] = 0x10101010; } else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) { TxAGC[RF_PATH_A] = 0x00000000; TxAGC[RF_PATH_B] = 0x00000000; } else { for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++) { TxAGC[idx1] = pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); } if(pHalData->EEPROMRegulatory==0) { tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) + (pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8); TxAGC[RF_PATH_A] += tmpval; tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][14]) + (pHalData->MCSTxPowerLevelOriginalOffset[0][15]<<24); TxAGC[RF_PATH_B] += tmpval; } } } for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++) { ptr = (u8*)(&(TxAGC[idx1])); for(idx2=0; idx2<4; idx2++) { if(*ptr > RF6052_MAX_TX_PWR) *ptr = RF6052_MAX_TX_PWR; ptr++; } } // rf-A cck tx power tmpval = TxAGC[RF_PATH_A]&0xff; PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_A_CCK1_Mcs32)); tmpval = TxAGC[RF_PATH_A]>>8; PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11)); // rf-B cck tx power tmpval = TxAGC[RF_PATH_B]>>24; PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval); //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11)); tmpval = TxAGC[RF_PATH_B]&0x00ffffff; PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", // tmpval, rTxAGC_B_CCK1_55_Mcs32)); } /* PHY_RF6052SetCckTxPower */
static int phy_RF6052_Config_ParaFile( IN PADAPTER Adapter ) { u32 u4RegValue; u8 eRFPath; BB_REGISTER_DEFINITION_T *pPhyReg; int rtStatus = _SUCCESS; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); static char sz8723RadioAFile[] = RTL8723_PHY_RADIO_A; static char sz8723RadioBFile[] = RTL8723_PHY_RADIO_B; char *pszRadioAFile, *pszRadioBFile; pszRadioAFile = sz8723RadioAFile; pszRadioBFile = sz8723RadioBFile; //3//----------------------------------------------------------------- //3// <2> Initialize RF //3//----------------------------------------------------------------- //for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) { pPhyReg = &pHalData->PHYRegDef[eRFPath]; /*----Store original RFENV control type----*/ switch(eRFPath) { case RF_PATH_A: case RF_PATH_C: u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV); break; case RF_PATH_B : case RF_PATH_D: u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16); break; } /*----Set RF_ENV enable----*/ PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); rtw_udelay_os(1);//PlatformStallExecution(1); /*----Set RF_ENV output high----*/ PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); rtw_udelay_os(1);//PlatformStallExecution(1); /* Set bit number of Address and Data for RF register */ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255 rtw_udelay_os(1);//PlatformStallExecution(1); PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255 rtw_udelay_os(1);//PlatformStallExecution(1); /*----Initialize RF fom connfiguration file----*/ switch(eRFPath) { case RF_PATH_A: #ifdef CONFIG_EMBEDDED_FWIMG #ifdef CONFIG_PHY_SETTING_WITH_ODM if(HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(ODM_RF_RADIO_PATH_E)eRFPath, (ODM_RF_RADIO_PATH_E)eRFPath)) rtStatus= _FAIL; #else rtStatus= rtl8723a_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath); #endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM #else rtStatus = rtl8192c_PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF_RADIO_PATH_E)eRFPath); #endif//#ifdef CONFIG_EMBEDDED_FWIMG break; case RF_PATH_B: #ifdef CONFIG_EMBEDDED_FWIMG #ifdef CONFIG_PHY_SETTING_WITH_ODM if(HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(ODM_RF_RADIO_PATH_E)eRFPath, (ODM_RF_RADIO_PATH_E)eRFPath)) rtStatus= _FAIL; #else rtStatus = rtl8723a_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath); #endif #else rtStatus = rtl8192c_PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF_RADIO_PATH_E)eRFPath); #endif break; case RF_PATH_C: break; case RF_PATH_D: break; } /*----Restore RFENV control type----*/; switch(eRFPath) { case RF_PATH_A: case RF_PATH_C: PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); break; case RF_PATH_B : case RF_PATH_D: PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); break; } if(rtStatus != _SUCCESS){ //RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); goto phy_RF6052_Config_ParaFile_Fail; } } //RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n")); return rtStatus; phy_RF6052_Config_ParaFile_Fail: return rtStatus; }
void rtl8192cd_dfs_det_chk(struct rtl8192cd_priv *priv) { unsigned int regf98_value; unsigned int reg918_value; unsigned int reg91c_value; unsigned int reg920_value; unsigned int reg924_value; unsigned int FA_count_cur=0, FA_count_inc=0; unsigned int VHT_CRC_ok_cnt_cur=0, VHT_CRC_ok_cnt_inc=0; unsigned int HT_CRC_ok_cnt_cur=0, HT_CRC_ok_cnt_inc=0; unsigned int LEG_CRC_ok_cnt_cur=0, LEG_CRC_ok_cnt_inc=0; unsigned int Total_CRC_OK_cnt_inc=0, FA_CRCOK_ratio=0; unsigned char DFS_tri_short_pulse=0, DFS_tri_long_pulse=0, fa_mask_mid_th=0, fa_mask_lower_th=0; unsigned char radar_type = 0; /* 0 for short, 1 for long */ unsigned int short_pulse_cnt_cur=0, short_pulse_cnt_inc=0; unsigned int long_pulse_cnt_cur=0, long_pulse_cnt_inc=0; unsigned int total_pulse_count_inc=0, max_sht_pusle_cnt_th=0; unsigned int sum, k, fa_flag=0; unsigned int st_L2H_new=0, st_L2H_tmp, index=0, fault_flag_det, fault_flag_psd; int flags=0; unsigned long throughput = 0; int j; int i, PSD_report_right[20], PSD_report_left[20]; int max_right, max_left; int max_fa_in_hist=0, total_fa_in_hist=0, pre_post_now_acc_fa_in_hist=0; if (priv->det_asoc_clear > 0) { priv->det_asoc_clear--; priv->pmib->dot11DFSEntry.DFS_detected = 0; priv->FA_count_pre = 0; priv->VHT_CRC_ok_cnt_pre = 0; priv->HT_CRC_ok_cnt_pre = 0; priv->LEG_CRC_ok_cnt_pre = 0; priv->mask_idx = 0; priv->mask_hist_checked = 0; memset(priv->radar_det_mask_hist, 0, sizeof(priv->radar_det_mask_hist)); memset(priv->pulse_flag_hist, 0, sizeof(priv->pulse_flag_hist)); mod_timer(&priv->dfs_det_chk_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(priv->pshare->rf_ft_var.dfs_det_period*10)); return; } throughput = priv->ext_stats.tx_avarage+priv->ext_stats.rx_avarage; #ifdef MBSSID if (priv->pmib->miscEntry.vap_enable) { for (j=0; j<RTL8192CD_NUM_VWLAN; j++) { if (IS_DRV_OPEN(priv->pvap_priv[j])) { throughput += priv->pvap_priv[j]->ext_stats.tx_avarage+priv->pvap_priv[j]->ext_stats.rx_avarage; } } } #endif // Get FA count during past 100ms FA_count_cur = PHY_QueryBBReg(priv, 0xf48, 0x0000ffff); if (priv->FA_count_pre == 0) FA_count_inc = 0; else if (FA_count_cur >= priv->FA_count_pre) FA_count_inc = FA_count_cur - priv->FA_count_pre; else FA_count_inc = FA_count_cur; priv->FA_count_pre = FA_count_cur; priv->fa_inc_hist[priv->mask_idx] = FA_count_inc; for (i=0; i<5; i++) { total_fa_in_hist = total_fa_in_hist + priv->fa_inc_hist[i]; if (priv->fa_inc_hist[i] > max_fa_in_hist) max_fa_in_hist = priv->fa_inc_hist[i]; } if (priv->mask_idx >= priv->pshare->rf_ft_var.dfs_det_flag_offset) index = priv->mask_idx - priv->pshare->rf_ft_var.dfs_det_flag_offset; else index = priv->pshare->rf_ft_var.dfs_det_hist_len + priv->mask_idx - priv->pshare->rf_ft_var.dfs_det_flag_offset; if (index == 0) pre_post_now_acc_fa_in_hist = priv->fa_inc_hist[index] + priv->fa_inc_hist[index+1] + priv->fa_inc_hist[4]; else if (index == 4) pre_post_now_acc_fa_in_hist = priv->fa_inc_hist[index] + priv->fa_inc_hist[0] + priv->fa_inc_hist[index-1]; else pre_post_now_acc_fa_in_hist = priv->fa_inc_hist[index] + priv->fa_inc_hist[index+1] + priv->fa_inc_hist[index-1]; // Get VHT CRC32 ok count during past 100ms VHT_CRC_ok_cnt_cur = PHY_QueryBBReg(priv, 0xf0c, 0x00003fff); if (VHT_CRC_ok_cnt_cur >= priv->VHT_CRC_ok_cnt_pre) VHT_CRC_ok_cnt_inc = VHT_CRC_ok_cnt_cur - priv->VHT_CRC_ok_cnt_pre; else VHT_CRC_ok_cnt_inc = VHT_CRC_ok_cnt_cur; priv->VHT_CRC_ok_cnt_pre = VHT_CRC_ok_cnt_cur; // Get HT CRC32 ok count during past 100ms HT_CRC_ok_cnt_cur = PHY_QueryBBReg(priv, 0xf10, 0x00003fff); if (HT_CRC_ok_cnt_cur >= priv->HT_CRC_ok_cnt_pre) HT_CRC_ok_cnt_inc = HT_CRC_ok_cnt_cur - priv->HT_CRC_ok_cnt_pre; else HT_CRC_ok_cnt_inc = HT_CRC_ok_cnt_cur; priv->HT_CRC_ok_cnt_pre = HT_CRC_ok_cnt_cur; // Get Legacy CRC32 ok count during past 100ms LEG_CRC_ok_cnt_cur = PHY_QueryBBReg(priv, 0xf14, 0x00003fff); if (LEG_CRC_ok_cnt_cur >= priv->LEG_CRC_ok_cnt_pre) LEG_CRC_ok_cnt_inc = LEG_CRC_ok_cnt_cur - priv->LEG_CRC_ok_cnt_pre; else LEG_CRC_ok_cnt_inc = LEG_CRC_ok_cnt_cur; priv->LEG_CRC_ok_cnt_pre = LEG_CRC_ok_cnt_cur; if ((VHT_CRC_ok_cnt_cur == 0x3fff) || (HT_CRC_ok_cnt_cur == 0x3fff) || (LEG_CRC_ok_cnt_cur == 0x3fff)) { PHY_SetBBReg(priv, 0xb58, BIT(0), 1); PHY_SetBBReg(priv, 0xb58, BIT(0), 0); } Total_CRC_OK_cnt_inc = VHT_CRC_ok_cnt_inc + HT_CRC_ok_cnt_inc + LEG_CRC_ok_cnt_inc; // check if the FA occrus frequencly during 100ms // FA_count_inc is divided by Total_CRC_OK_cnt_inc, which helps to distinguish normal trasmission from interference if (Total_CRC_OK_cnt_inc > 0) FA_CRCOK_ratio = FA_count_inc / Total_CRC_OK_cnt_inc; //=====dynamic power threshold (DPT) ======== // Get short pulse count, need carefully handle the counter overflow regf98_value = PHY_QueryBBReg(priv, 0xf98, 0xffffffff); short_pulse_cnt_cur = regf98_value & 0x000000ff; if (short_pulse_cnt_cur >= priv->short_pulse_cnt_pre) short_pulse_cnt_inc = short_pulse_cnt_cur - priv->short_pulse_cnt_pre; else short_pulse_cnt_inc = short_pulse_cnt_cur; priv->short_pulse_cnt_pre = short_pulse_cnt_cur; // Get long pulse count, need carefully handle the counter overflow long_pulse_cnt_cur = (regf98_value & 0x0000ff00) >> 8; if (long_pulse_cnt_cur >= priv->long_pulse_cnt_pre) long_pulse_cnt_inc = long_pulse_cnt_cur - priv->long_pulse_cnt_pre; else long_pulse_cnt_inc = long_pulse_cnt_cur; priv->long_pulse_cnt_pre = long_pulse_cnt_cur; total_pulse_count_inc = short_pulse_cnt_inc + long_pulse_cnt_inc; if (priv->pshare->rf_ft_var.dfs_det_print) { panic_printk("=====================================================================\n"); panic_printk("Total_CRC_OK_cnt_inc[%d] VHT_CRC_ok_cnt_inc[%d] HT_CRC_ok_cnt_inc[%d] LEG_CRC_ok_cnt_inc[%d] FA_count_inc[%d] FA_CRCOK_ratio[%d]\n", Total_CRC_OK_cnt_inc, VHT_CRC_ok_cnt_inc, HT_CRC_ok_cnt_inc, LEG_CRC_ok_cnt_inc, FA_count_inc, FA_CRCOK_ratio); panic_printk("Init_Gain[%x] 0x91c[%x] 0xf98[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n", priv->ini_gain_cur, priv->st_L2H_cur, regf98_value, short_pulse_cnt_inc, long_pulse_cnt_inc); panic_printk("Throughput: %luMbps\n", (throughput>>17)); reg918_value = PHY_QueryBBReg(priv, 0x918, 0xffffffff); reg91c_value = PHY_QueryBBReg(priv, 0x91c, 0xffffffff); reg920_value = PHY_QueryBBReg(priv, 0x920, 0xffffffff); reg924_value = PHY_QueryBBReg(priv, 0x924, 0xffffffff); printk("0x918[%08x] 0x91c[%08x] 0x920[%08x] 0x924[%08x]\n", reg918_value, reg91c_value, reg920_value, reg924_value); }
void mptbt_open_WiFiRF(PADAPTER Adapter) { PHY_SetBBReg(Adapter, 0x824, 0x700000, 0x3); PHY_SetBBReg(Adapter, 0x824, 0xF, 0x2); PHY_SetRFReg(Adapter, RF90_PATH_A, 0x0, 0xF0000, 0x3); }
static int phy_RF6052_Config_ParaFile( PADAPTER Adapter ) { u32 u4RegValue; u8 eRFPath; BB_REGISTER_DEFINITION_T *pPhyReg; int rtStatus = _SUCCESS; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); static char sz88eRadioAFile[] = RTL8188E_PHY_RADIO_A; static char sz88eRadioBFile[] = RTL8188E_PHY_RADIO_B; #ifndef CONFIG_EMBEDDED_FWIMG char *pszRadioAFile, *pszRadioBFile; pszRadioAFile = sz88eRadioAFile; pszRadioBFile = sz88eRadioBFile; #endif /* 3----------------------------------------------------------------- */ /* 3 <2> Initialize RF */ /* 3----------------------------------------------------------------- */ for (eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) { pPhyReg = &pHalData->PHYRegDef[eRFPath]; /*----Store original RFENV control type----*/ switch (eRFPath) { case RF_PATH_A: case RF_PATH_C: u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV); break; case RF_PATH_B : case RF_PATH_D: u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16); break; } /*----Set RF_ENV enable----*/ PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); rtw_udelay_os(1);/* PlatformStallExecution(1); */ /*----Set RF_ENV output high----*/ PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); rtw_udelay_os(1);/* PlatformStallExecution(1); */ /* Set bit number of Address and Data for RF register */ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */ rtw_udelay_os(1);/* PlatformStallExecution(1); */ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */ rtw_udelay_os(1);/* PlatformStallExecution(1); */ /*----Initialize RF fom connfiguration file----*/ switch (eRFPath) { case RF_PATH_A: #ifdef CONFIG_EMBEDDED_FWIMG if (HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(ODM_RF_RADIO_PATH_E)eRFPath, (ODM_RF_RADIO_PATH_E)eRFPath)) rtStatus= _FAIL; #else rtStatus = rtl8188e_PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF_RADIO_PATH_E)eRFPath); #endif/* ifdef CONFIG_EMBEDDED_FWIMG */ break; case RF_PATH_B: #ifdef CONFIG_EMBEDDED_FWIMG if (HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(ODM_RF_RADIO_PATH_E)eRFPath, (ODM_RF_RADIO_PATH_E)eRFPath)) rtStatus= _FAIL; #else rtStatus =rtl8188e_PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF_RADIO_PATH_E)eRFPath); #endif break; case RF_PATH_C: break; case RF_PATH_D: break; } /*----Restore RFENV control type----*/; switch (eRFPath) { case RF_PATH_A: case RF_PATH_C: PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); break; case RF_PATH_B : case RF_PATH_D: PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); break; } if (rtStatus != _SUCCESS) goto phy_RF6052_Config_ParaFile_Fail; } return rtStatus; phy_RF6052_Config_ParaFile_Fail: return rtStatus; }
RT_STATUS phy_RF6052_Config_ParaFile( struct net_device* dev ) { struct r8192_priv *priv = rtllib_priv(dev); u32 u4RegValue = 0; u8 eRFPath; RT_STATUS rtStatus = RT_STATUS_SUCCESS; BB_REGISTER_DEFINITION_T *pPhyReg; for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) { pPhyReg = &priv->PHYRegDef[eRFPath]; /*----Store original RFENV control type----*/ switch(eRFPath) { case RF90_PATH_A: case RF90_PATH_C: u4RegValue = PHY_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV); break; case RF90_PATH_B : case RF90_PATH_D: u4RegValue = PHY_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16); break; } /*----Set RF_ENV enable----*/ PHY_SetBBReg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); udelay(1); /*----Set RF_ENV output high----*/ PHY_SetBBReg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); udelay(1); /* Set bit number of Address and Data for RF register */ PHY_SetBBReg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); udelay(1); PHY_SetBBReg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); udelay(1); /*----Initialize RF fom connfiguration file----*/ switch(eRFPath) { case RF90_PATH_A: #if RTL8190_Download_Firmware_From_Header rtStatus= (PHY_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath) == true)?RT_STATUS_SUCCESS:RT_STATUS_FAILURE; #else rtStatus = (PHY_ConfigRFWithParaFile(dev, szRadioAFile, (RF90_RADIO_PATH_E)eRFPath) == true)?RT_STATUS_SUCCESS:RT_STATUS_FAILURE; #endif break; case RF90_PATH_B: #if RTL8190_Download_Firmware_From_Header rtStatus= (PHY_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath) == true)?RT_STATUS_SUCCESS:RT_STATUS_FAILURE; #else rtStatus = (PHY_ConfigRFWithParaFile(dev, szRadioBFile, (RF90_RADIO_PATH_E)eRFPath) == true)?RT_STATUS_SUCCESS:RT_STATUS_FAILURE; #endif break; case RF90_PATH_C: break; case RF90_PATH_D: break; } /*----Restore RFENV control type----*/; switch(eRFPath) { case RF90_PATH_A: case RF90_PATH_C: PHY_SetBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); break; case RF90_PATH_B : case RF90_PATH_D: PHY_SetBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); break; } if(rtStatus != RT_STATUS_SUCCESS){ RT_TRACE(COMP_INIT, "phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath); goto phy_RF6052_Config_ParaFile_Fail; } } RT_TRACE(COMP_INIT, "<---phy_RF6052_Config_ParaFile()\n"); return rtStatus; phy_RF6052_Config_ParaFile_Fail: return rtStatus; }
VOID odm_PathDiversityAfterLink_92C( IN PADAPTER Adapter ) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; pPD_T pDM_PDTable = &Adapter->DM_PDTable; u1Byte DefaultRespPath=0; if((!(pHalData->CVID_Version==VERSION_1_BEFORE_8703B && IS_92C_SERIAL(pHalData->VersionID))) || (pHalData->PathDivCfg != 1) || (pHalData->eRFPowerState == eRfOff)) { if(pHalData->PathDivCfg == 0) { RT_TRACE( COMP_INIT, DBG_LOUD, ("No ODM_TXPathDiversity()\n")); } else { RT_TRACE( COMP_INIT, DBG_LOUD, ("2T ODM_TXPathDiversity()\n")); } return; } if(!odm_IsConnected_92C(Adapter)) { RT_TRACE( COMP_INIT, DBG_LOUD, ("ODM_TXPathDiversity(): No Connections\n")); return; } if(pDM_PDTable->TrainingState == 0) { RT_TRACE( COMP_INIT, DBG_LOUD, ("ODM_TXPathDiversity() ==>\n")); odm_OFDMTXPathDiversity_92C(Adapter); if((pDM_PDTable->CCKPathDivEnable == TRUE) && (pDM_PDTable->OFDM_Pkt_Cnt < 100)) { //RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=0\n")); if(pDM_PDTable->CCK_Pkt_Cnt > 300) pDM_PDTable->Timer = 20; else if(pDM_PDTable->CCK_Pkt_Cnt > 100) pDM_PDTable->Timer = 60; else pDM_PDTable->Timer = 250; RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: timer=%d\n",pDM_PDTable->Timer)); PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x00); // RX path = PathA pDM_PDTable->TrainingState = 1; pHalData->RSSI_test = TRUE; ODM_SetTimer( pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, pDM_PDTable->Timer); //ms } else { pDM_PDTable->CCKTXPath = pDM_PDTable->OFDMTXPath; DefaultRespPath = pDM_PDTable->OFDMDefaultRespPath; RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_SetRespPath_92C: Skip odm_CCKTXPathDiversity_92C, DefaultRespPath is OFDM\n")); odm_SetRespPath_92C(Adapter, DefaultRespPath); odm_ResetPathDiversity_92C(Adapter); RT_TRACE( COMP_INIT, DBG_LOUD, ("ODM_TXPathDiversity() <==\n")); } } else if(pDM_PDTable->TrainingState == 1) { //RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=1\n")); PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x05); // RX path = PathB pDM_PDTable->TrainingState = 2; ODM_SetTimer( pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, pDM_PDTable->Timer); //ms } else { //RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=2\n")); pDM_PDTable->TrainingState = 0; odm_CCKTXPathDiversity_92C(Adapter); if(pDM_PDTable->OFDM_Pkt_Cnt != 0) { DefaultRespPath = pDM_PDTable->OFDMDefaultRespPath; RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_SetRespPath_92C: DefaultRespPath is OFDM\n")); } else { DefaultRespPath = pDM_PDTable->CCKDefaultRespPath; RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_SetRespPath_92C: DefaultRespPath is CCK\n")); } odm_SetRespPath_92C(Adapter, DefaultRespPath); odm_ResetPathDiversity_92C(Adapter); RT_TRACE( COMP_INIT, DBG_LOUD, ("ODM_TXPathDiversity() <==\n")); } }
void rtl8188e_PHY_RF6052SetCckTxPower( PADAPTER Adapter, u8* pPowerlevel) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; struct dm_priv *pdmpriv = &pHalData->dmpriv; struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; /* PMGNT_INFO pMgntInfo=&Adapter->MgntInfo; */ u32 TxAGC[2]={0, 0}, tmpval=0,pwrtrac_value; bool TurboScanOff = false; u8 idx1, idx2; u8* ptr; u8 direction; /* FOR CE ,must disable turbo scan */ TurboScanOff = true; if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) { TxAGC[RF_PATH_A] = 0x3f3f3f3f; TxAGC[RF_PATH_B] = 0x3f3f3f3f; TurboScanOff = true;/* disable turbo scan */ if (TurboScanOff) { for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++) { TxAGC[idx1] = pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); /* 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. */ if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA) TxAGC[idx1] = 0x20; } } } else { /* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */ /* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */ /* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */ if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) { TxAGC[RF_PATH_A] = 0x10101010; TxAGC[RF_PATH_B] = 0x10101010; } else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) { TxAGC[RF_PATH_A] = 0x00000000; TxAGC[RF_PATH_B] = 0x00000000; } else { for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++) { TxAGC[idx1] = pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); } if (pHalData->EEPROMRegulatory==0) { tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) + (pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8); TxAGC[RF_PATH_A] += tmpval; tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][14]) + (pHalData->MCSTxPowerLevelOriginalOffset[0][15]<<24); TxAGC[RF_PATH_B] += tmpval; } } } for (idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++) { ptr = (u8*)(&(TxAGC[idx1])); for (idx2=0; idx2<4; idx2++) { if (*ptr > RF6052_MAX_TX_PWR) *ptr = RF6052_MAX_TX_PWR; ptr++; } } ODM_TxPwrTrackAdjust88E(&pHalData->odmpriv, 1, &direction, &pwrtrac_value); if (direction == 1) /* Increase TX pwoer */ { TxAGC[0] += pwrtrac_value; TxAGC[1] += pwrtrac_value; } else if (direction == 2) /* Decrease TX pwoer */ { TxAGC[0] -= pwrtrac_value; TxAGC[1] -= pwrtrac_value; } /* rf-A cck tx power */ tmpval = TxAGC[RF_PATH_A]&0xff; PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); tmpval = TxAGC[RF_PATH_A]>>8; PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); /* rf-B cck tx power */ tmpval = TxAGC[RF_PATH_B]>>24; PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval); tmpval = TxAGC[RF_PATH_B]&0x00ffffff; PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); } /* PHY_RF6052SetCckTxPower */
BOOLEAN ODM_PathDiversityBeforeLink92C( //IN PADAPTER Adapter IN PDM_ODM_T pDM_Odm ) { #if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM) PADAPTER Adapter = pDM_Odm->Adapter; HAL_DATA_TYPE* pHalData = NULL; PMGNT_INFO pMgntInfo = NULL; //pSWAT_T pDM_SWAT_Table = &Adapter->DM_SWAT_Table; pPD_T pDM_PDTable = NULL; s1Byte Score = 0; PRT_WLAN_BSS pTmpBssDesc; PRT_WLAN_BSS pTestBssDesc; u1Byte target_chnl = 0; u2Byte index; if (pDM_Odm->Adapter == NULL) //For BSOD when plug/unplug fast. //By YJ,120413 { // The ODM structure is not initialized. return FALSE; } pHalData = GET_HAL_DATA(Adapter); pMgntInfo = &Adapter->MgntInfo; pDM_PDTable = &Adapter->DM_PDTable; // Condition that does not need to use path diversity. if((!(pHalData->CVID_Version==VERSION_1_BEFORE_8703B && IS_92C_SERIAL(pHalData->VersionID))) || (pHalData->PathDivCfg!=1) || pMgntInfo->AntennaTest ) { RT_TRACE(COMP_INIT, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C(): No PathDiv Mechanism before link.\n")); return FALSE; } // Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK); if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect) { PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK); RT_TRACE(COMP_INIT, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C(): RFChangeInProgress(%x), eRFPowerState(%x)\n", pMgntInfo->RFChangeInProgress, pHalData->eRFPowerState)); //pDM_SWAT_Table->SWAS_NoLink_State = 0; pDM_PDTable->PathDiv_NoLink_State = 0; return FALSE; } else { PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK); } //1 Run AntDiv mechanism "Before Link" part. //if(pDM_SWAT_Table->SWAS_NoLink_State == 0) if(pDM_PDTable->PathDiv_NoLink_State == 0) { //1 Prepare to do Scan again to check current antenna state. // Set check state to next step. //pDM_SWAT_Table->SWAS_NoLink_State = 1; pDM_PDTable->PathDiv_NoLink_State = 1; // Copy Current Scan list. Adapter->MgntInfo.tmpNumBssDesc = pMgntInfo->NumBssDesc; PlatformMoveMemory((PVOID)Adapter->MgntInfo.tmpbssDesc, (PVOID)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC); // Switch Antenna to another one. if(pDM_PDTable->DefaultRespPath == 0) { PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x05); // TRX path = PathB odm_SetRespPath_92C(Adapter, 1); pDM_PDTable->OFDMTXPath = 0xFFFFFFFF; pDM_PDTable->CCKTXPath = 0xFFFFFFFF; } else { PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x00); // TRX path = PathA odm_SetRespPath_92C(Adapter, 0); pDM_PDTable->OFDMTXPath = 0x0; pDM_PDTable->CCKTXPath = 0x0; } #if 0 pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna; pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A; RT_TRACE(COMP_INIT, DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Change to Ant(%s) for testing.\n", (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B")); //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna); pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8)); PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860); #endif // Go back to scan function again. RT_TRACE(COMP_INIT, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Scan one more time\n")); pMgntInfo->ScanStep=0; target_chnl = odm_SwAntDivSelectScanChnl(Adapter); odm_SwAntDivConstructScanChnl(Adapter, target_chnl); PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5); return TRUE; } else { //1 ScanComple() is called after antenna swiched. //1 Check scan result and determine which antenna is going //1 to be used. for(index=0; index<Adapter->MgntInfo.tmpNumBssDesc; index++) { pTmpBssDesc = &(Adapter->MgntInfo.tmpbssDesc[index]); pTestBssDesc = &(pMgntInfo->bssDesc[index]); if(PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0) { RT_TRACE(COMP_INIT, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C(): ERROR!! This shall not happen.\n")); continue; } if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower) { RT_TRACE(COMP_INIT, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Compare scan entry: Score++\n")); RT_PRINT_STR(COMP_INIT, DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen); RT_TRACE(COMP_INIT, DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); Score++; PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS)); } else if(pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower) { RT_TRACE(COMP_INIT, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Compare scan entry: Score--\n")); RT_PRINT_STR(COMP_INIT, DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen); RT_TRACE(COMP_INIT, DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); Score--; } } if(pMgntInfo->NumBssDesc!=0 && Score<=0) { RT_TRACE(COMP_INIT, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C(): DefaultRespPath=%d\n", pDM_PDTable->DefaultRespPath)); //pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna; } else { RT_TRACE(COMP_INIT, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C(): DefaultRespPath=%d\n", pDM_PDTable->DefaultRespPath)); if(pDM_PDTable->DefaultRespPath == 0) { pDM_PDTable->OFDMTXPath = 0xFFFFFFFF; pDM_PDTable->CCKTXPath = 0xFFFFFFFF; odm_SetRespPath_92C(Adapter, 1); } else { pDM_PDTable->OFDMTXPath = 0x0; pDM_PDTable->CCKTXPath = 0x0; odm_SetRespPath_92C(Adapter, 0); } PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x01); // RX path = PathAB //pDM_SWAT_Table->CurAntenna = pDM_SWAT_Table->PreAntenna; //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna); //pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8)); //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860); } // Check state reset to default and wait for next time. //pDM_SWAT_Table->SWAS_NoLink_State = 0; pDM_PDTable->PathDiv_NoLink_State = 0; return FALSE; } #else return FALSE; #endif }
static bool rtl8192_radio_on_off_checking(struct net_device *dev) { struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); u8 u1Tmp = 0; u8 gpio; if (priv->pwrdown) { u1Tmp = read_nic_byte(dev, 0x06); gpio = u1Tmp & BIT6; } else #ifdef CONFIG_BT_COEXIST if (pHalData->bt_coexist.BluetoothCoexist) { if (pHalData->bt_coexist.BT_CoexistType == BT_2Wire) { PlatformEFIOWrite1Byte(pAdapter, MAC_PINMUX_CFG, 0xa); u1Tmp = PlatformEFIORead1Byte(pAdapter, GPIO_IO_SEL); delay_us(100); u1Tmp = PlatformEFIORead1Byte(pAdapter, GPIO_IN); RTPRINT(FPWR, PWRHW, ("GPIO_IN=%02x\n", u1Tmp)); retval = (u1Tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? eRfOn : eRfOff; } else if ((pHalData->bt_coexist.BT_CoexistType == BT_ISSC_3Wire) || (pHalData->bt_coexist.BT_CoexistType == BT_Accel) || (pHalData->bt_coexist.BT_CoexistType == BT_CSR_BC4)) { u4tmp = PHY_QueryBBReg(pAdapter, 0x87c, bMaskDWord); if ((u4tmp & BIT17) != 0) { PHY_SetBBReg(pAdapter, 0x87c, bMaskDWord, u4tmp & ~BIT17); delay_us(50); RTPRINT(FBT, BT_RFPoll, ("BT write 0x87c (~BIT17) = 0x%x\n", u4tmp &~BIT17)); } u4tmp = PHY_QueryBBReg(pAdapter, 0x8e0, bMaskDWord); RTPRINT(FBT, BT_RFPoll, ("BT read 0x8e0 (BIT24)= 0x%x\n", u4tmp)); retval = (u4tmp & BIT24) ? eRfOn : eRfOff; RTPRINT(FBT, BT_RFPoll, ("BT check RF state to %s\n", (retval==eRfOn)? "ON":"OFF")); } } else #endif { write_nic_byte(dev, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO)); u1Tmp = read_nic_byte(dev, GPIO_IO_SEL); u1Tmp &= HAL_8192S_HW_GPIO_OFF_MASK; write_nic_byte(dev, GPIO_IO_SEL, u1Tmp); mdelay(10); u1Tmp = read_nic_byte(dev, GPIO_IN); gpio = u1Tmp & HAL_8192S_HW_GPIO_OFF_BIT; } #ifdef DEBUG_RFKILL { static u8 gpio_test; printk("%s: gpio = %x\n", __FUNCTION__, gpio); if(gpio_test % 5 == 0) { gpio = 0; } else { gpio = 1; } printk("%s: gpio_test = %d, gpio = %x\n", __FUNCTION__, gpio_test++ % 20, gpio); } #endif return gpio; }
void Scan_BB_PSD( IN PDM_ODM_T pDM_Odm, int *PSD_report_right, int *PSD_report_left, int len, int initial_gain) { struct rtl8192cd_priv *priv=pDM_Odm->priv; pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; u1Byte ST_TH_origin; u1Byte idx[20]={//96,99,102,106,109,112,115,118,122,125, 224,227,230,234,237,240,243,246,250,253, 0,3,6,10,13,16,19,22,26,29}; int tone_idx, channel_org, channel, i; // set DFS ST_TH to max value ST_TH_origin = RTL_R8(0x91c); RTL_W8(0x91c, 0x4e); // Turn off CCK ODM_SetBBReg(pDM_Odm, 0x808, BIT28, 0); //808[28] // Turn off TX // Pause TX Queue if (!priv->pmib->dot11DFSEntry.disable_tx) ODM_Write1Byte(pDM_Odm, 0x522, 0xFF); //REG_TXPAUSE 改為0x522 // Turn off CCA if(GET_CHIP_VER(priv) == VERSION_8814A){ ODM_SetBBReg(pDM_Odm, 0x838, BIT1, 0x1); //838[1] 設為1 } else{ ODM_SetBBReg(pDM_Odm, 0x838, BIT3, 0x1); //838[3] 設為1 } // PHYTXON while loop PHY_SetBBReg(priv, 0x8fc, 0xfff, 0); i = 0; while (ODM_GetBBReg(pDM_Odm, 0xfa0, BIT18)) { i++; if (i > 1000000) { panic_printk("Wait in %s() more than %d times!\n", __FUNCTION__, i); break; } } // backup IGI_origin , set IGI = 0x3e; pDM_DigTable->bPSDInProgress = TRUE; odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_7, initial_gain); // Turn off 3-wire ODM_SetBBReg(pDM_Odm, 0xC00, BIT1|BIT0, 0x0); //c00[1:0] 寫0 // pts value = 128, 256, 512, 1024 ODM_SetBBReg(pDM_Odm, 0x910, BIT14|BIT15, 0x1); //910[15:14]設為1, 用256點 ODM_SetBBReg(pDM_Odm, 0x910, BIT12|BIT13, 0x1); //910[13:12]設為1, avg 8 次 // scan in-band PSD channel_org = ODM_GetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF); if(priv, priv->pshare->CurrentChannelBW != HT_CHANNEL_WIDTH_20){ priv->pshare->No_RF_Write = 0; SwBWMode(priv, HT_CHANNEL_WIDTH_20, 0); priv->pshare->No_RF_Write = 1; } if (priv->pshare->rf_ft_var.dfs_scan_inband) { int PSD_report_inband[20]; for (tone_idx=0;tone_idx<len;tone_idx++) PSD_report_inband[tone_idx] = GetPSDData_8812(pDM_Odm, idx[tone_idx], initial_gain); panic_printk("PSD inband: "); for (i=0; i<len; i++) panic_printk("%d ", PSD_report_inband[i]); panic_printk("\n"); } // scan right(higher) neighbor channel if (priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_20) channel = channel_org + 4; else if (priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) channel = channel_org + 6; else channel = channel_org + 10; delay_us(300); // for idle 20M, it will emit signal in right 20M channel priv->pshare->No_RF_Write = 0; ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel); priv->pshare->No_RF_Write = 1; for (tone_idx=0;tone_idx<len;tone_idx++) PSD_report_right[tone_idx] = GetPSDData_8812(pDM_Odm, idx[tone_idx], initial_gain); // scan left(lower) neighbor channel if (priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_20) channel = channel_org - 4; else if (priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) channel = channel_org - 6; else channel = channel_org - 10; priv->pshare->No_RF_Write = 0; ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel); priv->pshare->No_RF_Write = 1; for (tone_idx=0;tone_idx<len;tone_idx++) PSD_report_left[tone_idx] = GetPSDData_8812(pDM_Odm, idx[tone_idx], initial_gain); // restore originl center frequency if(priv, priv->pshare->CurrentChannelBW != HT_CHANNEL_WIDTH_20){ priv->pshare->No_RF_Write = 0; SwBWMode(priv, priv->pshare->CurrentChannelBW, priv->pshare->offset_2nd_chan); priv->pshare->No_RF_Write = 1; } priv->pshare->No_RF_Write = 0; ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x3FF, channel_org); priv->pshare->No_RF_Write = 1; // Turn on 3-wire ODM_SetBBReg(pDM_Odm, 0xc00, BIT1|BIT0, 0x3); //c00[1:0] 寫3 // Restore Current Settings // Resume DIG pDM_DigTable->bPSDInProgress = FALSE; odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_7, NONE); //Turn on CCA if(GET_CHIP_VER(priv) == VERSION_8814A){ ODM_SetBBReg(pDM_Odm, 0x838, BIT1, 0); //838[1] 設為0 } else{ ODM_SetBBReg(pDM_Odm, 0x838, BIT3, 0); //838[3] 設為0 } // Turn on TX // Resume TX Queue if (!priv->pmib->dot11DFSEntry.disable_tx) ODM_Write1Byte(pDM_Odm, 0x522, 0x00); //REG_TXPAUSE 改為0x522 // CCK on if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) ODM_SetBBReg(pDM_Odm, 0x808, BIT28, 1); //808[28] // Resume DFS ST_TH RTL_W8(0x91c, ST_TH_origin); }
static void odm_TRX_HWAntDivInit(struct odm_dm_struct *dm_odm) { struct adapter *adapter = dm_odm->Adapter; u32 value32; if (*(dm_odm->mp_mode) == 1) { dm_odm->AntDivType = CGCS_RX_SW_ANTDIV; PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); /* disable HW AntDiv */ PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, 0); /* Default RX (0/1) */ return; } ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_TRX_HWAntDivInit()\n")); /* MAC Setting */ value32 = PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ /* Pin Settings */ PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */ PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */ PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 0); /* Regb2c[22]=1'b0 disable CS/CG switch */ PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */ /* OFDM Settings */ PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0); /* CCK Settings */ PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); /* Fix CCK PHY status report issue */ PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); /* CCK complete HW AntDiv within 64 samples */ /* Tx Settings */ PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 0); /* Reg80c[21]=1'b0 from TX Reg */ ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT); /* antenna mapping table */ if (!dm_odm->bIsMPChip) { /* testchip */ PHY_SetBBReg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT10|BIT9|BIT8, 1); /* Reg858[10:8]=3'b001 */ PHY_SetBBReg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT13|BIT12|BIT11, 2); /* Reg858[13:11]=3'b010 */ } else { /* MPchip */ PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, bMaskDWord, 0x0201); /* Reg914=3'b010, Reg915=3'b001 */ } }
int phy_RF6052_Config_ParaFile( IN PADAPTER Adapter ) { u32 u4RegValue; u8 eRFPath; BB_REGISTER_DEFINITION_T *pPhyReg; int rtStatus = _SUCCESS; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); static u8 sz88CRadioAFile[] = RTL8188C_PHY_RADIO_A; static u8 sz88CRadioBFile[] = RTL8188C_PHY_RADIO_B; #if DEV_BUS_TYPE==DEV_BUS_USB_INTERFACE static u8 sz88CRadioAFile_mCard[] = RTL8188C_PHY_RADIO_A_mCard; static u8 sz88CRadioBFile_mCard[] = RTL8188C_PHY_RADIO_B_mCard; static u8 sz88CRadioAFile_HP[] = RTL8188C_PHY_RADIO_A_HP; #endif static u8 sz92CCRadioAFile[] = RTL8192C_PHY_RADIO_A; static u8 sz92CRadioBFile[] = RTL8192C_PHY_RADIO_B; u8 *pszRadioAFile, *pszRadioBFile; if(IS_92C_SERIAL( pHalData->VersionID))// 88c's IPA is different from 92c's { pszRadioAFile = (u8*)&sz92CCRadioAFile; pszRadioBFile = (u8*)&sz92CRadioBFile; } else{ #if DEV_BUS_TYPE==DEV_BUS_USB_INTERFACE if( BOARD_MINICARD == pHalData->BoardType) { pszRadioAFile = sz88CRadioAFile_mCard; pszRadioBFile = sz88CRadioBFile_mCard; } else if( BOARD_USB_High_PA == pHalData->BoardType) { pszRadioAFile = sz88CRadioAFile_HP; } else #endif { pszRadioAFile = (u8*)&sz88CRadioAFile; pszRadioBFile = (u8*)&sz88CRadioBFile; } } //3//----------------------------------------------------------------- //3// <2> Initialize RF //3//----------------------------------------------------------------- //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) { pPhyReg = &pHalData->PHYRegDef[eRFPath]; /*----Store original RFENV control type----*/ switch(eRFPath) { case RF90_PATH_A: case RF90_PATH_C: u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV); break; case RF90_PATH_B : case RF90_PATH_D: u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16); break; } /*----Set RF_ENV enable----*/ PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); rtw_udelay_os(1);//PlatformStallExecution(1); /*----Set RF_ENV output high----*/ PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); rtw_udelay_os(1);//PlatformStallExecution(1); /* Set bit number of Address and Data for RF register */ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255 rtw_udelay_os(1);//PlatformStallExecution(1); PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255 rtw_udelay_os(1);//PlatformStallExecution(1); /*----Initialize RF fom connfiguration file----*/ switch(eRFPath) { case RF90_PATH_A: #ifdef CONFIG_EMBEDDED_FWIMG rtStatus= PHY_ConfigRFWithHeaderFile(Adapter,(RF90_RADIO_PATH_E)eRFPath); #else rtStatus = PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF90_RADIO_PATH_E)eRFPath); #endif break; case RF90_PATH_B: #ifdef CONFIG_EMBEDDED_FWIMG rtStatus= PHY_ConfigRFWithHeaderFile(Adapter,(RF90_RADIO_PATH_E)eRFPath); #else rtStatus = PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF90_RADIO_PATH_E)eRFPath); #endif break; case RF90_PATH_C: break; case RF90_PATH_D: break; } /*----Restore RFENV control type----*/; switch(eRFPath) { case RF90_PATH_A: case RF90_PATH_C: PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); break; case RF90_PATH_B : case RF90_PATH_D: PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); break; } if(rtStatus != _SUCCESS){ //RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); goto phy_RF6052_Config_ParaFile_Fail; } } //RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n")); return rtStatus; phy_RF6052_Config_ParaFile_Fail: return rtStatus; }
extern void PHY_RF6052SetCckTxPower( struct net_device* dev, u8* pPowerlevel) { struct r8192_priv *priv = rtllib_priv(dev); u32 TxAGC[2]={0, 0}, tmpval=0; bool TurboScanOff=false; u8 idx1, idx2; u8* ptr; if (priv->EEPROMRegulatory != 0) TurboScanOff = true; if(rtllib_act_scanning(priv->rtllib,true) == true) { TxAGC[RF90_PATH_A] = 0x3f3f3f3f; TxAGC[RF90_PATH_B] = 0x3f3f3f3f; if(TurboScanOff) { for(idx1=RF90_PATH_A; idx1<=RF90_PATH_B; idx1++) { TxAGC[idx1] = pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); } } } else { #ifdef ENABLE_DYNAMIC_TXPOWER if(priv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) { TxAGC[RF90_PATH_A] = 0x10101010; TxAGC[RF90_PATH_B] = 0x10101010; } else if(priv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) { TxAGC[RF90_PATH_A] = 0x00000000; TxAGC[RF90_PATH_B] = 0x00000000; } else #endif { for(idx1=RF90_PATH_A; idx1<=RF90_PATH_B; idx1++) { TxAGC[idx1] = pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); } if(priv->EEPROMRegulatory==0) { tmpval = (priv->MCSTxPowerLevelOriginalOffset[0][6]) + (priv->MCSTxPowerLevelOriginalOffset[0][7]<<8); TxAGC[RF90_PATH_A] += tmpval; tmpval = (priv->MCSTxPowerLevelOriginalOffset[0][14]) + (priv->MCSTxPowerLevelOriginalOffset[0][15]<<24); TxAGC[RF90_PATH_B] += tmpval; } } } for(idx1=RF90_PATH_A; idx1<=RF90_PATH_B; idx1++) { ptr = (u8*)(&(TxAGC[idx1])); for(idx2=0; idx2<4; idx2++) { if(*ptr > RF6052_MAX_TX_PWR) *ptr = RF6052_MAX_TX_PWR; ptr++; } } tmpval = TxAGC[RF90_PATH_A]&0xff; PHY_SetBBReg(dev, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_A_CCK1_Mcs32)); tmpval = TxAGC[RF90_PATH_A]>>8; if(priv->rtllib->mode == WIRELESS_MODE_B) tmpval = tmpval & 0xff00ffff; PHY_SetBBReg(dev, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11)); tmpval = TxAGC[RF90_PATH_B]>>24; PHY_SetBBReg(dev, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval); RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11)); tmpval = TxAGC[RF90_PATH_B]&0x00ffffff; PHY_SetBBReg(dev, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK1_55_Mcs32)); } /* PHY_RF6052SetCckTxPower */
static int phy_RF6052_Config_ParaFile( IN PADAPTER Adapter ) { u32 u4RegValue = 0; u8 eRFPath; BB_REGISTER_DEFINITION_T *pPhyReg; int rtStatus = _SUCCESS; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); static char sz8188RadioAFile[] = RTL8188F_PHY_RADIO_A; static char sz8188RadioBFile[] = RTL8188F_PHY_RADIO_B; static s1Byte sz8188FTxPwrTrackFile[] = RTL8188F_TXPWR_TRACK; char *pszRadioAFile, *pszRadioBFile, *pszTxPwrTrackFile; pszRadioAFile = sz8188RadioAFile; pszRadioBFile = sz8188RadioBFile; pszTxPwrTrackFile = sz8188FTxPwrTrackFile; /*3//----------------------------------------------------------------- */ /*3// <2> Initialize RF */ /*3//----------------------------------------------------------------- */ /*for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) */ for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) { pPhyReg = &pHalData->PHYRegDef[eRFPath]; /*----Store original RFENV control type----*/ switch (eRFPath) { case RF_PATH_A: case RF_PATH_C: u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV); break; case RF_PATH_B : case RF_PATH_D: u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV << 16); break; } /*----Set RF_ENV enable----*/ PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1); rtw_udelay_os(1);/*PlatformStallExecution(1); */ /*----Set RF_ENV output high----*/ PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); rtw_udelay_os(1);/*PlatformStallExecution(1); */ /* Set bit number of Address and Data for RF register */ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */ rtw_udelay_os(1);/*PlatformStallExecution(1); */ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */ rtw_udelay_os(1);/*PlatformStallExecution(1); */ /*----Initialize RF fom connfiguration file----*/ switch (eRFPath) { case RF_PATH_A: #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE if (PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, eRFPath) == _FAIL) #endif { #ifdef CONFIG_EMBEDDED_FWIMG if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_RADIO, (ODM_RF_RADIO_PATH_E)eRFPath)) rtStatus = _FAIL; #endif } break; case RF_PATH_B: #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE if (PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, eRFPath) == _FAIL) #endif { #ifdef CONFIG_EMBEDDED_FWIMG if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_RADIO, (ODM_RF_RADIO_PATH_E)eRFPath)) rtStatus = _FAIL; #endif } break; case RF_PATH_C: break; case RF_PATH_D: break; } /*----Restore RFENV control type----*/; switch (eRFPath) { case RF_PATH_A: case RF_PATH_C: PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); break; case RF_PATH_B : case RF_PATH_D: PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV << 16, u4RegValue); break; } if (rtStatus != _SUCCESS) { /*RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); */ goto phy_RF6052_Config_ParaFile_Fail; } } /*3 ----------------------------------------------------------------- */ /*3 Configuration of Tx Power Tracking */ /*3 ----------------------------------------------------------------- */ #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE if (PHY_ConfigRFWithTxPwrTrackParaFile(Adapter, pszTxPwrTrackFile) == _FAIL) #endif { #ifdef CONFIG_EMBEDDED_FWIMG ODM_ConfigRFWithTxPwrTrackHeaderFile(&pHalData->odmpriv); #endif } /*RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n")); */ return rtStatus; phy_RF6052_Config_ParaFile_Fail: return rtStatus; }
VOID rtl8192d_PHY_RF6052SetCckTxPower( IN PADAPTER Adapter, IN u8* pPowerlevel) { HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; u32 TxAGC[2]={0, 0}, tmpval=0; BOOLEAN TurboScanOff = _FALSE; u8 idx1, idx2; u8* ptr; if(pHalData->EEPROMRegulatory != 0) TurboScanOff = _TRUE; if(pmlmeext->sitesurvey_res.state == SCAN_PROCESS) { TxAGC[RF_PATH_A] = 0x3f3f3f3f; TxAGC[RF_PATH_B] = 0x3f3f3f3f; TurboScanOff = _TRUE;//disable Turbo scan if(TurboScanOff) { for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++) { TxAGC[idx1] = pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); } } } else { //vivi merge from 92c, pass win7 DTM item: performance_ext // 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. // Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. // In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. #if 0 if(pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) { TxAGC[RF_PATH_A] = 0x10101010; TxAGC[RF_PATH_B] = 0x10101010; } else if(pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) { TxAGC[RF_PATH_A] = 0x00000000; TxAGC[RF_PATH_B] = 0x00000000; } else #endif { for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++) { TxAGC[idx1] = pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); } if(pHalData->EEPROMRegulatory==0) { tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) + (pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8); TxAGC[RF_PATH_A] += tmpval; tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][14]) + (pHalData->MCSTxPowerLevelOriginalOffset[0][15]<<24); TxAGC[RF_PATH_B] += tmpval; } } } for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++) { ptr = (u8 *)(&(TxAGC[idx1])); for(idx2=0; idx2<4; idx2++) { if(*ptr > RF6052_MAX_TX_PWR) *ptr = RF6052_MAX_TX_PWR; ptr++; } } // rf-A cck tx power tmpval = TxAGC[RF_PATH_A]&0xff; PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_A_CCK1_Mcs32)); tmpval = TxAGC[RF_PATH_A]>>8; PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11)); // rf-B cck tx power tmpval = TxAGC[RF_PATH_B]>>24; PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval); //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11)); tmpval = TxAGC[RF_PATH_B]&0x00ffffff; PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", // tmpval, rTxAGC_B_CCK1_55_Mcs32)); } /* PHY_RF6052SetCckTxPower */
static int phy_RF6052_Config_ParaFile_8192E( IN PADAPTER Adapter ) { u8 eRFPath; int rtStatus = _SUCCESS; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); BB_REGISTER_DEFINITION_T *pPhyReg; static char sz8192ERadioAFile[] = RTL8192E_PHY_RADIO_A; static char sz8192ERadioBFile[] = RTL8192E_PHY_RADIO_B; static char sz8192ETxPwrTrack[] = RTL8192E_TXPWR_TRACK; char *pszRadioAFile = NULL, *pszRadioBFile = NULL, *pszTxPwrTrack = NULL; u32 u4RegValue,MaskforPhySet = 0;; pszRadioAFile = sz8192ERadioAFile; pszRadioBFile = sz8192ERadioBFile; pszTxPwrTrack = sz8192ETxPwrTrack; //3//----------------------------------------------------------------- //3// <2> Initialize RF //3//----------------------------------------------------------------- //for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) { pPhyReg = &pHalData->PHYRegDef[eRFPath]; switch(eRFPath) { case RF_PATH_A: case RF_PATH_C: u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs|MaskforPhySet, bRFSI_RFENV); break; case RF_PATH_B : case RF_PATH_D: u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs|MaskforPhySet, bRFSI_RFENV<<16); break; } /*----Set RF_ENV enable----*/ PHY_SetBBReg(Adapter, pPhyReg->rfintfe|MaskforPhySet, bRFSI_RFENV<<16, 0x1); rtw_udelay_os(1);//PlatformStallExecution(1); /*----Set RF_ENV output high----*/ PHY_SetBBReg(Adapter, pPhyReg->rfintfo|MaskforPhySet, bRFSI_RFENV, 0x1); rtw_udelay_os(1);//PlatformStallExecution(1); /* Set bit number of Address and Data for RF register */ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2|MaskforPhySet, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255 rtw_udelay_os(1);//PlatformStallExecution(1); PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2|MaskforPhySet, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255 rtw_udelay_os(1);//PlatformStallExecution(1); /*----Initialize RF fom connfiguration file----*/ switch(eRFPath) { case RF_PATH_A: #ifdef CONFIG_EMBEDDED_FWIMG if(HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,CONFIG_RF_RADIO, (ODM_RF_RADIO_PATH_E)eRFPath)) rtStatus= _FAIL; #else rtStatus = PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, eRFPath); #endif//#ifdef CONFIG_EMBEDDED_FWIMG break; case RF_PATH_B: #ifdef CONFIG_EMBEDDED_FWIMG if(HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,CONFIG_RF_RADIO, (ODM_RF_RADIO_PATH_E)eRFPath)) rtStatus= _FAIL; #else rtStatus =PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, eRFPath); #endif break; default: break; } /*----Restore RFENV control type----*/; switch(eRFPath) { case RF_PATH_A: case RF_PATH_C: PHY_SetBBReg(Adapter, pPhyReg->rfintfs|MaskforPhySet, bRFSI_RFENV, u4RegValue); break; case RF_PATH_B : case RF_PATH_D: PHY_SetBBReg(Adapter, pPhyReg->rfintfs|MaskforPhySet, bRFSI_RFENV<<16, u4RegValue); break; } if(rtStatus != _SUCCESS){ DBG_871X("%s():Radio[%d] Fail!!", __FUNCTION__, eRFPath); goto phy_RF6052_Config_ParaFile_Fail; } } //3 ----------------------------------------------------------------- //3 Configuration of Tx Power Tracking //3 ----------------------------------------------------------------- #ifdef CONFIG_EMBEDDED_FWIMG ODM_ConfigRFWithTxPwrTrackHeaderFile(&pHalData->odmpriv); #else PHY_ConfigRFWithTxPwrTrackParaFile(Adapter, pszTxPwrTrack); #endif //RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile_8192E()\n")); phy_RF6052_Config_ParaFile_Fail: return rtStatus; }