PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK),
PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK),
PINMUX_GPIO(GPIO_FN_SSI3_WS, SSI3_WS_MARK),
PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK),
PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK),
PINMUX_GPIO(GPIO_FN_SSI3_SDATA, SSI3_SDATA_MARK),
PINMUX_GPIO(GPIO_FN_FSTATUS, FSTATUS_MARK),
PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK),
PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK),
PINMUX_GPIO(GPIO_FN_SSI3_SCK, SSI3_SCK_MARK),
PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) {
PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU }
},
{ PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2) {
PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK),
};
static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) {
PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU,
PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
GPIO_FN(GNT0_GNTIN),
GPIO_FN(REQ0_REQOUT),
GPIO_FN(PERR),
GPIO_FN(SERR),
GPIO_FN(WE7_CBE3),
GPIO_FN(WE6_CBE2),
GPIO_FN(WE5_CBE1),
GPIO_FN(WE4_CBE0),
GPIO_FN(SCIF2_RXD),
GPIO_FN(SIOF_RXD),
GPIO_FN(MRESETOUT),
GPIO_FN(IRQOUT),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2) {
PA7_FN, PA7_OUT, PA7_IN, 0,
PA6_FN, PA6_OUT, PA6_IN, 0,
PA5_FN, PA5_OUT, PA5_IN, 0,
PA4_FN, PA4_OUT, PA4_IN, 0,
PA3_FN, PA3_OUT, PA3_IN, 0,
PA2_FN, PA2_OUT, PA2_IN, 0,
PA1_FN, PA1_OUT, PA1_IN, 0,
PA0_FN, PA0_OUT, PA0_IN, 0 }
},
{ PINMUX_CFG_REG("PBCR", 0xffe70002, 16, 2) {
PB7_FN, PB7_OUT, PB7_IN, 0,
PB6_FN, PB6_OUT, PB6_IN, 0,
PB5_FN, PB5_OUT, PB5_IN, 0,
PB4_FN, PB4_OUT, PB4_IN, 0,
PB3_FN, PB3_OUT, PB3_IN, 0,
PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK),
/* MMC */
PINMUX_GPIO(GPIO_FN_MMC_DAT, MMC_DAT_MARK),
PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK),
PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK),
PINMUX_GPIO(GPIO_FN_MMC_VDDON, MMC_VDDON_MARK),
PINMUX_GPIO(GPIO_FN_MMC_ODMOD, MMC_ODMOD_MARK),
/* SYSC */
PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN,
PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN,
PTA5_FN, PTA5_OUT, PTA5_IN_PU, PTA5_IN,
PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN,
PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN,
PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN,
PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN,
PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN }
},
{ PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
PTB7_FN, PTB7_OUT, PTB7_IN_PU, PTB7_IN,
PTB6_FN, PTB6_OUT, PTB6_IN_PU, PTB6_IN,
PTB5_FN, PTB5_OUT, PTB5_IN_PU, PTB5_IN,
PTB4_FN, PTB4_OUT, PTB4_IN_PU, PTB4_IN,
PTB3_FN, PTB3_OUT, PTB3_IN_PU, PTB3_IN,
GPIO_FN(LCD_DATA11),
GPIO_FN(LCD_DATA10),
GPIO_FN(LCD_DATA9),
GPIO_FN(LCD_DATA8),
GPIO_FN(LCD_DATA7),
GPIO_FN(LCD_DATA6),
GPIO_FN(LCD_DATA5),
GPIO_FN(LCD_DATA4),
GPIO_FN(LCD_DATA3),
GPIO_FN(LCD_DATA2),
GPIO_FN(LCD_DATA1),
GPIO_FN(LCD_DATA0),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1) {
0, 0,
0, 0,
0, 0,
0, 0,
PB11_IN, PB11_OUT,
PB10_IN, PB10_OUT,
PB9_IN, PB9_OUT,
PB8_IN, PB8_OUT,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
0, 0,
static struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) {
PTA7_FN, PTA7_OUT, PTA7_IN, PTA7_IN_PU,
PTA6_FN, PTA6_OUT, PTA6_IN, PTA6_IN_PU,
PTA5_FN, PTA5_OUT, PTA5_IN, PTA5_IN_PU,
PTA4_FN, PTA4_OUT, PTA4_IN, PTA4_IN_PU,
PTA3_FN, PTA3_OUT, PTA3_IN, PTA3_IN_PU,
PTA2_FN, PTA2_OUT, PTA2_IN, PTA2_IN_PU,
PTA1_FN, PTA1_OUT, PTA1_IN, PTA1_IN_PU,
PTA0_FN, PTA0_OUT, PTA0_IN, PTA0_IN_PU
}
},
{ PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2) {
PTB7_FN, PTB7_OUT, PTB7_IN, 0,
PTB6_FN, PTB6_OUT, PTB6_IN, 0,
PTB5_FN, PTB5_OUT, PTB5_IN, 0,
PTB4_FN, PTB4_OUT, PTB4_IN, 0,
PTB3_FN, PTB3_OUT, PTB3_IN, 0,
PTB2_FN, PTB2_OUT, PTB2_IN, 0,
PTB1_FN, PTB1_OUT, PTB1_IN, 0,
PTB0_FN, PTB0_OUT, PTB0_IN, 0
}
},
{ PINMUX_CFG_REG("PCCR", 0xffec0004, 16, 2) {
PTC7_FN, PTC7_OUT, PTC7_IN, 0,
PTC6_FN, PTC6_OUT, PTC6_IN, 0,
PTC5_FN, PTC5_OUT, PTC5_IN, 0,
PTC4_FN, PTC4_OUT, PTC4_IN, 0,
PTC3_FN, PTC3_OUT, PTC3_IN, 0,
PTC2_FN, PTC2_OUT, PTC2_IN, 0,
PTC1_FN, PTC1_OUT, PTC1_IN, 0,
