static int intel_gma_init(struct northbridge_intel_i945_config *conf,
unsigned int pphysbase, unsigned int piobase,
void *pmmio, unsigned int pgfx)
{
struct edid edid;
u8 edid_data[128];
unsigned long temp;
int hpolarity, vpolarity;
u32 candp1, candn;
u32 best_delta = 0xffffffff;
u32 target_frequency;
u32 pixel_p1 = 1;
u32 pixel_n = 1;
u32 pixel_m1 = 1;
u32 pixel_m2 = 1;
u32 hactive, vactive, right_border, bottom_border;
u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;
u32 i, j;
u32 uma_size;
u16 reg16;
printk(BIOS_SPEW,
"i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n",
(void *)pgfx, pmmio, piobase, pphysbase);
intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data, 128);
decode_edid(edid_data, sizeof(edid_data), &edid);
hpolarity = (edid.phsync == '-');
vpolarity = (edid.pvsync == '-');
hactive = edid.x_resolution;
vactive = edid.y_resolution;
right_border = edid.hborder;
bottom_border = edid.vborder;
vblank = edid.vbl;
hblank = edid.hbl;
vsync = edid.vspw;
hsync = edid.hspw;
hfront_porch = edid.hso;
vfront_porch = edid.vso;
for (i = 0; i < 2; i++)
for (j = 0; j < 0x100; j++)
/* R=j, G=j, B=j. */
write32(pmmio + PALETTE(i) + 4 * j, 0x10101 * j);
write32(pmmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
| (read32(pmmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
write32(pmmio + MI_ARB_STATE, MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27));
/* Clean registers. */
for (i = 0; i < 0x20; i += 4)
write32(pmmio + RENDER_RING_BASE + i, 0);
for (i = 0; i < 0x20; i += 4)
write32(pmmio + FENCE_REG_965_0 + i, 0);
write32(pmmio + PP_ON_DELAYS, 0);
write32(pmmio + PP_OFF_DELAYS, 0);
/* Disable VGA. */
write32(pmmio + VGACNTRL, VGA_DISP_DISABLE);
/* Disable pipes. */
write32(pmmio + PIPECONF(0), 0);
write32(pmmio + PIPECONF(1), 0);
/* Init PRB0. */
write32(pmmio + HWS_PGA, 0x352d2000);
write32(pmmio + PRB0_CTL, 0);
write32(pmmio + PRB0_HEAD, 0);
write32(pmmio + PRB0_TAIL, 0);
write32(pmmio + PRB0_START, 0);
write32(pmmio + PRB0_CTL, 0x0001f001);
write32(pmmio + D_STATE, DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING | DSTATE_DOT_CLOCK_GATING);
write32(pmmio + ECOSKPD, 0x00010000);
write32(pmmio + HWSTAM, 0xeffe);
write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug);
write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS);
target_frequency = conf->gpu_lvds_is_dual_channel ? edid.pixel_clock
: (2 * edid.pixel_clock);
/* Find suitable divisors. */
for (candp1 = 1; candp1 <= 8; candp1++) {
for (candn = 5; candn <= 10; candn++) {
u32 cur_frequency;
u32 m; /* 77 - 131. */
u32 denom; /* 35 - 560. */
u32 current_delta;
denom = candn * candp1 * 7;
/* Doesnt overflow for up to
5000000 kHz = 5 GHz. */
m = (target_frequency * denom
+ BASE_FREQUENCY / 2) / BASE_FREQUENCY;
if (m < 77 || m > 131)
continue;
cur_frequency = (BASE_FREQUENCY * m) / denom;
if (target_frequency > cur_frequency)
current_delta = target_frequency - cur_frequency;
else
current_delta = cur_frequency - target_frequency;
if (best_delta > current_delta) {
best_delta = current_delta;
pixel_n = candn;
pixel_p1 = candp1;
pixel_m2 = ((m + 3) % 5) + 7;
pixel_m1 = (m - pixel_m2) / 5;
}
}
}
if (best_delta == 0xffffffff) {
printk (BIOS_ERR, "Couldn't find GFX clock divisors\n");
return -1;
}
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
hactive, vactive);
printk(BIOS_DEBUG, "Borders %d x %d\n", right_border, bottom_border);
printk(BIOS_DEBUG, "Blank %d x %d\n", hblank, vblank);
printk(BIOS_DEBUG, "Sync %d x %d\n", hsync, vsync);
printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch);
printk(BIOS_DEBUG, (conf->gpu_lvds_use_spread_spectrum_clock
? "Spread spectrum clock\n"
: "DREF clock\n"));
printk(BIOS_DEBUG, (conf->gpu_lvds_is_dual_channel
? "Dual channel\n"
: "Single channel\n"));
printk(BIOS_DEBUG, "Polarities %d, %d\n",
hpolarity, vpolarity);
printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
pixel_n, pixel_m1, pixel_m2, pixel_p1);
printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n
/ (pixel_p1 * 7));
#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16));
write32(pmmio + PF_WIN_POS(0), 0);
write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
write32(pmmio + PFIT_CONTROL, PFIT_ENABLE | (1 << PFIT_PIPE_SHIFT) | HORIZ_AUTO_SCALE | VERT_AUTO_SCALE);
#else
/* Disable panel fitter (we're in native resolution). */
write32(pmmio + PF_CTL(0), 0);
write32(pmmio + PF_WIN_SZ(0), 0);
write32(pmmio + PF_WIN_POS(0), 0);
write32(pmmio + PFIT_PGM_RATIOS, 0);
write32(pmmio + PFIT_CONTROL, 0);
#endif
mdelay(1);
write32(pmmio + DSPCNTR(0), DISPPLANE_BGRX888
| DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE);
mdelay(1);
write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS
| (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
write32(pmmio + FP0(1),
((pixel_n - 2) << 16)
| ((pixel_m1 - 2) << 8) | pixel_m2);
write32(pmmio + DPLL(1),
DPLL_VGA_MODE_DIS |
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14)
| (conf->gpu_lvds_use_spread_spectrum_clock
? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV
: 0)
| (pixel_p1 << 16)
| (pixel_p1));
mdelay(1);
write32(pmmio + DPLL(1),
DPLL_VGA_MODE_DIS |
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14)
| ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13)
| (pixel_p1 << 16)
| (pixel_p1));
mdelay(1);
write32(pmmio + HTOTAL(1),
((hactive + right_border + hblank - 1) << 16)
| (hactive - 1));
write32(pmmio + HBLANK(1),
((hactive + right_border + hblank - 1) << 16)
| (hactive + right_border - 1));
write32(pmmio + HSYNC(1),
((hactive + right_border + hfront_porch + hsync - 1) << 16)
| (hactive + right_border + hfront_porch - 1));
write32(pmmio + VTOTAL(1), ((vactive + bottom_border + vblank - 1) << 16)
| (vactive - 1));
write32(pmmio + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16)
| (vactive + bottom_border - 1));
write32(pmmio + VSYNC(1),
(vactive + bottom_border + vfront_porch + vsync - 1)
| (vactive + bottom_border + vfront_porch - 1));
#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
write32(pmmio + PIPESRC(1), (639 << 16) | 399);
#else
write32(pmmio + PIPESRC(1), ((hactive - 1) << 16) | (vactive - 1));
#endif
mdelay(1);
write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16));
write32(pmmio + DSPPOS(0), 0);
/* Backlight init. */
write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK);
write32(pmmio + FW_BLC, 0x011d011a);
write32(pmmio + FW_BLC2, 0x00000102);
write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK);
write32(pmmio + FW_BLC_SELF, 0x0001003f);
write32(pmmio + FW_BLC, 0x011d0109);
write32(pmmio + FW_BLC2, 0x00000102);
write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK);
write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight);
edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
write32(pmmio + DSPADDR(0), 0);
write32(pmmio + DSPSURF(0), 0);
write32(pmmio + DSPSTRIDE(0), edid.bytes_per_line);
write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888
| DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE);
mdelay(1);
write32(pmmio + PIPECONF(1), PIPECONF_ENABLE);
write32(pmmio + LVDS, LVDS_ON
| (hpolarity << 20) | (vpolarity << 21)
| (conf->gpu_lvds_is_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_CLOCK_A_POWERUP_ALL
| LVDS_PIPE(1));
write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
mdelay(1);
write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS
| PANEL_POWER_ON | PANEL_POWER_RESET);
printk (BIOS_DEBUG, "waiting for panel powerup\n");
while (1) {
u32 reg32;
reg32 = read32(pmmio + PP_STATUS);
if ((reg32 & PP_SEQUENCE_MASK) == PP_SEQUENCE_NONE)
break;
}
printk (BIOS_DEBUG, "panel powered up\n");
write32(pmmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
/* Clear interrupts. */
write32(pmmio + DEIIR, 0xffffffff);
write32(pmmio + SDEIIR, 0xffffffff);
write32(pmmio + IIR, 0xffffffff);
write32(pmmio + IMR, 0xffffffff);
write32(pmmio + EIR, 0xffffffff);
if (gtt_setup(pmmio)) {
printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n");
return 0;
}
/* Setup GTT. */
reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
uma_size = 0;
if (!(reg16 & 2)) {
reg16 >>= 4;
reg16 &= 7;
switch (reg16) {
case 1:
uma_size = 1024;
break;
case 3:
uma_size = 8192;
break;
}
printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
}
static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
u8 *mmio, u32 physbase, u16 piobase, u32 lfb)
{
int i;
u8 edid_data[128];
struct edid edid;
struct edid_mode *mode;
u32 hactive, vactive, right_border, bottom_border;
int hpolarity, vpolarity;
u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;
u32 candp1, candn;
u32 best_delta = 0xffffffff;
u32 target_frequency;
u32 pixel_p1 = 1;
u32 pixel_n = 1;
u32 pixel_m1 = 1;
u32 pixel_m2 = 1;
u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000;
u32 data_m1;
u32 data_n1 = 0x00800000;
u32 link_m1;
u32 link_n1 = 0x00080000;
vga_gr_write(0x18, 0);
/* Setup GTT. */
for (i = 0; i < 0x2000; i++)
{
outl((i << 2) | 1, piobase);
outl(physbase + (i << 12) + 1, piobase + 4);
}
write32(mmio + ADPA, 0x40008c18);
write32(mmio + 0x7041c, 0x0);
write32(mmio + _DPLL_B_MD, 0x3);
vga_misc_write(0x67);
const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
0xff
};
vga_cr_write(0x11, 0);
for (i = 0; i <= 0x18; i++)
vga_cr_write(i, cr[i]);
power_port(mmio);
intel_gmbus_read_edid(mmio + GMBUS0, 3, 0x50, edid_data, 128);
decode_edid(edid_data,
sizeof(edid_data), &edid);
mode = &edid.mode;
/* Disable screen memory to prevent garbage from appearing. */
vga_sr_write(1, vga_sr_read(1) | 0x20);
hactive = edid.x_resolution;
vactive = edid.y_resolution;
right_border = mode->hborder;
bottom_border = mode->vborder;
hpolarity = (mode->phsync == '-');
vpolarity = (mode->pvsync == '-');
vsync = mode->vspw;
hsync = mode->hspw;
vblank = mode->vbl;
hblank = mode->hbl;
hfront_porch = mode->hso;
vfront_porch = mode->vso;
target_frequency = mode->lvds_dual_channel ? mode->pixel_clock
: (2 * mode->pixel_clock);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
vga_sr_write(1, 1);
vga_sr_write(0x2, 0xf);
vga_sr_write(0x3, 0x0);
vga_sr_write(0x4, 0xe);
vga_gr_write(0, 0x0);
vga_gr_write(1, 0x0);
vga_gr_write(2, 0x0);
vga_gr_write(3, 0x0);
vga_gr_write(4, 0x0);
vga_gr_write(5, 0x0);
vga_gr_write(6, 0x5);
vga_gr_write(7, 0xf);
vga_gr_write(0x10, 0x1);
vga_gr_write(0x11, 0);
edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
write32(mmio + DSPADDR(0), 0);
write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
write32(mmio + DSPSURF(0), 0);
for (i = 0; i < 0x100; i++)
write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
} else {
vga_textmode_init();
}
/* Find suitable divisors. */
for (candp1 = 1; candp1 <= 8; candp1++) {
for (candn = 5; candn <= 10; candn++) {
u32 cur_frequency;
u32 m; /* 77 - 131. */
u32 denom; /* 35 - 560. */
u32 current_delta;
denom = candn * candp1 * 7;
/* Doesnt overflow for up to
5000000 kHz = 5 GHz. */
m = (target_frequency * denom + 60000) / 120000;
if (m < 77 || m > 131)
continue;
cur_frequency = (120000 * m) / denom;
if (target_frequency > cur_frequency)
current_delta = target_frequency - cur_frequency;
else
current_delta = cur_frequency - target_frequency;
if (best_delta > current_delta) {
best_delta = current_delta;
pixel_n = candn;
pixel_p1 = candp1;
pixel_m2 = ((m + 3) % 5) + 7;
pixel_m1 = (m - pixel_m2) / 5;
}
}
}
if (best_delta == 0xffffffff) {
printk (BIOS_ERR, "Couldn't find GFX clock divisors\n");
return;
}
link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency;
data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock)
/ (link_frequency * 8 * 4);
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
hactive, vactive);
printk(BIOS_DEBUG, "Borders %d x %d\n",
right_border, bottom_border);
printk(BIOS_DEBUG, "Blank %d x %d\n",
hblank, vblank);
printk(BIOS_DEBUG, "Sync %d x %d\n",
hsync, vsync);
printk(BIOS_DEBUG, "Front porch %d x %d\n",
hfront_porch, vfront_porch);
printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock
? "Spread spectrum clock\n" : "DREF clock\n"));
printk(BIOS_DEBUG,
mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
printk(BIOS_DEBUG, "Polarities %d, %d\n",
hpolarity, vpolarity);
printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
data_m1, data_n1);
printk(BIOS_DEBUG, "Link frequency %d kHz\n",
link_frequency);
printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n",
link_m1, link_n1);
printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
pixel_n, pixel_m1, pixel_m2, pixel_p1);
printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
120000 * (5 * pixel_m1 + pixel_m2) / pixel_n
/ (pixel_p1 * 7));
write32(mmio + LVDS,
(hpolarity << 20) | (vpolarity << 21)
| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
mdelay(1);
write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS
| (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
write32(mmio + FP0(0),
((pixel_n - 2) << 16)
| ((pixel_m1 - 2) << 8) | pixel_m2);
write32(mmio + DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14)
| (0x10000 << (pixel_p1 - 1))
| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
| (0x1 << (pixel_p1 - 1)));
mdelay(1);
write32(mmio + DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14)
| (0x10000 << (pixel_p1 - 1))
| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
| (0x1 << (pixel_p1 - 1)));
/* Re-lock the registers. */
write32(mmio + PP_CONTROL,
(read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
write32(mmio + LVDS,
(hpolarity << 20) | (vpolarity << 21)
| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
write32(mmio + HTOTAL(0),
((hactive + right_border + hblank - 1) << 16)
| (hactive - 1));
write32(mmio + HBLANK(0),
((hactive + right_border + hblank - 1) << 16)
| (hactive + right_border - 1));
write32(mmio + HSYNC(0),
((hactive + right_border + hfront_porch + hsync - 1) << 16)
| (hactive + right_border + hfront_porch - 1));
write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
| (vactive - 1));
write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
| (vactive + bottom_border - 1));
write32(mmio + VSYNC(0),
(vactive + bottom_border + vfront_porch + vsync - 1)
| (vactive + bottom_border + vfront_porch - 1));
write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
write32(mmio + PF_WIN_POS(0), 0);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
write32(mmio + PIPESRC(0), ((hactive - 1) << 16)
| (vactive - 1));
write32(mmio + PF_CTL(0), 0);
write32(mmio + PF_WIN_SZ(0), 0);
write32(mmio + PFIT_CONTROL, 0x20000000);
} else {
write32(mmio + PIPESRC(0), (639 << 16) | 399);
write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);
write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
write32(mmio + PFIT_CONTROL, 0xa0000000);
}
mdelay(1);
write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
write32(mmio + PIPE_DATA_N1(0), data_n1);
write32(mmio + PIPE_LINK_M1(0), link_m1);
write32(mmio + PIPE_LINK_N1(0), link_n1);
write32(mmio + 0x000f000c, 0x00002040);
mdelay(1);
write32(mmio + 0x000f000c, 0x00002050);
write32(mmio + 0x00060100, 0x00044000);
mdelay(1);
write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
write32(mmio + 0x000f0008, 0x00000040);
write32(mmio + 0x000f000c, 0x00022050);
write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
write32(mmio + VGACNTRL, 0x22c4008e | VGA_DISP_DISABLE);
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
| DISPPLANE_BGRX888);
mdelay(1);
} else {
write32(mmio + VGACNTRL, 0x22c4008e);
}
write32(mmio + TRANS_HTOTAL(0),
((hactive + right_border + hblank - 1) << 16)
| (hactive - 1));
write32(mmio + TRANS_HBLANK(0),
((hactive + right_border + hblank - 1) << 16)
| (hactive + right_border - 1));
write32(mmio + TRANS_HSYNC(0),
((hactive + right_border + hfront_porch + hsync - 1) << 16)
| (hactive + right_border + hfront_porch - 1));
write32(mmio + TRANS_VTOTAL(0),
((vactive + bottom_border + vblank - 1) << 16)
| (vactive - 1));
write32(mmio + TRANS_VBLANK(0),
((vactive + bottom_border + vblank - 1) << 16)
| (vactive + bottom_border - 1));
write32(mmio + TRANS_VSYNC(0),
(vactive + bottom_border + vfront_porch + vsync - 1)
| (vactive + bottom_border + vfront_porch - 1));
write32(mmio + 0x00060100, 0xb01c4000);
write32(mmio + 0x000f000c, 0xb01a2050);
mdelay(1);
write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
);
write32(mmio + LVDS,
LVDS_PORT_ENABLE
| (hpolarity << 20) | (vpolarity << 21)
| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
/* Enable screen memory. */
vga_sr_write(1, vga_sr_read(1) & ~0x20);
/* Clear interrupts. */
write32(mmio + DEIIR, 0xffffffff);
write32(mmio + SDEIIR, 0xffffffff);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
memset((void *) lfb, 0,
edid.x_resolution * edid.y_resolution * 4);
set_vbe_mode_info_valid(&edid, lfb);
}
}
void runio(struct intel_dp *dp)
{
u8 read_val;
intel_dp_wait_panel_power_control(0xabcd0008);
/* vbios spins at this point. Some haswell weirdness? */
intel_dp_wait_panel_power_control(0xabcd0008);
/* This should be a function like intel_panel_enable_backlight
However, we are not sure how the value 0x3a9 comes up.
It has to do something with PWM frequency */
gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
gtt_write(BLC_PWM_PCH_CTL1,BLM_PCH_PWM_ENABLE);
gtt_write(DEIIR,0x00008000);
intel_dp_wait_reg(DEIIR, 0x00000000);
gtt_write(DSPSTRIDE(dp->plane),dp->stride);
intel_dp_sink_dpms(dp, 0);
intel_dp_get_max_downspread(dp, &read_val);
intel_dp_set_m_n_regs(dp);
intel_dp_set_resolution(dp);
gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
gtt_write(PIPECONF(dp->transcoder),0x00000000);
gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000);
mainboard_set_port_clk_dp(dp);
gtt_write(DSPSTRIDE(dp->plane),dp->stride);
gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_BGRX888);
gtt_write(DEIIR,0x00000080);
gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags);
gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN);
intel_dp_wait_panel_power_control(0xabcd000a);
/* what is this doing? Not sure yet. */
intel_dp_i2c_write(dp, 0x0);
intel_dp_i2c_read(dp, &read_val);
intel_dp_i2c_write(dp, 0x04);
intel_dp_i2c_read(dp, &read_val);
intel_dp_i2c_write(dp, 0x7e);
intel_dp_i2c_read(dp, &read_val);
/* this needs to be a call to a function */
gtt_write(DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x00000091);
gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
gtt_write(DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE | DP_SYNC_VS_HIGH |0x80040091);
/* we may need to move these *after* power well power up and *before* PCH_PP_CONTROL in gma.c */
gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x1<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x0001000a);
gtt_write(PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_LVDS |(/* PANEL_POWER_UP_DELAY_MASK */0x7d0<<16)|(/* PANEL_LIGHT_ON_DELAY_MASK */0xa<<0)|0x07d0000a);
intel_dp_set_bw(dp);
intel_dp_set_lane_count(dp);
mainboard_train_link(dp);
/* need a function: intel_ddi_set_tp or similar */
gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_IDLE);
gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_NORMAL);
gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
/* some of this is not needed. */
gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE );
gtt_write(SDEIIR,0x00000000);
gtt_write(DEIIR,0x00000000);
gtt_write(DEIIR,0x00008000);
intel_dp_wait_reg(DEIIR, 0x00000000);
gtt_write(DSPSTRIDE(dp->plane),dp->stride);
gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
gtt_write(DEIIR,0x00000080);
intel_dp_wait_reg(DEIIR, 0x00000000);
gtt_write(DSPSTRIDE(dp->plane),dp->stride);
gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON);
gtt_write(SDEIIR,0x00000000);
gtt_write(SDEIIR,0x00000000);
gtt_write(DEIIR,0x00000000);
}
/**
* intel_vgpu_decode_primary_plane - Decode primary plane
* @vgpu: input vgpu
* @plane: primary plane to save decoded info
* This function is called for decoding plane
*
* Returns:
* 0 on success, non-zero if failed.
*/
int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
struct intel_vgpu_primary_plane_format *plane)
{
u32 val, fmt;
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
int pipe;
pipe = get_active_pipe(vgpu);
if (pipe >= I915_MAX_PIPES)
return -ENODEV;
val = vgpu_vreg_t(vgpu, DSPCNTR(pipe));
plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
if (!plane->enabled)
return -ENODEV;
if (IS_SKYLAKE(dev_priv)
|| IS_KABYLAKE(dev_priv)
|| IS_BROXTON(dev_priv)) {
plane->tiled = val & PLANE_CTL_TILED_MASK;
fmt = skl_format_to_drm(
val & PLANE_CTL_FORMAT_MASK,
val & PLANE_CTL_ORDER_RGBX,
val & PLANE_CTL_ALPHA_MASK,
val & PLANE_CTL_YUV422_ORDER_MASK);
if (fmt >= ARRAY_SIZE(skl_pixel_formats)) {
gvt_vgpu_err("Out-of-bounds pixel format index\n");
return -EINVAL;
}
plane->bpp = skl_pixel_formats[fmt].bpp;
plane->drm_format = skl_pixel_formats[fmt].drm_format;
} else {
plane->tiled = val & DISPPLANE_TILED;
fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK);
plane->bpp = bdw_pixel_formats[fmt].bpp;
plane->drm_format = bdw_pixel_formats[fmt].drm_format;
}
if (!plane->bpp) {
gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
return -EINVAL;
}
plane->hw_format = fmt;
plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK;
if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0))
return -EINVAL;
plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
gvt_vgpu_err("Translate primary plane gma 0x%x to gpa fail\n",
plane->base);
return -EINVAL;
}
plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,
(IS_SKYLAKE(dev_priv)
|| IS_KABYLAKE(dev_priv)
|| IS_BROXTON(dev_priv)) ?
(_PRI_PLANE_STRIDE_MASK >> 6) :
_PRI_PLANE_STRIDE_MASK, plane->bpp);
plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>
_PIPE_H_SRCSZ_SHIFT;
plane->width += 1;
plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) &
_PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
plane->height += 1; /* raw height is one minus the real value */
val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe));
plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
_PRI_PLANE_X_OFF_SHIFT;
plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
_PRI_PLANE_Y_OFF_SHIFT;
return 0;
}
static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
u8 *mmio, u32 physbase, u16 piobase, u32 lfb)
{
int i;
u8 edid_data[128];
struct edid edid;
struct edid_mode *mode;
u8 edid_is_found;
/* Initialise mode variables for 640 x 480 @ 60Hz */
u32 hactive = 640, vactive = 480;
u32 right_border = 0, bottom_border = 0;
int hpolarity = 0, vpolarity = 0;
u32 hsync = 96, vsync = 2;
u32 hblank = 160, vblank = 45;
u32 hfront_porch = 16, vfront_porch = 10;
u32 target_frequency = 25175;
u32 err_most = 0xffffffff;
u32 pixel_p1 = 1;
u32 pixel_p2;
u32 pixel_n = 1;
u32 pixel_m1 = 1;
u32 pixel_m2 = 1;
vga_gr_write(0x18, 0);
/* Set up GTT */
for (i = 0; i < 0x1000; i++) {
outl((i << 2) | 1, piobase);
outl(physbase + (i << 12) + 1, piobase + 4);
}
write32(mmio + VGA0, 0x31108);
write32(mmio + VGA1, 0x31406);
write32(mmio + ADPA, ADPA_DAC_ENABLE
| ADPA_PIPE_A_SELECT
| ADPA_CRT_HOTPLUG_MONITOR_COLOR
| ADPA_CRT_HOTPLUG_ENABLE
| ADPA_USE_VGA_HVPOLARITY
| ADPA_VSYNC_CNTL_ENABLE
| ADPA_HSYNC_CNTL_ENABLE
| ADPA_DPMS_ON
);
write32(mmio + 0x7041c, 0x0);
write32(mmio + DPLL_MD(0), 0x3);
write32(mmio + DPLL_MD(1), 0x3);
vga_misc_write(0x67);
const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
0xff
};
vga_cr_write(0x11, 0);
for (i = 0; i <= 0x18; i++)
vga_cr_write(i, cr[i]);
udelay(1);
intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data,
sizeof(edid_data));
intel_gmbus_stop(mmio + GMBUS0);
decode_edid(edid_data,
sizeof(edid_data), &edid);
mode = &edid.mode;
/* Disable screen memory to prevent garbage from appearing. */
vga_sr_write(1, vga_sr_read(1) | 0x20);
edid_is_found = edid_is_present(edid_data, sizeof(edid_data));
if (edid_is_found) {
printk(BIOS_DEBUG, "EDID is not null");
hactive = edid.x_resolution;
vactive = edid.y_resolution;
right_border = mode->hborder;
bottom_border = mode->vborder;
hpolarity = (mode->phsync == '-');
vpolarity = (mode->pvsync == '-');
vsync = mode->vspw;
hsync = mode->hspw;
vblank = mode->vbl;
hblank = mode->hbl;
hfront_porch = mode->hso;
vfront_porch = mode->vso;
target_frequency = mode->pixel_clock;
} else
printk(BIOS_DEBUG, "EDID is null, using 640 x 480 @ 60Hz mode");
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
vga_sr_write(1, 1);
vga_sr_write(0x2, 0xf);
vga_sr_write(0x3, 0x0);
vga_sr_write(0x4, 0xe);
vga_gr_write(0, 0x0);
vga_gr_write(1, 0x0);
vga_gr_write(2, 0x0);
vga_gr_write(3, 0x0);
vga_gr_write(4, 0x0);
vga_gr_write(5, 0x0);
vga_gr_write(6, 0x5);
vga_gr_write(7, 0xf);
vga_gr_write(0x10, 0x1);
vga_gr_write(0x11, 0);
edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
| DISPPLANE_BGRX888);
write32(mmio + DSPADDR(0), 0);
write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
write32(mmio + DSPSURF(0), 0);
for (i = 0; i < 0x100; i++)
write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
} else {
vga_textmode_init();
}
pixel_p2 = target_frequency <= 225000 ? 10 : 5;
u32 candn, candm1, candm2, candp1;
for (candn = 1; candn <= 4; candn++) {
for (candm1 = 23; candm1 >= 16; candm1--) {
for (candm2 = 11; candm2 >= 5; candm2--) {
for (candp1 = 8; candp1 >= 1; candp1--) {
u32 m = 5 * (candm1 + 2) + (candm2 + 2);
u32 p = candp1 * pixel_p2;
u32 vco = DIV_ROUND_CLOSEST(
BASE_FREQUENCY * m, candn + 2);
u32 dot = DIV_ROUND_CLOSEST(vco, p);
u32 this_err = MAX(dot, target_frequency) -
MIN(dot, target_frequency);
if (this_err < err_most) {
err_most = this_err;
pixel_n = candn;
pixel_m1 = candm1;
pixel_m2 = candm2;
pixel_p1 = candp1;
}
}
}
}
}
if (err_most == 0xffffffff) {
printk(BIOS_ERR, "Couldn't find GFX clock divisors\n");
return;
}
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
hactive, vactive);
printk(BIOS_DEBUG, "Borders %d x %d\n",
right_border, bottom_border);
printk(BIOS_DEBUG, "Blank %d x %d\n",
hblank, vblank);
printk(BIOS_DEBUG, "Sync %d x %d\n",
hsync, vsync);
printk(BIOS_DEBUG, "Front porch %d x %d\n",
hfront_porch, vfront_porch);
printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock
? "Spread spectrum clock\n" : "DREF clock\n"));
printk(BIOS_DEBUG, "Polarities %d, %d\n",
hpolarity, vpolarity);
printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n",
pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2);
printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) /
(pixel_n + 2) / (pixel_p1 * pixel_p2));
mdelay(1);
write32(mmio + FP0(0), (pixel_n << 16)
| (pixel_m1 << 8) | pixel_m2);
write32(mmio + DPLL(0), DPLL_VCO_ENABLE
| DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL
| (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 :
DPLL_DAC_SERIAL_P2_CLOCK_DIV_5)
| (0x10000 << (pixel_p1 - 1))
| (6 << 9));
mdelay(1);
write32(mmio + DPLL(0), DPLL_VCO_ENABLE
| DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL
| (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 :
DPLL_DAC_SERIAL_P2_CLOCK_DIV_5)
| (0x10000 << (pixel_p1 - 1))
| (6 << 9));
write32(mmio + ADPA, ADPA_DAC_ENABLE
| ADPA_PIPE_A_SELECT
| ADPA_CRT_HOTPLUG_MONITOR_COLOR
| ADPA_CRT_HOTPLUG_ENABLE
| ADPA_VSYNC_CNTL_ENABLE
| ADPA_HSYNC_CNTL_ENABLE
| ADPA_DPMS_ON
| (vpolarity ? ADPA_VSYNC_ACTIVE_LOW :
ADPA_VSYNC_ACTIVE_HIGH)
| (hpolarity ? ADPA_HSYNC_ACTIVE_LOW :
ADPA_HSYNC_ACTIVE_HIGH));
write32(mmio + HTOTAL(0),
((hactive + right_border + hblank - 1) << 16)
| (hactive - 1));
write32(mmio + HBLANK(0),
((hactive + right_border + hblank - 1) << 16)
| (hactive + right_border - 1));
write32(mmio + HSYNC(0),
((hactive + right_border + hfront_porch + hsync - 1) << 16)
| (hactive + right_border + hfront_porch - 1));
write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
| (vactive - 1));
write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
| (vactive + bottom_border - 1));
write32(mmio + VSYNC(0),
((vactive + bottom_border + vfront_porch + vsync - 1) << 16)
| (vactive + bottom_border + vfront_porch - 1));
write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
write32(mmio + PF_WIN_POS(0), 0);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
write32(mmio + PIPESRC(0), ((hactive - 1) << 16)
| (vactive - 1));
write32(mmio + PF_CTL(0), 0);
write32(mmio + PF_WIN_SZ(0), 0);
write32(mmio + PFIT_CONTROL, 0);
} else {
write32(mmio + PIPESRC(0), (639 << 16) | 399);
write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);
write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
write32(mmio + PFIT_CONTROL, 0x80000000);
}
mdelay(1);
write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
write32(mmio + PIPECONF(0), PIPECONF_ENABLE
| PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
| DISPPLANE_BGRX888);
mdelay(1);
} else {
write32(mmio + VGACNTRL, 0xc4008e);
}
write32(mmio + ADPA, ADPA_DAC_ENABLE
| ADPA_PIPE_A_SELECT
| ADPA_CRT_HOTPLUG_MONITOR_COLOR
| ADPA_CRT_HOTPLUG_ENABLE
| ADPA_VSYNC_CNTL_ENABLE
| ADPA_HSYNC_CNTL_ENABLE
| ADPA_DPMS_ON
| (vpolarity ? ADPA_VSYNC_ACTIVE_LOW :
ADPA_VSYNC_ACTIVE_HIGH)
| (hpolarity ? ADPA_HSYNC_ACTIVE_LOW :
ADPA_HSYNC_ACTIVE_HIGH));
write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
/* Enable screen memory. */
vga_sr_write(1, vga_sr_read(1) & ~0x20);
/* Clear interrupts. */
write32(mmio + DEIIR, 0xffffffff);
write32(mmio + SDEIIR, 0xffffffff);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
memset((void *) lfb, 0,
hactive * vactive * 4);
set_vbe_mode_info_valid(&edid, lfb);
}
}
static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
struct device *vga, u8 *mmio, u8 *gtt, u32 physbase, u16 piobase)
{
int i;
u32 hactive, vactive;
u32 temp;
printk(BIOS_SPEW, "gtt %x mmio %x addrport %x physbase %x\n",
(u32)gtt, (u32)mmio, piobase, physbase);
gtt_setup(mmio);
pci_write_config16(vga, 0x52, 0x130);
/* Disable VGA. */
write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
/* Disable pipes. */
write32(mmio + PIPECONF(0), 0);
write32(mmio + PIPECONF(1), 0);
write32(mmio + INSTPM, 0x800);
vga_gr_write(0x18, 0);
write32(mmio + VGA0, 0x200074);
write32(mmio + VGA1, 0x200074);
write32(mmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN);
write32(mmio + DSPCLK_GATE_D, 0);
write32(mmio + FW_BLC, 0x03060106);
write32(mmio + FW_BLC2, 0x00000306);
write32(mmio + ADPA, ADPA_DAC_ENABLE
| ADPA_PIPE_A_SELECT
| ADPA_HOTPLUG_BITS
| ADPA_USE_VGA_HVPOLARITY
| ADPA_VSYNC_CNTL_ENABLE
| ADPA_HSYNC_CNTL_ENABLE
| ADPA_DPMS_ON
);
write32(mmio + 0x7041c, 0x0);
write32(mmio + DPLL_MD(0), 0x3);
write32(mmio + DPLL_MD(1), 0x3);
write32(mmio + DSPCNTR(1), 0x1000000);
write32(mmio + PIPESRC(1), 0x027f01df);
vga_misc_write(0x67);
const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
0xff
};
vga_cr_write(0x11, 0);
for (i = 0; i <= 0x18; i++)
vga_cr_write(i, cr[i]);
// Disable screen memory to prevent garbage from appearing.
vga_sr_write(1, vga_sr_read(1) | 0x20);
hactive = 640;
vactive = 400;
mdelay(1);
write32(mmio + DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
| DPLL_VGA_MODE_DIS
| DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
| 0x400601
);
mdelay(1);
write32(mmio + DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
| DPLL_VGA_MODE_DIS
| DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
| 0x400601
);
write32(mmio + ADPA, ADPA_DAC_ENABLE
| ADPA_PIPE_A_SELECT
| ADPA_HOTPLUG_BITS
| ADPA_USE_VGA_HVPOLARITY
| ADPA_VSYNC_CNTL_ENABLE
| ADPA_HSYNC_CNTL_ENABLE
| ADPA_DPMS_ON
);
write32(mmio + HTOTAL(1), 0x031f027f);
write32(mmio + HBLANK(1), 0x03170287);
write32(mmio + HSYNC(1), 0x02ef028f);
write32(mmio + VTOTAL(1), 0x020c01df);
write32(mmio + VBLANK(1), 0x020401e7);
write32(mmio + VSYNC(1), 0x01eb01e9);
write32(mmio + HTOTAL(0),
((hactive - 1) << 16)
| (hactive - 1));
write32(mmio + HBLANK(0),
((hactive - 1) << 16)
| (hactive - 1));
write32(mmio + HSYNC(0),
((hactive - 1) << 16)
| (hactive - 1));
write32(mmio + VTOTAL(0), ((vactive - 1) << 16)
| (vactive - 1));
write32(mmio + VBLANK(0), ((vactive - 1) << 16)
| (vactive - 1));
write32(mmio + VSYNC(0),
((vactive - 1) << 16)
| (vactive - 1));
write32(mmio + PF_WIN_POS(0), 0);
write32(mmio + PIPESRC(0), (639 << 16) | 399);
write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
write32(mmio + PFIT_CONTROL, 0x0);
mdelay(1);
write32(mmio + FDI_RX_CTL(0), 0x00002040);
mdelay(1);
write32(mmio + FDI_RX_CTL(0), 0x80002050);
write32(mmio + FDI_TX_CTL(0), 0x00044000);
mdelay(1);
write32(mmio + FDI_TX_CTL(0), 0x80044000);
write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
write32(mmio + VGACNTRL, 0x0);
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
mdelay(1);
write32(mmio + ADPA, ADPA_DAC_ENABLE
| ADPA_PIPE_A_SELECT
| ADPA_HOTPLUG_BITS
| ADPA_USE_VGA_HVPOLARITY
| ADPA_VSYNC_CNTL_ENABLE
| ADPA_HSYNC_CNTL_ENABLE
| ADPA_DPMS_ON
);
write32(mmio + DSPFW3, 0x7f3f00c1);
write32(mmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH);
write32(mmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5));
write32(mmio + CACHE_MODE_1, 0x380 & ~(1 << 9));
for (i = 0; i < (8192 - 512) / 4; i++) {
outl((i << 2) | 1, piobase);
outl(physbase + (i << 12) + 1, piobase + 4);
}
temp = read32(mmio + PGETBL_CTL);
printk(BIOS_INFO, "GTT PGETBL_CTL register : 0x%08x\n", temp);
temp = read32(mmio + PGETBL2_CTL);
printk(BIOS_INFO, "GTT PGETBL2_CTL register: 0x%08x\n", temp);
/* Clear interrupts. */
write32(mmio + DEIIR, 0xffffffff);
write32(mmio + SDEIIR, 0xffffffff);
write32(mmio + IIR, 0xffffffff);
write32(mmio + IMR, 0xffffffff);
write32(mmio + EIR, 0xffffffff);
vga_textmode_init();
/* Enable screen memory. */
vga_sr_write(1, vga_sr_read(1) & ~0x20);
}
