void sch4037_early_init(unsigned port) { pnp_devfn_t dev; dev = PNP_DEV(port, SMSCSUPERIO_SP1); pnp_enter_conf_state(dev); /* Auto power management */ pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */ pnp_write_config(dev, 0x23, 0); /* Enable SMSC UART 0 */ dev = PNP_DEV(port, SMSCSUPERIO_SP1); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4); /* Enabled High speed, disabled MIDI support. */ pnp_write_config(dev, 0xF0, 0x02); pnp_set_enable(dev, 1); /* Enable keyboard */ dev = PNP_DEV(port, SCH4037_KBC); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ pnp_set_enable(dev, 1); pnp_exit_conf_state(dev); }
void mainboard_config_superio(void) { const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1); const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); const pnp_devfn_t IR_DEV = PNP_DEV(0x2e, NCT6776_SP2); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); /* Select HWM/LED functions instead of floppy functions. */ pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03); pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24); /* Power RAM in S3 and let the PCH handle power failure actions. */ pnp_set_logical_device(ACPI_DEV); pnp_write_config(ACPI_DEV, 0xe4, 0x70); /* * Don't know what's needed here, just set the same as the vendor * firmware. */ pnp_set_logical_device(IR_DEV); pnp_write_config(IR_DEV, 0xf1, 0x5c); nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); }
int board_early_init_f(void) { lpc47m_enable_serial(PNP_DEV(LPC47M_IO_PORT, LPC47M_SP1), UART0_BASE, UART0_IRQ); lpc47m_enable_kbc(PNP_DEV(LPC47M_IO_PORT, LPC47M_KBC), KBD_IRQ, MSE_IRQ); return 0; }
static void early_superio_config(void) { device_t dev; dev=PNP_DEV(0x2e, 0x00); pnp_enter_ext_func_mode(dev); pnp_write_register(dev, 0x01, 0x94); // Extended Parport modes pnp_write_register(dev, 0x02, 0x88); // UART power on pnp_write_register(dev, 0x03, 0x72); // Floppy pnp_write_register(dev, 0x04, 0x01); // EPP + SPP pnp_write_register(dev, 0x14, 0x03); // Floppy pnp_write_register(dev, 0x20, (0x3f0 >> 2)); // Floppy pnp_write_register(dev, 0x23, (0x378 >> 2)); // PP base pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base pnp_write_register(dev, 0x25, (0x2f8 >> 2)); // UART2 base pnp_write_register(dev, 0x26, (2 << 4) | 0); // FDC + PP DMA pnp_write_register(dev, 0x27, (6 << 4) | 7); // FDC + PP DMA pnp_write_register(dev, 0x28, (4 << 4) | 3); // UART1,2 IRQ /* These are the SMI status registers in the SIO: */ pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base pnp_write_register(dev, 0x31, 0x00); // GPIO1 DIR pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL pnp_write_register(dev, 0x33, 0x40); // GPIO2 DIR pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL pnp_write_register(dev, 0x35, 0xff); // GPIO3 DIR pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL pnp_write_register(dev, 0x37, 0xe0); // GPIO4 DIR pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL pnp_write_register(dev, 0x39, 0x80); // GPIO4 POL pnp_exit_ext_func_mode(dev); }
void main(unsigned long bist) { if (bist == 0) enable_lapic(); i5000_lpc_config(); w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); early_config(); setup_gpio(); enable_smbus(); /* setup PCIe MMCONF base address */ pci_write_config32(PCI_DEV(0, 16, 0), 0x64, CONFIG_MMCONF_BASE_ADDRESS >> 16); smbus_write_byte(0x6f, 0x00, 0x63); smbus_write_byte(0x6f, 0x01, 0x04); smbus_write_byte(0x6f, 0x02, 0x53); smbus_write_byte(0x6f, 0x03, 0x39); smbus_write_byte(0x6f, 0x08, 0x06); smbus_write_byte(0x6f, 0x09, 0x00); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1); i5000_fbdimm_init(); smbus_write_byte(0x69, 0x01, 0x01); }
void mainboard_romstage_entry(unsigned long bist) { if (bist == 0) enable_lapic(); i5000_lpc_config(); winbond_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); early_config(); setup_gpio(); enable_smbus(); smbus_write_byte(0x6f, 0x00, 0x63); smbus_write_byte(0x6f, 0x01, 0x04); smbus_write_byte(0x6f, 0x02, 0x53); smbus_write_byte(0x6f, 0x03, 0x39); smbus_write_byte(0x6f, 0x08, 0x06); smbus_write_byte(0x6f, 0x09, 0x00); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1); i5000_fbdimm_init(); smbus_write_byte(0x69, 0x01, 0x01); }
static void wilco_ec_serial_init(void) { pnp_devfn_t dev = PNP_DEV(PNP_CFG_IDX, PNP_LDN_SERIAL); pnp_enter_conf_state(dev); pnp_set_logical_device(dev); pnp_set_enable(dev, 1); pnp_set_iobase(dev, PNP_IDX_IO1, cpu_to_be16(CONFIG_TTYS0_BASE)); pnp_write_config(dev, PNP_IDX_IO0, 1); pnp_exit_conf_state(dev); }
static inline void kbc1100_early_init(unsigned port) { device_t dev; dev = PNP_DEV (port, KBC1100_KBC); pnp_enter_conf_state(dev); /* Serial IRQ enabled */ outb(0x25, port); outb(0x04, port + 1); /* Enable SMSC UART 0 */ dev = PNP_DEV (port, SMSCSUPERIO_SP1); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); pnp_set_enable(dev, 1); /* Enable keyboard */ dev = PNP_DEV (port, KBC1100_KBC); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ pnp_set_enable(dev, 1); /* Enable EC Channel 0 */ dev = PNP_DEV (port, KBC1100_EC0); pnp_set_logical_device(dev); pnp_set_enable(dev, 1); pnp_exit_conf_state(dev); /* disable the 1s timer */ outb(0xE7, 0x64); }
static void early_superio_config(void) { int timeout = 100000; pnp_devfn_t dev = PNP_DEV(0x2e, 3); pnp_write_config(dev, 0x29, 0x06); while (!(pnp_read_config(dev, 0x29) & 0x08) && timeout--) udelay(1000); /* Enable COM1 */ pnp_set_logical_device(dev); pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); pnp_set_enable(dev, 1); }
int board_early_init_f(void) { #ifndef CONFIG_INTERNAL_UART /* * The FSP enables the BayTrail internal legacy UART (again). * Disable it again, so that the Winbond one can be used. */ setup_internal_uart(0); /* Enable the legacy UART in the Winbond W83627 Super IO chip */ winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1), UART0_BASE, UART0_IRQ); #endif return 0; }
static void early_superio_config(void) { pnp_devfn_t dev; dev = PNP_DEV(0x4e, 0x00); pnp_enter_ext_func_mode(dev); pnp_write_register(dev, 0x02, 0x0e); // UART power pnp_write_register(dev, 0x1b, (0x3e8 >> 2)); // UART3 base pnp_write_register(dev, 0x1c, (0x2e8 >> 2)); // UART4 base pnp_write_register(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ pnp_write_register(dev, 0x1e, 1); // no 32khz clock pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base pnp_write_register(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ pnp_write_register(dev, 0x2c, 0); // DMA0 FIR pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base pnp_write_register(dev, 0x31, 0xce); // GPIO1 DIR pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL pnp_write_register(dev, 0x33, 0x0f); // GPIO2 DIR pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL pnp_write_register(dev, 0x35, 0xa8); // GPIO3 DIR pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL pnp_write_register(dev, 0x37, 0xa8); // GPIO4 DIR pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL pnp_write_register(dev, 0x39, 0x00); // GPIO1 OUT pnp_write_register(dev, 0x40, 0x80); // GPIO2/MISC OUT pnp_write_register(dev, 0x41, 0x00); // GPIO5 OUT pnp_write_register(dev, 0x42, 0xa8); // GPIO5 DIR pnp_write_register(dev, 0x43, 0x00); // GPIO5 POL pnp_write_register(dev, 0x44, 0x00); // GPIO ALT1 pnp_write_register(dev, 0x45, 0x50); // GPIO ALT2 pnp_write_register(dev, 0x46, 0x00); // GPIO ALT3 pnp_write_register(dev, 0x48, 0x55); // GPIO ALT5 pnp_write_register(dev, 0x49, 0x55); // GPIO ALT6 pnp_write_register(dev, 0x4a, 0x55); // GPIO ALT7 pnp_write_register(dev, 0x4b, 0x55); // GPIO ALT8 pnp_write_register(dev, 0x4c, 0x55); // GPIO ALT9 pnp_write_register(dev, 0x4d, 0x55); // GPIO ALT10 pnp_exit_ext_func_mode(dev); }
void main(unsigned long bist) { if (bist == 0) enable_lapic(); i5000_lpc_config(); w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); early_config(); setup_gpio(); enable_smbus(); /* setup PCIe MMCONF base address */ pci_write_config32(PCI_DEV(0, 16, 0), 0x64, CONFIG_MMCONF_BASE_ADDRESS >> 16); outb(0x07, 0x11b8); /* These are smbus write captured with serialice. They seem to setup the clock generator */ smbus_write_byte(0x6f, 0x88, 0x1f); smbus_write_byte(0x6f, 0x81, 0xff); smbus_write_byte(0x6f, 0x82, 0xff); smbus_write_byte(0x6f, 0x80, 0x23); outb(0x03, 0x11b8); outb(0x01, 0x11b8); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1); i5000_fbdimm_init(); smbus_write_byte(0x69, 0x01, 0x01); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); /* enable port80 decoding and southbridge poweron init */ sb800_lpc_init(); sb800_pci_port80(); } post_code(0x30); if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ /* All cores run this but the BSP(node0,core0) is the only core that returns. */ } post_code(0x32); enable_rs780_dev8(); sb800_clk_output_48Mhz(); winbond_set_clksel_48(PNP_DEV(0x2e, 0)); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); printk(BIOS_DEBUG, "\n"); /* Halt if there was a built in self test failure */ report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); update_microcode(val); post_code(0x33); cpuSetAMDMSR(0); post_code(0x34); amd_ht_init(sysinfo); post_code(0x35); /* Setup nodes PCI space and start core 0 AP init. */ finalize_node_setup(sysinfo); /* Setup any mainboard PCI settings etc. */ setup_mb_resource_map(); post_code(0x36); /* wait for all the APs core0 started by finalize_node_setup. */ /* FIXME: A bunch of cores are going to start output to serial at once. It would be nice to fixup prink spinlocks for ROM XIP mode. I think it could be done by putting the spinlock flag in the cache of the BSP located right after sysinfo. */ wait_all_core0_started(); #if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif post_code(0x38); /* run _early_setup before soft-reset. */ rs780_early_setup(); sb800_early_setup(); #if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); /* show final fid and vid */ msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif rs780_htinit(); /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ if (!warm_reset_detect(0)) { printk(BIOS_INFO, "...WARM RESET...\n\n\n"); soft_reset(); die("After soft_reset - shouldn't see this message!!!\n"); } post_code(0x3B); /* It's the time to set ctrl in sysinfo now; */ printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); post_code(0x40); timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); amdmct_cbmem_store_info(sysinfo); sb800_before_pci_init(); post_code(0x42); }
#include <console/console.h> #include <device/pnp.h> #include "pilot.h" /* * Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to * be another serial (?), it is also deactivated on the HP machine. */ void pilot_early_init(device_t dev) { u16 port = dev >> 8; print_debug("Using port: "); print_debug_hex16(port); print_debug("\n"); pilot_disable_serial(PNP_DEV(port, 0x1)); print_debug("disable serial 1\n"); pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x3)); pnp_set_enable(dev, 0); pnp_set_iobase(dev, 0x60, 0x0b00); pnp_set_iobase(dev, 0x62, 0x0b80); pnp_set_iobase(dev, 0x64, 0x0b84); pnp_set_iobase(dev, 0x66, 0x0b86); pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); /* pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x3));
/* This box has one superio * Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. */ static void early_superio_config_w83627ehg(void) { device_t dev; dev = DUMMY_DEV; pnp_enter_ext_func_mode(dev); pnp_write_config(dev, 0x24, 0xc4); // PNPCSV pnp_write_config(dev, 0x29, 0x01); // GPIO settings pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02 pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings? pnp_write_config(dev, 0x2c, 0x03); // GPIO settings? pnp_write_config(dev, 0x2d, 0x20); // GPIO settings? dev=PNP_DEV(0x4e, W83627EHG_SP1); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); pnp_set_irq(dev, PNP_IDX_IRQ0, 4); pnp_set_enable(dev, 1); dev=PNP_DEV(0x4e, W83627EHG_SP2); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); pnp_set_irq(dev, PNP_IDX_IRQ0, 3); // pnp_write_config(dev, 0xf1, 4); // IRMODE0 pnp_set_enable(dev, 1); dev=PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); //pnp_write_config(dev, 0xf0, 0x82); pnp_set_enable(dev, 1); dev=PNP_DEV(0x4e, W83627EHG_GPIO2); pnp_set_logical_device(dev); pnp_set_enable(dev, 1); // Just enable it dev=PNP_DEV(0x4e, W83627EHG_GPIO3); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient dev=PNP_DEV(0x4e, W83627EHG_FDC); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); dev=PNP_DEV(0x4e, W83627EHG_PP); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); /* Enable HWM */ dev=PNP_DEV(0x4e, W83627EHG_HWM); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; post_code(0x30); agesawrapper_amdinitmmio(); post_code(0x31); /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ wpcm450_enable_dev(WPCM450_SP1, SIO_PORT, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); post_code(0x34); post_code(0x35); console_init(); val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x37); val = agesawrapper_amdinitreset(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n"); } if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, * Disable all Pcie Bridges to work around It. */ sr56x0_rd890_disable_pcie_bridge(); post_code(0x39); nb_Poweron_Init(); post_code(0x3A); sb_Poweron_Init(); } post_code(0x3B); val = agesawrapper_amdinitearly(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n"); } post_code(0x3C); /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. * In order to access W83795G/ADG HWM using I2C protocol, * we select function to SDA, SCL function (or GP33, GP32 function). */ w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI)); nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); distinguish_cpu_resets(0); soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); } post_code(0x40); val = agesawrapper_amdinitpost(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); } post_code(0x41); val = agesawrapper_amdinitenv(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); } printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n"); post_code(0x42); post_code(0x50); print_debug("Disabling cache as ram "); disable_cache_as_ram(); print_debug("done\n"); post_code(0x51); copy_and_run(); /* We will not return, Should never see this message and post code. */ print_debug("should not be here -\n"); post_code(0x54); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); //enable port80 decoding and southbridge poweron init sb_Poweron_Init(); } post_code(0x30); if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ /* All cores run this but the BSP(node0,core0) is the only core that returns. */ } post_code(0x32); enable_rs780_dev8(); sb800_clk_output_48Mhz(); w83627hf_set_clksel_48(PNP_DEV(CONFIG_SIO_PORT, 0)); w83627hf_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); console_init(); printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); // Load MPB val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); #if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); #endif post_code(0x33); cpuSetAMDMSR(); post_code(0x34); amd_ht_init(sysinfo); post_code(0x35); /* Setup nodes PCI space and start core 0 AP init. */ finalize_node_setup(sysinfo); /* Setup any mainboard PCI settings etc. */ setup_mb_resource_map(); post_code(0x36); /* wait for all the APs core0 started by finalize_node_setup. */ /* FIXME: A bunch of cores are going to start output to serial at once. It would be nice to fixup prink spinlocks for ROM XIP mode. I think it could be done by putting the spinlock flag in the cache of the BSP located right after sysinfo. */ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif post_code(0x38); /* run _early_setup before soft-reset. */ rs780_early_setup(); #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); post_code(0x39); if (!warm_reset_detect(0)) { // BSP is node 0 init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 } post_code(0x3A); /* show final fid and vid */ msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); #endif rs780_htinit(); /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); } post_code(0x3B); /* It's the time to set ctrl in sysinfo now; */ printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); post_code(0x40); // die("Die Before MCT init."); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); post_code(0x41); /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ // ram_check(0x00200000, 0x00200000 + (640 * 1024)); // ram_check(0x40200000, 0x40200000 + (640 * 1024)); // die("After MCT init before CAR disabled."); rs780_before_pci_init(); post_code(0x42); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. }
void main(unsigned long bist) { static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} }; SystemPreInit(); msr_init(); cs5536_early_setup(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Enable COM3. */ device_t dev = PNP_DEV(0x2e, 0x0b); u16 port = dev >> 8; outb(0x55, port); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); pnp_set_irq(dev, PNP_IDX_IRQ0, 4); pnp_set_enable(dev, 1); outb(0xaa, port); report_bist_failure(bist); pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
/* * Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to * be another serial (?), it is also deactivated on the HP machine. */ static void pilot_early_init(device_t dev) { unsigned port = dev >> 8; print_debug("Using port: "); print_debug_hex16(port); print_debug("\n"); pilot_disable_serial(PNP_DEV(port, 0x1)); print_debug("disable serial 1\n"); pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x3)); pnp_set_enable(dev, 0); pnp_set_iobase(dev, 0x60, 0x0b00); pnp_set_iobase(dev, 0x62, 0x0b80); pnp_set_iobase(dev, 0x64, 0x0b84); pnp_set_iobase(dev, 0x66, 0x0b86); pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); /* pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x3)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_enable(PNP_DEV(port, 0x3), 0); pnp_exit_ext_func_mode(dev); */ pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x4)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_enable( PNP_DEV(port, 0x4), 0); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x5)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_enable(PNP_DEV(port, 0x5), 0); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x6)); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); pnp_set_irq(dev, PNP_IDX_IRQ0, 1); pnp_set_drq(dev, 0x71, 3); pnp_set_enable(dev, 0); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0xe)); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x70); pnp_set_iobase(dev, PNP_IDX_IO1, 0x72); pnp_set_irq(dev, PNP_IDX_IRQ0, 8); pnp_set_drq(dev, 0x71, 3); pnp_set_enable(dev, 0); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x7)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_enable(PNP_DEV(port, 0x7), 0); pnp_exit_ext_func_mode(dev); /* pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x8)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_enable(PNP_DEV(port, 0x8), 0); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x9)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_enable(PNP_DEV(port, 0x9), 0); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x10)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); pnp_set_enable(PNP_DEV(port, 0x10), 0); pnp_exit_ext_func_mode(dev); */ }