static char *vd_va_vb(char *s,ppc_word in,int mask)
{
static const char *fmt = "v%d,";
if (mask) {
if (mask & 4)
s += sprintf(s,fmt,(int)PPCGETD(in));
if (mask & 2) {
if (mask & 16) { /* A = SIMM */
int a = PPCGETA(in);
s += sprintf(s,fmt+1,(a>15)?(a-32):a);
}
else if (mask & 8) /* A = UIMM */
s += sprintf(s,fmt+1,(int)PPCGETA(in));
else
s += sprintf(s,fmt,(int)PPCGETA(in));
}
if (mask & 1)
s += sprintf(s,fmt,(int)PPCGETB(in));
*--s = '\0';
}
else
*s = '\0';
return (s);
}
static int branch(struct DisasmPara_PPC *dp,ppc_word in, const char *bname,int aform,int bdisp)
/* build a branch instr. and return number of chars written to operand */
{
int bo = (int)PPCGETD(in);
int bi = (int)PPCGETA(in);
char y = (char)(bo & 1);
int opercnt = 0;
const char *ext = b_ext[aform*2+(int)(in&1)];
if (bdisp < 0)
y ^= 1;
y = y ? '+':'-';
if (bo & 4) {
/* standard case - no decrement */
if (bo & 16) {
/* branch always */
if (PPCGETIDX(in) != 16) {
sprintf(dp->opcode,"b%s%s",bname,ext);
}
else {
sprintf(dp->opcode,"bc%s",ext);
opercnt = sprintf(dp->operands,"%d, %d",bo,bi);
}
}
else {
/* branch conditional */
sprintf(dp->opcode,"b%s%s%s%c",b_condition[((bo&8)>>1)+(bi&3)],
bname,ext,y);
if (bi >= 4)
opercnt = sprintf(dp->operands,"cr%d",bi>>2);
}
}
else {
static void imm(struct DisasmPara_PPC *dp,ppc_word in,int uimm,int type,int hex)
/* Generate immediate instruction operand. */
/* type 0: D-mode, D,A,imm */
/* type 1: S-mode, A,S,imm */
/* type 2: S/D register is ignored (trap,cmpi) */
/* type 3: A register is ignored (li) */
{
int i = (int)(in & 0xffff);
dp->type = PPCINSTR_IMM;
if (!uimm) {
if (i > 0x7fff)
i -= 0x10000;
}
else
dp->flags |= PPCF_UNSIGNED;
dp->displacement = i;
switch (type) {
case 0:
sprintf(dp->operands,"%s, %s, %d",regnames[(int)PPCGETD(in)],regnames[(int)PPCGETA(in)],i);
break;
case 1:
if (hex)
sprintf(dp->operands,"%s, %s, 0x%.4X",regnames[(int)PPCGETA(in)],regnames[(int)PPCGETD(in)],i);
else
sprintf(dp->operands,"%s, %s, %d",regnames[(int)PPCGETA(in)],regnames[(int)PPCGETD(in)],i);
break;
case 2:
sprintf(dp->operands,"%s, %d",regnames[(int)PPCGETA(in)],i);
break;
case 3:
if (hex)
sprintf(dp->operands,"%s, 0x%.4X",regnames[(int)PPCGETD(in)],i);
else
sprintf(dp->operands,"%s, %d",regnames[(int)PPCGETD(in)],i);
break;
default:
ierror("imm(): Wrong type");
break;
}
}
static void addi(struct DisasmPara_PPC *dp,ppc_word in,char *ext)
{
if ((in&0x08000000) && !PPCGETA(in)) {
sprintf(dp->opcode,"l%s",ext); /* li, lis */
imm(dp,in,0,3);
}
else {
sprintf(dp->opcode,"%s%s",(in&0x8000)?"sub":"add",ext);
if (in & 0x8000)
in = (in^0xffff) + 1;
imm(dp,in,1,0);
}
}
static void addi(struct PPCDisasm *dp,ppc_word in,const char *ext)
{
if ((in&0x08000000) && !PPCGETA(in)) {
sprintf(dp->opcode,"l%s",ext); /* li, lis */
if(!strcmp(ext, "i"))
imm(dp,in,0,3,1);
else
imm(dp,in,1,3,1);
}
else {
sprintf(dp->opcode,"%s%s",(in&0x8000)?"sub":"add",ext);
if (in & 0x8000)
in = (in^0xffff) + 1;
imm(dp,in,1,0,0);
}
}
static char *rd_ra_rb(char *s,ppc_word in,int mask)
{
static const char *fmt = "r%d,";
if (mask) {
if (mask & 4)
s += sprintf(s,fmt,(int)PPCGETD(in));
if (mask & 2)
s += sprintf(s,fmt,(int)PPCGETA(in));
if (mask & 1)
s += sprintf(s,fmt,(int)PPCGETB(in));
*--s = '\0';
}
else
*s = '\0';
return (s);
}
static char *fd_ra_rb(char *s,ppc_word in,int mask)
{
static const char *ffmt = "f%d,";
static const char *rfmt = "%s,";
if (mask) {
if (mask & 4)
s += sprintf(s,ffmt,(int)PPCGETD(in));
if (mask & 2)
s += sprintf(s,rfmt,regnames[(int)PPCGETA(in)]);
if (mask & 1)
s += sprintf(s,rfmt,regnames[(int)PPCGETB(in)]);
*--s = '\0';
}
else
*s = '\0';
return (s);
}
static void ra_rb(char *s,ppc_word in)
{
sprintf(s,"r%d,r%d",(int)PPCGETA(in),(int)PPCGETB(in));
}
static void ra_rb(char *s,ppc_word in)
{
sprintf(s,"%s, %s",regnames[(int)PPCGETA(in)],regnames[(int)PPCGETB(in)]);
}
