void bsp_restart(void *addr) { rtems_interrupt_level level; void (*start)(void) = addr; #ifdef HAS_UBOOT const void *mem_begin = (const void *) bsp_uboot_board_info.bi_memstart; size_t mem_size = bsp_uboot_board_info.bi_memsize; #else /* HAS_UBOOT */ const void *mem_begin = bsp_ram_start; size_t mem_size = (size_t) bsp_ram_size; #endif /* HAS_UBOOT */ uint32_t hid0; rtems_interrupt_disable(level); hid0 = PPC_SPECIAL_PURPOSE_REGISTER(HID0); if ((hid0 & HID0_DCE) != 0) { rtems_cache_flush_multiple_data_lines(mem_begin, mem_size); } hid0 &= ~(HID0_DCE | HID0_ICE); PPC_SET_SPECIAL_PURPOSE_REGISTER(HID0, hid0); (*start)(); }
static uint32_t ppc_exc_get_DAR_dflt(void) { if (ppc_cpu_is_60x()) return PPC_SPECIAL_PURPOSE_REGISTER(PPC_DAR); else switch (ppc_cpu_is_bookE()) { default: break; case PPC_BOOKE_STD: case PPC_BOOKE_E500: return PPC_SPECIAL_PURPOSE_REGISTER(DEAR_BOOKE); case PPC_BOOKE_405: return PPC_SPECIAL_PURPOSE_REGISTER(DEAR_405); } return 0xdeadbeef; }
static void null_pointer_protection(void) { #if defined(MPC55XX_BOARD_MPC5674FEVB) || defined(MPC55XX_BOARD_MPC5566EVB) struct MMU_tag mmu = { .MAS0 = { .B = { .TLBSEL = 1, .ESEL = 1 } } }; PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS0, mmu.MAS0.R); __asm__ volatile ("tlbre"); mmu.MAS1.R = PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS1); mmu.MAS1.B.VALID = 0; PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS1, mmu.MAS1.R); __asm__ volatile ("tlbwe"); #endif }
static void null_pointer_protection(void) { #ifdef MPC55XX_NULL_POINTER_PROTECTION struct MMU_tag mmu = { .MAS0 = { .B = { .TLBSEL = 1, .ESEL = 1 } } }; PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS0, mmu.MAS0.R); __asm__ volatile ("tlbre"); mmu.MAS1.R = PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS1); mmu.MAS1.B.VALID = 0; PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS1, mmu.MAS1.R); __asm__ volatile ("tlbwe"); #endif }