static void gv100_grctx_generate_attrib(struct gf100_grctx *info) { struct gf100_gr *gr = info->gr; const struct gf100_grctx_func *grctx = gr->func->grctx; const u32 alpha = grctx->alpha_nr; const u32 attrib = grctx->attrib_nr; const u32 gfxp = grctx->gfxp_nr; const int s = 12; const int max_batches = 0xffff; u32 size = grctx->alpha_nr_max * gr->tpc_total; u32 ao = 0; u32 bo = ao + size; int gpc, ppc, b, n = 0; size += grctx->gfxp_nr * gr->tpc_total; size = ((size * 0x20) + 128) & ~127; b = mmio_vram(info, size, (1 << s), false); mmio_refn(info, 0x418810, 0x80000000, s, b); mmio_refn(info, 0x419848, 0x10000000, s, b); mmio_refn(info, 0x419c2c, 0x10000000, s, b); mmio_refn(info, 0x419e00, 0x00000000, s, b); mmio_wr32(info, 0x419e04, 0x80000000 | size >> 7); mmio_wr32(info, 0x405830, attrib); mmio_wr32(info, 0x40585c, alpha); mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); for (gpc = 0; gpc < gr->gpc_nr; gpc++) { for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc]; const u32 gs = gfxp * gr->ppc_tpc_nr[gpc][ppc]; const u32 u = 0x418ea0 + (n * 0x04); const u32 o = PPC_UNIT(gpc, ppc, 0); if (!(gr->ppc_mask[gpc] & (1 << ppc))) continue; mmio_wr32(info, o + 0xc0, gs); mmio_wr32(info, o + 0xf4, bo); mmio_wr32(info, o + 0xf0, bs); bo += gs; mmio_wr32(info, o + 0xe4, as); mmio_wr32(info, o + 0xf8, ao); ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; mmio_wr32(info, u, bs); } } mmio_wr32(info, 0x4181e4, 0x00000100); mmio_wr32(info, 0x41befc, 0x00000100); }
void gk104_gr_init_ppc_exceptions(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; int gpc, ppc; for (gpc = 0; gpc < gr->gpc_nr; gpc++) { for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { if (!(gr->ppc_mask[gpc] & (1 << ppc))) continue; nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); } } }
void gp102_grctx_generate_attrib(struct gf100_grctx *info) { struct gf100_gr *gr = info->gr; const struct gf100_grctx_func *grctx = gr->func->grctx; const u32 alpha = grctx->alpha_nr; const u32 attrib = grctx->attrib_nr; const u32 pertpc = 0x20 * (grctx->attrib_nr_max + grctx->alpha_nr_max); const u32 size = roundup(gr->tpc_total * pertpc, 0x80); const int s = 12; const int b = mmio_vram(info, size, (1 << s), false); const int max_batches = 0xffff; u32 ao = 0; u32 bo = ao + grctx->alpha_nr_max * gr->tpc_total; int gpc, ppc, n = 0; mmio_refn(info, 0x418810, 0x80000000, s, b); mmio_refn(info, 0x419848, 0x10000000, s, b); mmio_refn(info, 0x419c2c, 0x10000000, s, b); mmio_refn(info, 0x419b00, 0x00000000, s, b); mmio_wr32(info, 0x419b04, 0x80000000 | size >> 7); mmio_wr32(info, 0x405830, attrib); mmio_wr32(info, 0x40585c, alpha); mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); for (gpc = 0; gpc < gr->gpc_nr; gpc++) { for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc]; const u32 u = 0x418ea0 + (n * 0x04); const u32 o = PPC_UNIT(gpc, ppc, 0); const u32 p = GPC_UNIT(gpc, 0xc44 + (ppc * 4)); if (!(gr->ppc_mask[gpc] & (1 << ppc))) continue; mmio_wr32(info, o + 0xc0, bs); mmio_wr32(info, p, bs); mmio_wr32(info, o + 0xf4, bo); mmio_wr32(info, o + 0xf0, bs); bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; mmio_wr32(info, o + 0xe4, as); mmio_wr32(info, o + 0xf8, ao); ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; mmio_wr32(info, u, bs); } } mmio_wr32(info, 0x4181e4, 0x00000100); mmio_wr32(info, 0x41befc, 0x00000100); }
static void gm107_grctx_generate_attrib(struct nvc0_grctx *info) { struct nvc0_graph_priv *priv = info->priv; const struct nvc0_grctx_oclass *impl = (void *)nvc0_grctx_impl(priv); const u32 alpha = impl->alpha_nr; const u32 attrib = impl->attrib_nr; const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); const u32 access = NV_MEM_ACCESS_RW; const int s = 12; const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access); const int max_batches = 0xffff; u32 bo = 0; u32 ao = bo + impl->attrib_nr_max * priv->tpc_total; int gpc, ppc, n = 0; mmio_refn(info, 0x418810, 0x80000000, s, b); mmio_refn(info, 0x419848, 0x10000000, s, b); mmio_refn(info, 0x419c2c, 0x10000000, s, b); mmio_wr32(info, 0x405830, (attrib << 16) | alpha); mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); for (gpc = 0; gpc < priv->gpc_nr; gpc++) { for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++, n++) { const u32 as = alpha * priv->ppc_tpc_nr[gpc][ppc]; const u32 bs = attrib * priv->ppc_tpc_nr[gpc][ppc]; const u32 u = 0x418ea0 + (n * 0x04); const u32 o = PPC_UNIT(gpc, ppc, 0); mmio_wr32(info, o + 0xc0, bs); mmio_wr32(info, o + 0xf4, bo); bo += impl->attrib_nr_max * priv->ppc_tpc_nr[gpc][ppc]; mmio_wr32(info, o + 0xe4, as); mmio_wr32(info, o + 0xf8, ao); ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc]; mmio_wr32(info, u, (0x715 /*XXX*/ << 16) | bs); } } }
void nvd7_grctx_generate_attrib(struct nvc0_grctx *info) { struct nvc0_graph_priv *priv = info->priv; const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv); const u32 alpha = impl->alpha_nr; const u32 beta = impl->attrib_nr; const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); const u32 access = NV_MEM_ACCESS_RW; const int s = 12; const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access); const int timeslice_mode = 1; const int max_batches = 0xffff; u32 bo = 0; u32 ao = bo + impl->attrib_nr_max * priv->tpc_total; int gpc, ppc; mmio_refn(info, 0x418810, 0x80000000, s, b); mmio_refn(info, 0x419848, 0x10000000, s, b); mmio_wr32(info, 0x405830, (beta << 16) | alpha); mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); for (gpc = 0; gpc < priv->gpc_nr; gpc++) { for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++) { const u32 a = alpha * priv->ppc_tpc_nr[gpc][ppc]; const u32 b = beta * priv->ppc_tpc_nr[gpc][ppc]; const u32 t = timeslice_mode; const u32 o = PPC_UNIT(gpc, ppc, 0); mmio_skip(info, o + 0xc0, (t << 28) | (b << 16) | ++bo); mmio_wr32(info, o + 0xc0, (t << 28) | (b << 16) | --bo); bo += impl->attrib_nr_max * priv->ppc_tpc_nr[gpc][ppc]; mmio_wr32(info, o + 0xe4, (a << 16) | ao); ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc]; } } }
int gm107_gr_init(struct nvkm_object *object) { struct gf100_gr_oclass *oclass = (void *)object->oclass; struct gf100_gr_priv *priv = (void *)object; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; int gpc, tpc, ppc, rop; int ret, i; ret = nvkm_gr_init(&priv->base); if (ret) return ret; nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); gf100_gr_mmio(priv, oclass->mmio); gm107_gr_init_bios(priv); nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); memset(data, 0x00, sizeof(data)); memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); for (i = 0, gpc = -1; i < priv->tpc_total; i++) { do { gpc = (gpc + 1) % priv->gpc_nr; } while (!tpcnr[gpc]); tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; data[i / 8] |= tpc << ((i % 8) * 4); } nv_wr32(priv, GPC_BCAST(0x0980), data[0]); nv_wr32(priv, GPC_BCAST(0x0984), data[1]); nv_wr32(priv, GPC_BCAST(0x0988), data[2]); nv_wr32(priv, GPC_BCAST(0x098c), data[3]); for (gpc = 0; gpc < priv->gpc_nr; gpc++) { nv_wr32(priv, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tpc_total); nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); } nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); nv_wr32(priv, 0x400500, 0x00010001); nv_wr32(priv, 0x400100, 0xffffffff); nv_wr32(priv, 0x40013c, 0xffffffff); nv_wr32(priv, 0x400124, 0x00000002); nv_wr32(priv, 0x409c24, 0x000e0000); nv_wr32(priv, 0x404000, 0xc0000000); nv_wr32(priv, 0x404600, 0xc0000000); nv_wr32(priv, 0x408030, 0xc0000000); nv_wr32(priv, 0x404490, 0xc0000000); nv_wr32(priv, 0x406018, 0xc0000000); nv_wr32(priv, 0x407020, 0x40000000); nv_wr32(priv, 0x405840, 0xc0000000); nv_wr32(priv, 0x405844, 0x00ffffff); nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); for (gpc = 0; gpc < priv->gpc_nr; gpc++) { for (ppc = 0; ppc < 2 /* priv->ppc_nr[gpc] */; ppc++) nv_wr32(priv, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); } nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); } for (rop = 0; rop < priv->rop_nr; rop++) { nv_wr32(priv, ROP_UNIT(rop, 0x144), 0x40000000); nv_wr32(priv, ROP_UNIT(rop, 0x070), 0x40000000); nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); } nv_wr32(priv, 0x400108, 0xffffffff); nv_wr32(priv, 0x400138, 0xffffffff); nv_wr32(priv, 0x400118, 0xffffffff); nv_wr32(priv, 0x400130, 0xffffffff); nv_wr32(priv, 0x40011c, 0xffffffff); nv_wr32(priv, 0x400134, 0xffffffff); nv_wr32(priv, 0x400054, 0x2c350f63); gf100_gr_zbc_init(priv); return gf100_gr_init_ctxctl(priv); }