ISP_MGR_MIXER3_T&
ISP_MGR_MIXER3_T::
put(ISP_NVRAM_MIXER3_T const& rParam)
{
PUT_REG_INFO(CAM_MIX3_CTRL_0, ctrl_0);
PUT_REG_INFO(CAM_MIX3_CTRL_1, ctrl_1);
PUT_REG_INFO(CAM_MIX3_SPARE, spare);
return (*this);
}
ISP_MGR_G2C_SHADE_T&
ISP_MGR_G2C_SHADE_T::
put(ISP_NVRAM_G2C_SHADE_T const& rParam)
{
PUT_REG_INFO(CAM_G2C_SHADE_CON_1, con_1);
PUT_REG_INFO(CAM_G2C_SHADE_CON_2, con_2);
PUT_REG_INFO(CAM_G2C_SHADE_CON_3, con_3);
PUT_REG_INFO(CAM_G2C_SHADE_TAR, tar);
PUT_REG_INFO(CAM_G2C_SHADE_SP, sp);
return (*this);
}
ISP_MGR_MFB_T&
ISP_MGR_MFB_T::
put(ISP_NVRAM_MFB_T const& rParam)
{
PUT_REG_INFO(CAM_MFB_LL_CON2, ll_con2);
PUT_REG_INFO(CAM_MFB_LL_CON3, ll_con3);
PUT_REG_INFO(CAM_MFB_LL_CON4, ll_con4);
PUT_REG_INFO(CAM_MFB_LL_CON5, ll_con5);
PUT_REG_INFO(CAM_MFB_LL_CON6, ll_con6);
return (*this);
}
ISP_MGR_LSC_T&
ISP_MGR_LSC_T::
put(ISP_NVRAM_LSC_T const& rParam)
{
MY_LOG_IF(ENABLE_MY_LOG, "[%s\n", __FUNCTION__);
// PUT_REG_INFO(CAM_LSCI_BASE_ADDR, baseaddr);
PUT_REG_INFO(CAM_LSC_CTL1, ctl1);
PUT_REG_INFO(CAM_LSC_CTL2, ctl2);
PUT_REG_INFO(CAM_LSC_CTL3, ctl3);
PUT_REG_INFO(CAM_LSC_LBLOCK, lblock);
PUT_REG_INFO(CAM_LSC_RATIO, ratio);
// PUT_REG_INFO(CAM_LSC_GAIN_TH, gain_th);
return (*this);
}
ISP_MGR_SEEE_T&
ISP_MGR_SEEE_T::
put(ISP_NVRAM_SE_T const& rParam)
{
PUT_REG_INFO(CAM_SEEE_OUT_EDGE_CTRL, out_edge_ctrl);
PUT_REG_INFO(CAM_SEEE_SE_Y_CTRL, y_ctrl);
PUT_REG_INFO(CAM_SEEE_SE_EDGE_CTRL_1, edge_ctrl_1);
PUT_REG_INFO(CAM_SEEE_SE_EDGE_CTRL_2, edge_ctrl_2);
PUT_REG_INFO(CAM_SEEE_SE_EDGE_CTRL_3, edge_ctrl_3);
PUT_REG_INFO(CAM_SEEE_SE_SPECL_CTRL, special_ctrl);
PUT_REG_INFO(CAM_SEEE_SE_CORE_CTRL_1, core_ctrl_1);
PUT_REG_INFO(CAM_SEEE_SE_CORE_CTRL_2, core_ctrl_2);
return (*this);
}
ISP_MGR_G2C_T&
ISP_MGR_G2C_T::
put(ISP_NVRAM_G2C_T const& rParam)
{
PUT_REG_INFO(CAM_G2C_CONV_0A, conv_0a);
PUT_REG_INFO(CAM_G2C_CONV_0B, conv_0b);
PUT_REG_INFO(CAM_G2C_CONV_1A, conv_1a);
PUT_REG_INFO(CAM_G2C_CONV_1B, conv_1b);
PUT_REG_INFO(CAM_G2C_CONV_2A, conv_2a);
PUT_REG_INFO(CAM_G2C_CONV_2B, conv_2b);
return (*this);
}
ISP_MGR_LCE_T &
ISP_MGR_LCE_T::
put(ISP_NVRAM_LCE_T const &rParam)
{
//MY_LOG("rParam.qua.val = x%08x", rParam.qua.val);
PUT_REG_INFO(CAM_LCE_QUA, qua);
//MY_LOG("m_rIspRegInfo[ERegInfo_CAM_LCE_QUA].val = 0x%8x", m_rIspRegInfo[ERegInfo_CAM_LCE_QUA].val);
mLceWeakest = m_rIspRegInfo[ERegInfo_CAM_LCE_QUA].val & 0x01F;
mLceStrogest = (m_rIspRegInfo[ERegInfo_CAM_LCE_QUA].val & 0x3E0) >> 5;
mLvLowBound = (m_rIspRegInfo[ERegInfo_CAM_LCE_QUA].val & 0x1FFC00) >> 10;
mLvUpBound = (m_rIspRegInfo[ERegInfo_CAM_LCE_QUA].val & 0xFFE00000) >> 21;
#if (LCE_DEBUG)
MY_LOG("[%s] QUA(0x%08x),lceIdx(%u,%u),LV(%u,%u)",__func__,m_rIspRegInfo[ERegInfo_CAM_LCE_QUA].val,mLceWeakest,mLceStrogest,mLvLowBound,mLvUpBound);
#else
MY_LOG_IF(g_lceDebug,"[%s] QUA(0x%08x),lceIdx(%u,%u),LV(%u,%u)",__func__,m_rIspRegInfo[ERegInfo_CAM_LCE_QUA].val,mLceWeakest,mLceStrogest,mLvLowBound,mLvUpBound);
#endif
return (*this);
}
ISP_MGR_CFA_T&
ISP_MGR_CFA_T::
put(ISP_NVRAM_CFA_T const& rParam)
{
PUT_REG_INFO(CAM_DM_O_BYP, byp);
PUT_REG_INFO(CAM_DM_O_ED_FLAT, ed_flat);
PUT_REG_INFO(CAM_DM_O_ED_NYQ, ed_nyq);
PUT_REG_INFO(CAM_DM_O_ED_STEP, ed_step);
PUT_REG_INFO(CAM_DM_O_RGB_HF, rgb_hf);
PUT_REG_INFO(CAM_DM_O_DOT, dot);
PUT_REG_INFO(CAM_DM_O_F1_ACT, f1_act);
PUT_REG_INFO(CAM_DM_O_F2_ACT, f2_act);
PUT_REG_INFO(CAM_DM_O_F3_ACT, f3_act);
PUT_REG_INFO(CAM_DM_O_F4_ACT, f4_act);
PUT_REG_INFO(CAM_DM_O_F1_L, f1_l);
PUT_REG_INFO(CAM_DM_O_F2_L, f2_l);
PUT_REG_INFO(CAM_DM_O_F3_L, f3_l);
PUT_REG_INFO(CAM_DM_O_F4_L, f4_l);
PUT_REG_INFO(CAM_DM_O_HF_RB, hf_rb);
PUT_REG_INFO(CAM_DM_O_HF_GAIN, hf_gain);
PUT_REG_INFO(CAM_DM_O_HF_COMP, hf_comp);
PUT_REG_INFO(CAM_DM_O_HF_CORIN_TH, hf_coring_th);
PUT_REG_INFO(CAM_DM_O_ACT_LUT, act_lut);
PUT_REG_INFO(CAM_DM_O_SPARE, spare);
PUT_REG_INFO(CAM_DM_O_BB, bb);
return (*this);
}
ISP_MGR_RPG_T&
ISP_MGR_RPG_T::
put(ISP_NVRAM_RPG_T const& rParam)
{
if (m_eSensorTG == ESensorTG_1) {
PUT_REG_INFO(CAM_RPG_SATU_1, satu_1);
PUT_REG_INFO(CAM_RPG_SATU_2, satu_2);
PUT_REG_INFO(CAM_RPG_GAIN_1, gain_1);
PUT_REG_INFO(CAM_RPG_GAIN_2, gain_2);
PUT_REG_INFO(CAM_RPG_OFST_1, ofst_1);
PUT_REG_INFO(CAM_RPG_OFST_2, ofst_2);
}
else {
PUT_REG_INFO(CAM_RPG_D_SATU_1, satu_1);
PUT_REG_INFO(CAM_RPG_D_SATU_2, satu_2);
PUT_REG_INFO(CAM_RPG_D_GAIN_1, gain_1);
PUT_REG_INFO(CAM_RPG_D_GAIN_2, gain_2);
PUT_REG_INFO(CAM_RPG_D_OFST_1, ofst_1);
PUT_REG_INFO(CAM_RPG_D_OFST_2, ofst_2);
}
return (*this);
}
ISP_MGR_SEEE_T&
ISP_MGR_SEEE_T::
put(ISP_NVRAM_EE_T const& rParam)
{
PUT_REG_INFO(CAM_SEEE_SRK_CTRL, srk_ctrl);
PUT_REG_INFO(CAM_SEEE_CLIP_CTRL, clip_ctrl);
PUT_REG_INFO(CAM_SEEE_FLT_CTRL_1, flt_ctrl_1);
PUT_REG_INFO(CAM_SEEE_FLT_CTRL_2, flt_ctrl_2);
PUT_REG_INFO(CAM_SEEE_GLUT_CTRL_01, glut_ctrl_01);
PUT_REG_INFO(CAM_SEEE_GLUT_CTRL_02, glut_ctrl_02);
PUT_REG_INFO(CAM_SEEE_GLUT_CTRL_03, glut_ctrl_03);
PUT_REG_INFO(CAM_SEEE_GLUT_CTRL_04, glut_ctrl_04);
PUT_REG_INFO(CAM_SEEE_GLUT_CTRL_05, glut_ctrl_05);
PUT_REG_INFO(CAM_SEEE_GLUT_CTRL_06, glut_ctrl_06);
PUT_REG_INFO(CAM_SEEE_EDTR_CTRL, edtr_ctrl);
PUT_REG_INFO(CAM_SEEE_GLUT_CTRL_07, glut_ctrl_07);
PUT_REG_INFO(CAM_SEEE_GLUT_CTRL_08, glut_ctrl_08);
PUT_REG_INFO(CAM_SEEE_GLUT_CTRL_09, glut_ctrl_09);
PUT_REG_INFO(CAM_SEEE_GLUT_CTRL_10, glut_ctrl_10);
PUT_REG_INFO(CAM_SEEE_GLUT_CTRL_11, glut_ctrl_11);
return (*this);
}
