static int ev64260_get_cpu_speed(void) { unsigned long pvr, hid1, pll_ext; pvr = PVR_VER(mfspr(SPRN_PVR)); if (pvr != PVR_VER(PVR_7450)) { hid1 = mfspr(SPRN_HID1) >> 28; return ev64260_get_bus_speed() * cpu_7xx[hid1]/2; }
int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { uint pvr; uint ver; unsigned long val, msr; pvr = get_pvr(); ver = PVR_VER(pvr); if (ver & 1){ /* e500 v2 core has reset control register */ volatile unsigned int * rstcr; rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0); *rstcr = 0x2; /* HRESET_REQ */ udelay(100); } /* * Fallthrough if the code above failed * Initiate hard reset in debug control register DBCR0 * Make sure MSR[DE] = 1 */ msr = mfmsr (); msr |= MSR_DE; mtmsr (msr); val = mfspr(DBCR0); val |= 0x70000000; mtspr(DBCR0,val); return 1; }
void __init adjust_total_lowmem(void) { unsigned long max_low_mem = MAX_LOW_MEM; #ifdef HAVE_BATS unsigned long bat_max = 0x10000000; unsigned long align; unsigned long ram = total_lowmem; int is601 = 0; /* 601s have smaller BATs */ if (PVR_VER(mfspr(PVR)) == 1) { bat_max = 0x00800000; is601 = 1; } /* Make sure we don't map a block larger than the smallest alignment of the physical address. */ /* alignment of ram_phys_base */ align = ~(ram_phys_base-1) & ram_phys_base; /* set BAT block size to MIN(max_size, align) */ if (align && align < bat_max) bat_max = align; /* Calculate BAT values */ __bat2 = 1UL << __ilog2(ram); if (__bat2 > bat_max) __bat2 = bat_max; ram -= __bat2; if (ram) { __bat3 = 1UL << __ilog2(ram); if (__bat3 > bat_max) __bat3 = bat_max; ram -= __bat3; } printk(KERN_INFO "Memory BAT mapping: BAT2=%ldMb, BAT3=%ldMb, residual: %ldMb\n", __bat2 >> 20, __bat3 >> 20, ram >> 20); /* On SMP, we limit the lowmem to the area mapped with BATs. * We also assume nobody will do SMP with 601s */ #ifdef CONFIG_SMP if (!is601) max_low_mem = __bat2 + __bat3; #endif /* CONFIG_SMP */ #endif /* HAVE_BATS */ if (total_lowmem > max_low_mem) { total_lowmem = max_low_mem; #ifndef CONFIG_HIGHMEM printk(KERN_INFO "Warning, memory limited to %ld Mb, use CONFIG_HIGHMEM" " to reach %ld Mb\n", max_low_mem >> 20, total_lowmem >> 20); total_memory = total_lowmem; #endif /* CONFIG_HIGHMEM */ }
int __init oprofile_arch_init(struct oprofile_operations **ops) { unsigned int pvr; pvr = _get_PVR(); switch (PVR_VER(pvr)) { case PV_630: case PV_630p: model = &op_model_rs64; model->num_counters = 8; oprof_ppc64_ops.cpu_type = "ppc64/power3"; break; case PV_NORTHSTAR: case PV_PULSAR: case PV_ICESTAR: case PV_SSTAR: model = &op_model_rs64; model->num_counters = 8; oprof_ppc64_ops.cpu_type = "ppc64/rs64"; break; case PV_POWER4: case PV_POWER4p: model = &op_model_power4; model->num_counters = 8; oprof_ppc64_ops.cpu_type = "ppc64/power4"; break; case PV_970: case PV_970FX: model = &op_model_power4; model->num_counters = 8; oprof_ppc64_ops.cpu_type = "ppc64/970"; break; case PV_POWER5: case PV_POWER5p: model = &op_model_power4; model->num_counters = 6; oprof_ppc64_ops.cpu_type = "ppc64/power5"; break; default: return -ENODEV; } *ops = &oprof_ppc64_ops; printk(KERN_INFO "oprofile: using %s performance monitoring.\n", oprof_ppc64_ops.cpu_type); return 0; }
int get_cpuid(char *buffer, size_t sz) { unsigned long pvr; int nb; pvr = mfspr(SPRN_PVR); nb = scnprintf(buffer, sz, "%lu,%lu$", PVR_VER(pvr), PVR_REV(pvr)); /* */ if (strchr(buffer, '$')) { buffer[nb-1] = '\0'; return 0; } return -1; }
int get_cpuid(char *buffer, size_t sz) { unsigned long pvr; int nb; pvr = mfspr(SPRN_PVR); nb = scnprintf(buffer, sz, "%lu,%lu$", PVR_VER(pvr), PVR_REV(pvr)); /* look for end marker to ensure the entire data fit */ if (strchr(buffer, '$')) { buffer[nb-1] = '\0'; return 0; } return -1; }
int checkcpu (void) { sys_info_t sysinfo; uint pvr, svr; uint fam; uint ver; uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif /* CONFIG_FSL_CORENET */ #ifdef CONFIG_DDR_CLK_FREQ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else #ifdef CONFIG_FSL_CORENET u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; #else u32 ddr_ratio = 0; #endif /* CONFIG_FSL_CORENET */ #endif /* CONFIG_DDR_CLK_FREQ */ int i; svr = get_svr(); major = SVR_MAJ(svr); #ifdef CONFIG_MPC8536 major &= 0x7; /* the msb of this nibble is a mfg code */ #endif minor = SVR_MIN(svr); if (cpu_numcores() > 1) { #ifndef CONFIG_MP puts("Unicore software on multiprocessor system!!\n" "To enable mutlticore build define CONFIG_MP\n"); #endif volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { puts("CPU: "); } cpu = gd->cpu; puts(cpu->name); if (IS_E_PROCESSOR(svr)) puts("E"); printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); fam = PVR_FAM(pvr); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); if (PVR_FAM(PVR_85xx)) { switch(PVR_MEM(pvr)) { case 0x1: case 0x2: puts("E500"); break; case 0x3: puts("E500MC"); break; case 0x4: puts("E5500"); break; default: puts("Unknown"); break; } } else { puts("Unknown"); } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); get_sys_info(&sysinfo); puts("Clock Configuration:"); for (i = 0; i < cpu_numcores(); i++) { if (!(i & 3)) printf ("\n "); printf("CPU%d:%-4s MHz, ", i,strmhz(buf1, sysinfo.freqProcessor[i])); } printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); #ifdef CONFIG_FSL_CORENET if (ddr_sync == 1) { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); } else { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); } #else switch (ddr_ratio) { case 0x0: printf(" DDR:%-4s MHz (%s MT/s data rate), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; case 0x7: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; default: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; } #endif #if defined(CONFIG_FSL_LBC) if (sysinfo.freqLocalBus > LCRR_CLKDIV) { printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); } #endif #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); #endif #ifdef CONFIG_QE printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); #endif #ifdef CONFIG_SYS_DPAA_FMAN for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { printf(" FMAN%d: %s MHz\n", i + 1, strmhz(buf1, sysinfo.freqFMan[i])); } #endif #ifdef CONFIG_SYS_DPAA_PME printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); #endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); return 0; }
void __init smp_boot_cpus(void) { extern struct task_struct *current_set[NR_CPUS]; int i, cpu_nr; struct task_struct *p; printk("Entering SMP Mode...\n"); smp_num_cpus = 1; smp_store_cpu_info(0); cpu_online_map = 1UL; /* * assume for now that the first cpu booted is * cpu 0, the master -- Cort */ cpu_callin_map[0] = 1; current->processor = 0; for (i = 0; i < NR_CPUS; i++) { prof_counter[i] = 1; prof_multiplier[i] = 1; } /* * XXX very rough, assumes 20 bus cycles to read a cache line, * timebase increments every 4 bus cycles, 32kB L1 data cache. */ cacheflush_time = 5 * 1024; smp_ops = ppc_md.smp_ops; if (smp_ops == NULL) { printk("SMP not supported on this machine.\n"); return; } #ifndef CONFIG_750_SMP /* check for 750's, they just don't work with linux SMP. * If you actually have 750 SMP hardware and want to try to get * it to work, send me a patch to make it work and * I'll make CONFIG_750_SMP a config option. -- Troy ([email protected]) */ if ( PVR_VER(mfspr(PVR)) == 8 ){ printk("SMP not supported on 750 cpus. %s line %d\n", __FILE__, __LINE__); return; } #endif /* Probe arch for CPUs */ cpu_nr = smp_ops->probe(); /* Backup CPU 0 state */ __save_cpu_setup(); /* * only check for cpus we know exist. We keep the callin map * with cpus at the bottom -- Cort */ if (cpu_nr > max_cpus) cpu_nr = max_cpus; for (i = 1; i < cpu_nr; i++) { int c; struct pt_regs regs; /* create a process for the processor */ /* only regs.msr is actually used, and 0 is OK for it */ memset(®s, 0, sizeof(struct pt_regs)); if (do_fork(CLONE_VM|CLONE_PID, 0, ®s, 0) < 0) panic("failed fork for CPU %d", i); p = init_task.prev_task; if (!p) panic("No idle task for CPU %d", i); init_idle(p, i); unhash_process(p); init_tasks[i] = p; p->processor = i; p->cpus_runnable = 1 << i; /* we schedule the first task manually */ current_set[i] = p; /* * There was a cache flush loop here to flush the cache * to memory for the first 8MB of RAM. The cache flush * has been pushed into the kick_cpu function for those * platforms that need it. */ /* wake up cpus */ smp_ops->kick_cpu(i); /* * wait to see if the cpu made a callin (is actually up). * use this value that I found through experimentation. * -- Cort */ for ( c = 10000; c && !cpu_callin_map[i] ; c-- ) udelay(100); if ( cpu_callin_map[i] ) { char buf[32]; sprintf(buf, "found cpu %d", i); if (ppc_md.progress) ppc_md.progress(buf, 0x350+i); printk("Processor %d found.\n", i); smp_num_cpus++; } else { char buf[32]; sprintf(buf, "didn't find cpu %d", i); if (ppc_md.progress) ppc_md.progress(buf, 0x360+i); printk("Processor %d is stuck.\n", i); } } /* Setup CPU 0 last (important) */ smp_ops->setup_cpu(0); if (smp_num_cpus < 2) smp_tb_synchronized = 1; }
int checkcpu (void) { sys_info_t sysinfo; uint pvr, svr; uint ver; uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif /* * Cornet platforms use ddr sync bit in RCW to indicate sync vs async * mode. Previous platform use ddr ratio to do the same. This * information is only for display here. */ #ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 u32 ddr_sync = 0; /* only async mode is supported */ #else u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #else /* CONFIG_FSL_CORENET */ #ifdef CONFIG_DDR_CLK_FREQ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; #endif /* CONFIG_DDR_CLK_FREQ */ #endif /* CONFIG_FSL_CORENET */ unsigned int i, core, nr_cores = cpu_numcores(); u32 mask = cpu_mask(); #ifdef CONFIG_HETROGENOUS_CLUSTERS unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores(); u32 dsp_mask = cpu_dsp_mask(); #endif svr = get_svr(); major = SVR_MAJ(svr); minor = SVR_MIN(svr); #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) if (SVR_SOC_VER(svr) == SVR_T4080) { ccsr_rcpm_t *rcpm = (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 || FSL_CORENET_DEVDISR2_DTSEC1_9); setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3); setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3); /* It needs SW to disable core4~7 as HW design sake on T4080 */ for (i = 4; i < 8; i++) cpu_disable(i); /* request core4~7 into PH20 state, prior to entering PCL10 * state, all cores in cluster should be placed in PH20 state. */ setbits_be32(&rcpm->pcph20setr, 0xf0); /* put the 2nd cluster into PCL10 state */ setbits_be32(&rcpm->clpcl10setr, 1 << 1); } #endif if (cpu_numcores() > 1) { #ifndef CONFIG_MP puts("Unicore software on multiprocessor system!!\n" "To enable mutlticore build define CONFIG_MP\n"); #endif volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { puts("CPU: "); } cpu = gd->arch.cpu; puts(cpu->name); if (IS_E_PROCESSOR(svr)) puts("E"); printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); switch(ver) { case PVR_VER_E500_V1: case PVR_VER_E500_V2: puts("e500"); break; case PVR_VER_E500MC: puts("e500mc"); break; case PVR_VER_E5500: puts("e5500"); break; case PVR_VER_E6500: puts("e6500"); break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); if (nr_cores > CONFIG_MAX_CPUS) { panic("\nUnexpected number of cores: %d, max is %d\n", nr_cores, CONFIG_MAX_CPUS); } get_sys_info(&sysinfo); #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK if (sysinfo.diff_sysclk == 1) puts("Single Source Clock Configuration\n"); #endif puts("Clock Configuration:"); for_each_cpu(i, core, nr_cores, mask) { if (!(i & 3)) printf ("\n "); printf("CPU%d:%-4s MHz, ", core, strmhz(buf1, sysinfo.freq_processor[core])); } #ifdef CONFIG_HETROGENOUS_CLUSTERS for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) { if (!(j & 3)) printf("\n "); printf("DSP CPU%d:%-4s MHz, ", j, strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core])); } #endif printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus)); printf("\n"); #ifdef CONFIG_FSL_CORENET if (ddr_sync == 1) { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freq_ddrbus/2), strmhz(buf2, sysinfo.freq_ddrbus)); } else { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freq_ddrbus/2), strmhz(buf2, sysinfo.freq_ddrbus)); } #else switch (ddr_ratio) { case 0x0: printf(" DDR:%-4s MHz (%s MT/s data rate), ", strmhz(buf1, sysinfo.freq_ddrbus/2), strmhz(buf2, sysinfo.freq_ddrbus)); break; case 0x7: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freq_ddrbus/2), strmhz(buf2, sysinfo.freq_ddrbus)); break; default: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freq_ddrbus/2), strmhz(buf2, sysinfo.freq_ddrbus)); break; } #endif #if defined(CONFIG_FSL_LBC) if (sysinfo.freq_localbus > LCRR_CLKDIV) { printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freq_localbus); } #endif #if defined(CONFIG_FSL_IFC) printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); #endif #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus)); #endif #ifdef CONFIG_QE printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe)); #endif #if defined(CONFIG_SYS_CPRI) printf(" "); printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri)); #endif #if defined(CONFIG_SYS_MAPLE) printf("\n "); printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple)); printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb)); printf("MAPLE-eTVPE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_maple_etvpe)); #endif #ifdef CONFIG_SYS_DPAA_FMAN for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { printf(" FMAN%d: %s MHz\n", i + 1, strmhz(buf1, sysinfo.freq_fman[i])); } #endif #ifdef CONFIG_SYS_DPAA_QBMAN printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman)); #endif #ifdef CONFIG_SYS_DPAA_PME printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme)); #endif puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n"); #ifdef CONFIG_FSL_CORENET /* Display the RCW, so that no one gets confused as to what RCW * we're actually using for this boot. */ puts("Reset Configuration Word (RCW):"); for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { u32 rcw = in_be32(&gur->rcwsr[i]); if ((i % 4) == 0) printf("\n %08x:", i * 4); printf(" %08x", rcw); } puts("\n"); #endif return 0; }
int checkcpu (void) { sys_info_t sysinfo; uint lcrr; /* local bus clock ratio register */ uint clkdiv; /* clock divider portion of lcrr */ uint pvr, svr; uint fam; uint ver; uint major, minor; struct cpu_type *cpu; #ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; #else u32 ddr_ratio = 0; #endif svr = get_svr(); ver = SVR_SOC_VER(svr); major = SVR_MAJ(svr); #ifdef CONFIG_MPC8536 major &= 0x7; /* the msb of this nibble is a mfg code */ #endif minor = SVR_MIN(svr); puts("CPU: "); cpu = identify_cpu(ver); if (cpu) { puts(cpu->name); if (IS_E_PROCESSOR(svr)) puts("E"); } else { puts("Unknown"); } printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); fam = PVR_FAM(pvr); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); switch (fam) { case PVR_FAM(PVR_85xx): puts("E500"); break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); get_sys_info(&sysinfo); puts("Clock Configuration:\n"); printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000)); printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000)); switch (ddr_ratio) { case 0x0: printf(" DDR:%4lu MHz (%lu MT/s data rate), ", DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000)); break; case 0x7: printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ", DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000)); break; default: printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ", DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000)); break; } #if defined(CFG_LBC_LCRR) lcrr = CFG_LBC_LCRR; #else { volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); lcrr = lbc->lcrr; } #endif clkdiv = lcrr & 0x0f; if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { #if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \ defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536) /* * Yes, the entire PQ38 family use the same * bit-representation for twice the clock divider values. */ clkdiv *= 2; #endif printf("LBC:%4lu MHz\n", DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv); } else { printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr); } #ifdef CONFIG_CPM2 printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); #endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); return 0; }
int checkcpu(void) { sys_info_t sysinfo; uint pvr, svr; uint ver; uint major, minor; uint lcrr; /* local bus clock ratio register */ uint clkdiv; /* clock divider portion of lcrr */ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; puts("Freescale PowerPC\n"); pvr = get_pvr(); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); puts("CPU:\n"); puts(" Core: "); switch (ver) { case PVR_VER(PVR_86xx): { uint msscr0 = mfspr(MSSCR0); printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE) puts("\n Core1Translation Enabled"); debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr); } break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); svr = get_svr(); ver = SVR_SOC_VER(svr); major = SVR_MAJ(svr); minor = SVR_MIN(svr); puts(" System: "); switch (ver) { case SVR_8641: if (SVR_SUBVER(svr) == 1) { puts("8641D"); } else { puts("8641"); } break; case SVR_8610: puts("8610"); break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); get_sys_info(&sysinfo); puts(" Clocks: "); printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000); printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); #if defined(CONFIG_SYS_LBC_LCRR) lcrr = CONFIG_SYS_LBC_LCRR; #else { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_lbc_t *lbc = &immap->im_lbc; lcrr = lbc->lcrr; } #endif clkdiv = lcrr & 0x0f; if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { printf("LBC:%4lu MHz\n", sysinfo.freqSystemBus / 1000000 / clkdiv); } else { printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr); } puts(" L2: "); if (get_l2cr() & 0x80000000) puts("Enabled\n"); else puts("Disabled\n"); return 0; }
int checkcpu (void) { sys_info_t sysinfo; uint pvr, svr; uint fam; uint ver; uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; #ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; #endif int i; svr = get_svr(); ver = SVR_SOC_VER(svr); major = SVR_MAJ(svr); #ifdef CONFIG_MPC8536 major &= 0x7; /* the msb of this nibble is a mfg code */ #endif minor = SVR_MIN(svr); #if (CONFIG_NUM_CPUS > 1) volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); printf("CPU%d: ", pic->whoami); #else puts("CPU: "); #endif cpu = identify_cpu(ver); if (cpu) { puts(cpu->name); if (IS_E_PROCESSOR(svr)) puts("E"); } else { puts("Unknown"); } printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); fam = PVR_FAM(pvr); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); switch (fam) { case PVR_FAM(PVR_85xx): puts("E500"); break; default: puts("Unknown"); break; } if (PVR_MEM(pvr) == 0x03) puts("MC"); printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); get_sys_info(&sysinfo); puts("Clock Configuration:"); for (i = 0; i < CONFIG_NUM_CPUS; i++) { if (!(i & 3)) printf ("\n "); printf("CPU%d:%-4s MHz, ", i,strmhz(buf1, sysinfo.freqProcessor[i])); } printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); switch (ddr_ratio) { case 0x0: printf(" DDR:%-4s MHz (%s MT/s data rate), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; case 0x7: printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; default: printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; } if (sysinfo.freqLocalBus > LCRR_CLKDIV) printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); else printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); #endif #ifdef CONFIG_QE printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); #endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); return 0; }
unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) { unsigned int tlb_size; unsigned int ram_tlb_index; unsigned int ram_tlb_address; /* * Determine size of each TLB1 entry. */ switch (memsize_in_meg) { case 16: case 32: tlb_size = BOOKE_PAGESZ_16M; break; case 64: case 128: tlb_size = BOOKE_PAGESZ_64M; break; case 256: case 512: tlb_size = BOOKE_PAGESZ_256M; break; case 1024: case 2048: if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx)) tlb_size = BOOKE_PAGESZ_1G; else tlb_size = BOOKE_PAGESZ_256M; break; default: puts("DDR: only 16M, 32M, 64M, 128M, 256M, 512M, 1G" " and 2G are supported.\n"); /* * The memory was not able to be mapped. * Default to a small size. */ tlb_size = BOOKE_PAGESZ_64M; memsize_in_meg = 64; break; } /* * Configure DDR TLB1 entries. * Starting at TLB1 8, use no more than 8 TLB1 entries. */ ram_tlb_index = 8; ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; while (ram_tlb_address < (memsize_in_meg * 1024 * 1024) && ram_tlb_index < 16) { set_tlb(1, ram_tlb_address, ram_tlb_address, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, ram_tlb_index, tlb_size, 1); ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2)); ram_tlb_index++; } /* * Confirm that the requested amount of memory was mapped. */ return memsize_in_meg; }
int checkcpu (void) { sys_info_t sysinfo; uint pvr, svr; uint ver; uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif /* * Cornet platforms use ddr sync bit in RCW to indicate sync vs async * mode. Previous platform use ddr ratio to do the same. This * information is only for display here. */ #ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 u32 ddr_sync = 0; /* only async mode is supported */ #else u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #else /* CONFIG_FSL_CORENET */ #ifdef CONFIG_DDR_CLK_FREQ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; #endif /* CONFIG_DDR_CLK_FREQ */ #endif /* CONFIG_FSL_CORENET */ unsigned int i, core, nr_cores = cpu_numcores(); u32 mask = cpu_mask(); svr = get_svr(); major = SVR_MAJ(svr); minor = SVR_MIN(svr); if (cpu_numcores() > 1) { #ifndef CONFIG_MP puts("Unicore software on multiprocessor system!!\n" "To enable mutlticore build define CONFIG_MP\n"); #endif volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { puts("CPU: "); } cpu = gd->arch.cpu; puts(cpu->name); if (IS_E_PROCESSOR(svr)) puts("E"); printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); switch(ver) { case PVR_VER_E500_V1: case PVR_VER_E500_V2: puts("e500"); break; case PVR_VER_E500MC: puts("e500mc"); break; case PVR_VER_E5500: puts("e5500"); break; case PVR_VER_E6500: puts("e6500"); break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); if (nr_cores > CONFIG_MAX_CPUS) { panic("\nUnexpected number of cores: %d, max is %d\n", nr_cores, CONFIG_MAX_CPUS); } get_sys_info(&sysinfo); puts("Clock Configuration:"); for_each_cpu(i, core, nr_cores, mask) { if (!(i & 3)) printf ("\n "); printf("CPU%d:%-4s MHz, ", core, strmhz(buf1, sysinfo.freqProcessor[core])); } printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); #ifdef CONFIG_FSL_CORENET if (ddr_sync == 1) { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); } else { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); } #else switch (ddr_ratio) { case 0x0: printf(" DDR:%-4s MHz (%s MT/s data rate), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; case 0x7: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; default: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; } #endif #if defined(CONFIG_FSL_LBC) if (sysinfo.freqLocalBus > LCRR_CLKDIV) { printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); } #endif #if defined(CONFIG_FSL_IFC) printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); #endif #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); #endif #ifdef CONFIG_QE printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); #endif #ifdef CONFIG_SYS_DPAA_FMAN for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { printf(" FMAN%d: %s MHz\n", i + 1, strmhz(buf1, sysinfo.freqFMan[i])); } #endif #ifdef CONFIG_SYS_DPAA_QBMAN printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freqQMAN)); #endif #ifdef CONFIG_SYS_DPAA_PME printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); #endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); #ifdef CONFIG_FSL_CORENET /* Display the RCW, so that no one gets confused as to what RCW * we're actually using for this boot. */ puts("Reset Configuration Word (RCW):"); for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { u32 rcw = in_be32(&gur->rcwsr[i]); if ((i % 4) == 0) printf("\n %08x:", i * 4); printf(" %08x", rcw); } puts("\n"); #endif return 0; }
/* * 750's don't broadcast tlb invalidates so * we have to emulate that behavior. * -- Cort */ void smp_send_tlb_invalidate(int cpu) { if ( PVR_VER(mfspr(SPRN_PVR)) == 8 ) smp_message_pass(MSG_ALL_BUT_SELF, PPC_MSG_INVALIDATE_TLB, 0, 0); }
void __init initialize_cache_info(void) { struct device_node *cpu = NULL, *l2, *l3 = NULL; u32 pvr; DBG(" -> initialize_cache_info()\n"); /* * All shipping POWER8 machines have a firmware bug that * puts incorrect information in the device-tree. This will * be (hopefully) fixed for future chips but for now hard * code the values if we are running on one of these */ pvr = PVR_VER(mfspr(SPRN_PVR)); if (pvr == PVR_POWER8 || pvr == PVR_POWER8E || pvr == PVR_POWER8NVL) { /* size lsize blk sets */ init_cache_info(&ppc64_caches.l1i, 0x8000, 128, 128, 32); init_cache_info(&ppc64_caches.l1d, 0x10000, 128, 128, 64); init_cache_info(&ppc64_caches.l2, 0x80000, 128, 0, 512); init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192); } else cpu = of_find_node_by_type(NULL, "cpu"); /* * We're assuming *all* of the CPUs have the same * d-cache and i-cache sizes... -Peter */ if (cpu) { if (!parse_cache_info(cpu, false, &ppc64_caches.l1d)) DBG("Argh, can't find dcache properties !\n"); if (!parse_cache_info(cpu, true, &ppc64_caches.l1i)) DBG("Argh, can't find icache properties !\n"); /* * Try to find the L2 and L3 if any. Assume they are * unified and use the D-side properties. */ l2 = of_find_next_cache_node(cpu); of_node_put(cpu); if (l2) { parse_cache_info(l2, false, &ppc64_caches.l2); l3 = of_find_next_cache_node(l2); of_node_put(l2); } if (l3) { parse_cache_info(l3, false, &ppc64_caches.l3); of_node_put(l3); } } /* For use by binfmt_elf */ dcache_bsize = ppc64_caches.l1d.block_size; icache_bsize = ppc64_caches.l1i.block_size; cur_cpu_spec->dcache_bsize = dcache_bsize; cur_cpu_spec->icache_bsize = icache_bsize; DBG(" <- initialize_cache_info()\n"); }
int checkcpu(void) { sys_info_t sysinfo; uint pvr, svr; uint ver; uint major, minor; uint lcrr; /* local bus clock ratio register */ uint clkdiv; /* clock divider portion of lcrr */ puts("Freescale PowerPC\n"); pvr = get_pvr(); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); puts("CPU:\n"); puts(" Core: "); switch (ver) { case PVR_VER(PVR_86xx): puts("E600"); break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); svr = get_svr(); ver = SVR_VER(svr); major = SVR_MAJ(svr); minor = SVR_MIN(svr); puts(" System: "); switch (ver) { case SVR_8641: if (SVR_SUBVER(svr) == 1) { puts("8641D"); } else { puts("8641"); } break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); get_sys_info(&sysinfo); puts(" Clocks: "); printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000); printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); #if defined(CFG_LBC_LCRR) lcrr = CFG_LBC_LCRR; #else { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile ccsr_lbc_t *lbc = &immap->im_lbc; lcrr = lbc->lcrr; } #endif clkdiv = lcrr & 0x0f; if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { printf("LBC:%4lu MHz\n", sysinfo.freqSystemBus / 1000000 / clkdiv); } else { printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr); } puts(" L2: "); if (get_l2cr() & 0x80000000) puts("Enabled\n"); else puts("Disabled\n"); return 0; }