AGESA_STATUS
PcieConfigRunProcForAllWrappers (
IN UINT32 DescriptorFlags,
IN PCIe_RUN_ON_WRAPPER_CALLBACK Callback,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
PCIe_WRAPPER_CONFIG *Wrapper;
AgesaStatus = AGESA_SUCCESS;
Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_WRAPPERS, &Pcie->Header);
while (Wrapper != NULL) {
if (!(PcieLibIsVirtualDesciptor (Wrapper) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) {
if ((DescriptorFlags & DESCRIPTOR_ALL_WRAPPERS & Wrapper->Header.DescriptorFlags) != 0) {
Status = Callback (Wrapper, Buffer, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
}
Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetNextTopologyDescriptor (Wrapper, DESCRIPTOR_TERMINATE_TOPOLOGY);
}
return AgesaStatus;
}
AGESA_STATUS
PcieConfigRunProcForAllDescriptors (
IN UINT32 InDescriptorFlags,
IN UINT32 OutDescriptorFlags,
IN UINT32 TerminationFlags,
IN PCIe_RUN_ON_DESCRIPTOR_CALLBACK Callback,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
PCIe_DESCRIPTOR_HEADER *Descriptor;
AgesaStatus = AGESA_SUCCESS;
Descriptor = PcieConfigGetChild (InDescriptorFlags & DESCRIPTOR_ALL_TYPES, &Pcie->Header);
while (Descriptor != NULL) {
if ((InDescriptorFlags & Descriptor->DescriptorFlags) != 0 && (OutDescriptorFlags && Descriptor->DescriptorFlags) == 0) {
Status = Callback (Descriptor, Buffer, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
Descriptor = (PCIe_DESCRIPTOR_HEADER *) PcieConfigGetNextTopologyDescriptor (Descriptor, TerminationFlags);
}
return AgesaStatus;
}
UINT32
PcieTimerGetTimeStamp (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_WRAP_80F0_STRUCT D0F0xE4_WRAP_80F0;
D0F0xE4_WRAP_80F0.Value = PcieRegisterRead (
(PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_PCIE_WRAPPER, &Pcie->Header),
WRAP_SPACE (0, D0F0xE4_WRAP_80F0_ADDRESS),
Pcie
);
return D0F0xE4_WRAP_80F0.Value;
}
/**
* Get GNB handle
*
*
* @param[in] StdHeader Standard configuration header
*/
GNB_HANDLE *
GnbGetHandle (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCIe_PLATFORM_CONFIG *Pcie;
GNB_HANDLE *GnbHandle;
AGESA_STATUS Status;
GnbHandle = NULL;
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
ASSERT (Status == AGESA_SUCCESS);
if (Status == AGESA_SUCCESS) {
GnbHandle = (GNB_HANDLE *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header);
}
return GnbHandle;
}
VOID
PcieConfigRunProcForAllEngines (
IN UINT32 DescriptorFlags,
IN PCIe_RUN_ON_ENGINE_CALLBACK Callback,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_ENGINE_CONFIG *Engine;
Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &Pcie->Header);
while (Engine != NULL) {
if (!(PcieLibIsVirtualDesciptor (Engine) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) {
if (!((DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0 && !PcieLibIsEngineAllocated (Engine))) {
if ((Engine->Header.DescriptorFlags & DESCRIPTOR_ALL_ENGINES & DescriptorFlags) != 0) {
Callback (Engine, Buffer, Pcie);
}
}
}
Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (Engine, DESCRIPTOR_TERMINATE_TOPOLOGY);
}
}
/**
* Control port visibility in PCI config space
*
*
* @param[in] Control Control Hide/Unhide ports
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PciePortsVisibilityControlV5 (
IN PCIE_PORT_VISIBILITY Control,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_SILICON_CONFIG *SiliconList;
SiliconList = (PCIe_SILICON_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header);
while (SiliconList != NULL) {
switch (Control) {
case UnhidePorts:
PcieSiliconControlPortsV5 (UnhidePorts, SiliconList, Pcie);
break;
case HidePorts:
PcieSiliconControlPortsV5 (HidePorts, SiliconList, Pcie);
PcieSiliconEnablePortsV5 (SiliconList, Pcie);
break;
default:
ASSERT (FALSE);
}
SiliconList = (PCIe_SILICON_CONFIG *) PcieConfigGetNextTopologyDescriptor (SiliconList, DESCRIPTOR_TERMINATE_TOPOLOGY);
}
}
/**
* Helper function to dump configuration to debug out
*
*
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieConfigDebugDump (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_SILICON_CONFIG *SiliconList;
PCIe_WRAPPER_CONFIG *WrapperList;
PCIe_COMPLEX_CONFIG *ComplexList;
ComplexList = (PCIe_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_COMPLEX, &Pcie->Header);
IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config Start------------>\n");
IDS_HDT_CONSOLE (PCIE_MISC, " PSPP Policy - %s\n",
(Pcie->PsppPolicy == PsppPowerSaving) ? "Power Saving" :
(Pcie->PsppPolicy == PsppBalanceHigh) ? "Balance-High" : (
(Pcie->PsppPolicy == PsppBalanceLow) ? "Balance-Low" : (
(Pcie->PsppPolicy == PsppPerformance) ? "Performance" : (
(Pcie->PsppPolicy == PsppDisabled) ? "Disabled" : "Unknown")))
);
IDS_HDT_CONSOLE (PCIE_MISC, " GFX Workaround - %s\n",
(Pcie->GfxCardWorkaround == 0) ? "Disabled" : "Enabled"
);
IDS_HDT_CONSOLE (PCIE_MISC, " LinkL0Pooling - %dus\n",
Pcie->LinkL0Pooling
);
IDS_HDT_CONSOLE (PCIE_MISC, " LinkGpioResetAssertionTime - %dus\n",
Pcie->LinkGpioResetAssertionTime
);
IDS_HDT_CONSOLE (PCIE_MISC, " LinkReceiverDetectionPooling - %dus\n",
Pcie->LinkReceiverDetectionPooling
);
IDS_HDT_CONSOLE (PCIE_MISC, " Training Algorythm - %s\n",
(Pcie->TrainingAlgorithm == PcieTrainingStandard) ? "PcieTrainingStandard" : (
(Pcie->TrainingAlgorithm == PcieTrainingDistributed) ? "PcieTrainingDistributed" : "Unknown")
);
while (ComplexList != NULL) {
IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Complex Config Start ---------->\n");
IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", ComplexList->Header.DescriptorFlags);
IDS_HDT_CONSOLE (PCIE_MISC, " Socket ID - %d\n", ComplexList->SocketId);
SiliconList = PcieConfigGetChildSilicon (ComplexList);
while (SiliconList != NULL) {
IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Silicon Config Start -------->\n");
IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", SiliconList->Header.DescriptorFlags);
IDS_HDT_CONSOLE (PCIE_MISC, " Silicon ID - %d\n", SiliconList->SiliconId);
IDS_HDT_CONSOLE (PCIE_MISC, " Node ID - %d\n", SiliconList->NodeId);
IDS_HDT_CONSOLE (PCIE_MISC, " Host PCI Address - %d:%d:%d\n",
SiliconList->Address.Address.Bus,
SiliconList->Address.Address.Device,
SiliconList->Address.Address.Function
);
WrapperList = PcieConfigGetChildWrapper (SiliconList);
while (WrapperList != NULL) {
PcieConfigWrapperDebugDump (WrapperList);
WrapperList = PcieLibGetNextDescriptor (WrapperList);
}
IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Silicon Config End ---------->\n");
SiliconList = PcieLibGetNextDescriptor (SiliconList);
}
IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Complex Config End ------------>\n");
ComplexList = PcieLibGetNextDescriptor (ComplexList);
}
IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config End-------------->\n");
}
