AGESA_STATUS
STATIC
PcieConfigureGppEnginesLaneAllocationTN (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN UINT8 ConfigurationId
)
{
PCIe_ENGINE_CONFIG *EnginesList;
UINTN CoreLaneIndex;
UINTN PortIdIndex;
if (ConfigurationId > ((sizeof (GppLaneConfigurationTable) / (NUMBER_OF_GPP_PORTS * 2)) - 1)) {
return AGESA_ERROR;
}
EnginesList = PcieConfigGetChildEngine (Wrapper);
CoreLaneIndex = 0;
PortIdIndex = 0;
while (EnginesList != NULL) {
PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED);
EnginesList->Type.Port.StartCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
EnginesList->Type.Port.EndCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
EnginesList = PcieLibGetNextDescriptor (EnginesList);
}
return AGESA_SUCCESS;
}
/**
* Configure engine list to support lane allocation according to configuration ID.
*
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] DdiLaneConfig Lane configuration descriptor
* @param[in] ConfigurationId Configuration ID
* @retval AGESA_SUCCESS Configuration successfully applied
* @retval AGESA_ERROR Requested configuration not supported
*/
STATIC AGESA_STATUS
PcieConfigureDdiEnginesLaneAllocation (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_LANE_ALLOC_DESCRIPTOR *DdiLaneConfig,
IN UINT8 ConfigurationId
)
{
UINTN LaneIndex;
PCIe_ENGINE_CONFIG *EnginesList;
if (ConfigurationId >= DdiLaneConfig->NumberOfConfigurations) {
return AGESA_ERROR;
}
LaneIndex = ConfigurationId * DdiLaneConfig->NumberOfEngines * 2;
EnginesList = PcieConfigGetChildEngine (Wrapper);
while (EnginesList != NULL) {
if (PcieLibIsDdiEngine (EnginesList)) {
PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED);
EnginesList->EngineData.StartLane = DdiLaneConfig->ConfigTable[LaneIndex++] + Wrapper->StartPhyLane;
EnginesList->EngineData.EndLane = DdiLaneConfig->ConfigTable[LaneIndex++] + Wrapper->StartPhyLane;
}
EnginesList = PcieLibGetNextDescriptor (EnginesList);
}
return AGESA_SUCCESS;
}
AGESA_STATUS
STATIC
PcieConfigureGfxDdiEnginesLaneAllocationTN (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN UINT8 ConfigurationId
)
{
UINTN LaneIndex;
PCIe_ENGINE_CONFIG *EnginesList;
if (ConfigurationId > ((sizeof (GfxDdiLaneConfigurationTable) / (NUMBER_OF_GFX_DDIS * 2)) - 1)) {
return AGESA_ERROR;
}
LaneIndex = 0;
EnginesList = PcieConfigGetChildEngine (Wrapper);
while (EnginesList != NULL) {
if (PcieLibIsDdiEngine (EnginesList)) {
PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED);
EnginesList->EngineData.StartLane = GfxDdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
EnginesList->EngineData.EndLane = GfxDdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
}
EnginesList = PcieLibGetNextDescriptor (EnginesList);
}
return AGESA_SUCCESS;
}
