/** * Check if link fail because device does not support Gen2 * * * @param[in] CurrentEngine Pointer to engine config descriptor * @param[in] Pcie Pointer to global PCIe configuration * */ VOID PcieTrainingGen2FailV2 ( IN PCIe_ENGINE_CONFIG *CurrentEngine, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 LinkTrainingState; if (CurrentEngine->Type.Port.PortData.MiscControls.LinkSafeMode != PcieGen1) { PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_GEN2_RECOVERY, 0); CurrentEngine->Type.Port.PortData.MiscControls.LinkSafeMode = PcieGen1; PcieLinkSafeMode (CurrentEngine, Pcie); LinkTrainingState = LinkStateResetAssert; PutEventLog ( AGESA_WARNING, GNB_EVENT_BROKEN_LANE_RECOVERY, CurrentEngine->Type.Port.Address.AddressValue, 0, 0, 0, GnbLibGetHeader (Pcie) ); } else { LinkTrainingState = LinkStateTrainingFail; } PcieTrainingSetPortStateV2 (CurrentEngine, LinkTrainingState, FALSE, Pcie); }
VOID STATIC PciePortPostS3InitCallback ( IN PCIe_ENGINE_CONFIG *Engine, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { PCIE_LINK_SPEED_CAP LinkSpeedCapability; ASSERT (Engine->EngineData.EngineType == PciePortEngine); LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine, Pcie); PcieSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie); if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { PcieLinkSafeMode (Engine, Pcie); } if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { PcieForceCompliance (Engine, Pcie); } if (!Engine->Type.Port.IsSB) { if ((PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || ((Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) && (Engine->Type.Port.PortData.LinkHotplug != HotplugInboard)) || (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1))) { PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie); } else { PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie); } PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); } else { PcieTrainingSetPortState (Engine, LinkStateTrainingSuccess, FALSE, Pcie); } }
VOID STATIC PciePortPostInitCallback ( IN PCIe_ENGINE_CONFIG *Engine, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { PCIE_LINK_SPEED_CAP LinkSpeedCapability; ASSERT (Engine->EngineData.EngineType == PciePortEngine); if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { PcieLinkSafeMode (Engine, Pcie); } LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine, Pcie); PcieSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie); // Retrain only present port to Gen2 if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) && (LinkSpeedCapability > PcieGen1) && !Engine->Type.Port.IsSB) { PcieTrainingSetPortState (Engine, LinkStateRetrain, FALSE, Pcie); PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); } // Train ports forced to compliance if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { PcieForceCompliance (Engine, Pcie); PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie); } }
VOID STATIC PciePostS3PortInitCallbackML ( IN PCIe_ENGINE_CONFIG *Engine, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { PCIE_LINK_SPEED_CAP LinkSpeedCapability; PCIE_LINK_TRAINING_STATE State; ASSERT (Engine->EngineData.EngineType == PciePortEngine); LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine); PcieSetLinkSpeedCapV4 (LinkSpeedCapability, Engine, Pcie); if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { PcieLinkSafeMode (Engine, Pcie); } if (!PcieConfigIsSbPcieEngine (Engine)) { // // General Port // State = LinkStateDeviceNotPresent; if (Engine->Type.Port.PortData.LinkHotplug == HotplugDisabled || Engine->Type.Port.PortData.LinkHotplug == HotplugInboard) { // // Non hotplug device: we only check status from previous boot // if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { State = LinkStateResetExit; } } else { UINT32 PcieScratch; // // Get endpoint staus from scratch // PcieScratch = PciePortRegisterRead (Engine, DxFxxE4_x01_ADDRESS, Pcie); // // Hotplug device: we check ep status if reported // if ((PcieScratch & 0x1) == 0) { State = LinkStateResetExit; } } // // For compliance we always leave link in enabled state // if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode) { State = LinkStateResetExit; } PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); } else { // // SB port // State = LinkStateTrainingSuccess; } PcieTrainingSetPortStateV2 (Engine, State, FALSE, Pcie); }
/** * Links in compliance * * * @param[in] CurrentEngine Pointer to engine config descriptor * @param[in] Pcie Pointer to global PCIe configuration * */ VOID STATIC PcieTrainingCompliance ( IN PCIe_ENGINE_CONFIG *CurrentEngine, IN PCIe_PLATFORM_CONFIG *Pcie ) { PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE, 0); PcieTrainingSetPortStateV2 (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie); }
/** * Training fail on this port * * * @param[in] CurrentEngine Pointer to engine config descriptor * @param[in] Pcie Pointer to global PCIe configuration * */ VOID STATIC PcieTrainingFail ( IN PCIe_ENGINE_CONFIG *CurrentEngine, IN PCIe_PLATFORM_CONFIG *Pcie ) { PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_TRAINING_FAIL, 0); PcieTrainingSetPortStateV2 (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie); }
VOID STATIC PcieTrainingSuccess ( IN PCIe_ENGINE_CONFIG *CurrentEngine, IN PCIe_PLATFORM_CONFIG *Pcie ) { PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_TRAINING_SUCCESS, 0); PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie); }
VOID STATIC PcieTrainingSuccess ( IN PCIe_ENGINE_CONFIG *CurrentEngine, IN PCIe_PLATFORM_CONFIG *Pcie ) { PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_TRAINING_SUCCESS, 0); PcieTrainingSetPortStateV2 (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie); GnbLibPciRMW ( CurrentEngine->Type.Port.Address.AddressValue | DxFxx68_ADDRESS, AccessWidth32, (UINT32) ~DxFxx68_LinkBWManagementStatus_MASK, 1 << DxFxx68_LinkBWManagementStatus_OFFSET, GnbLibGetHeader (Pcie) ); }