/**
* Initialize engine data
*
*
*
* @param[in] ComplexDescriptor Pointer to user defined complex descriptor
* @param[in,out] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieMapInitializeEngineData (
IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor,
IN OUT PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_ENGINE_CONFIG *EngineList;
PCIe_ENGINE_DESCRIPTOR *EngineDescriptor;
EngineList = PcieConfigGetChildEngine (Wrapper);
while (EngineList != NULL) {
if (PcieLibIsEngineAllocated (EngineList)) {
if (EngineList->Scratch != 0xFF) {
EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, EngineList->Scratch);
LibAmdMemCopy (&EngineList->EngineData, &EngineDescriptor->EngineData, sizeof (EngineDescriptor->EngineData), GnbLibGetHeader (Pcie));
if (PcieLibIsDdiEngine (EngineList)) {
LibAmdMemCopy (&EngineList->Type.Ddi, &((PCIe_DDI_DESCRIPTOR*) EngineDescriptor)->Ddi, sizeof (PCIe_DDI_DATA), GnbLibGetHeader (Pcie));
EngineList->Type.Ddi.DisplayPriorityIndex = (UINT8) EngineList->Scratch;
} else if (PcieLibIsPcieEngine (EngineList)) {
LibAmdMemCopy (&EngineList->Type.Port, &((PCIe_PORT_DESCRIPTOR*) EngineDescriptor)->Port, sizeof (PCIe_PORT_DATA), GnbLibGetHeader (Pcie));
}
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
}
AGESA_STATUS
STATIC
PcieLnConfigureGfxDdiEnginesLaneAllocation (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN UINT8 ConfigurationId
)
{
UINTN LaneIndex;
PCIe_ENGINE_CONFIG *EnginesList;
if (ConfigurationId > ((sizeof (GfxDdiLaneConfigurationTable) / (NUMBER_OF_GFX_DDIS * 2)) - 1)) {
return AGESA_ERROR;
}
LaneIndex = 0;
EnginesList = PcieConfigGetChildEngine (Wrapper);
while (EnginesList != NULL) {
if (PcieLibIsDdiEngine (EnginesList)) {
PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED);
EnginesList->EngineData.StartLane = GfxDdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
EnginesList->EngineData.EndLane = GfxDdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
}
EnginesList = PcieLibGetNextDescriptor (EnginesList);
}
return AGESA_SUCCESS;
}
/**
* Configure engine list to support lane allocation according to configuration ID.
*
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] DdiLaneConfig Lane configuration descriptor
* @param[in] ConfigurationId Configuration ID
* @retval AGESA_SUCCESS Configuration successfully applied
* @retval AGESA_ERROR Requested configuration not supported
*/
AGESA_STATUS
PcieConfigureDdiEnginesLaneAllocationML (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_LANE_ALLOC_DESCRIPTOR *DdiLaneConfig,
IN UINT8 ConfigurationId
)
{
UINTN LaneIndex;
PCIe_ENGINE_CONFIG *EnginesList;
if (ConfigurationId >= DdiLaneConfig->NumberOfConfigurations) {
return AGESA_ERROR;
}
LaneIndex = ConfigurationId * DdiLaneConfig->NumberOfEngines * 2;
EnginesList = PcieConfigGetChildEngine (Wrapper);
while (EnginesList != NULL) {
if (PcieLibIsDdiEngine (EnginesList)) {
PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED);
EnginesList->EngineData.StartLane = DdiLaneConfig->ConfigTable[LaneIndex++] + Wrapper->StartPhyLane;
EnginesList->EngineData.EndLane = DdiLaneConfig->ConfigTable[LaneIndex++] + Wrapper->StartPhyLane;
}
EnginesList = PcieLibGetNextDescriptor (EnginesList);
}
return AGESA_SUCCESS;
}
