VOID PciePwrPowerDownUnusedLanes ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT32 UnusedLanes; IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Enter\n"); if (Wrapper->Features.PowerOffUnusedLanes != 0) { UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE, Wrapper); PcieTopologyLaneControl ( DisableLanes, UnusedLanes, Wrapper, Pcie ); } if (Wrapper->Features.PowerOffUnusedPlls != 0) { UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE, Wrapper); PciePifPllPowerDown ( UnusedLanes, Wrapper, Pcie ); } IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Exit\n"); }
VOID PciePwrPowerDownUnusedLanes ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT32 UnusedLanes; UINT32 AllLanes; IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Enter\n"); if (Wrapper->Features.PowerOffUnusedPlls != 0) { AllLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, 0, Wrapper); UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, Wrapper); if (AllLanes != UnusedLanes) { //Some lanes end up beeing used. We should keep master PLL powered up UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL, Wrapper); } PciePifPllPowerDown ( UnusedLanes, Wrapper, Pcie ); } if (Wrapper->Features.PowerOffUnusedLanes != 0) { UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE, Wrapper); PcieTopologyLaneControl ( DisableLanes, UnusedLanes, Wrapper, Pcie ); } IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Exit\n"); }
/** * Per wrapper Pcie Init prior training. * * * @param[in] Wrapper Pointer to wrapper configuration descriptor * @param[in] Buffer Pointer buffer * @param[in] Pcie Pointer to global PCIe configuration */ AGESA_STATUS STATIC PcieEarlyInitCallbackTN ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { AGESA_STATUS Status; BOOLEAN CoreConfigChanged; BOOLEAN PllConfigChanged; IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackTN Enter\n"); CoreConfigChanged = FALSE; PllConfigChanged = FALSE; PcieTopologyPrepareForReconfig (Wrapper, Pcie); Status = PcieTopologySetCoreConfig (Wrapper, &CoreConfigChanged, Pcie); ASSERT (Status == AGESA_SUCCESS); PcieTopologyApplyLaneMux (Wrapper, Pcie); PciePifSetRxDetectPowerMode (Wrapper, Pcie); PciePifSetLs2ExitTime (Wrapper, Pcie); PcieTopologySelectMasterPll (Wrapper, &PllConfigChanged, Pcie); if (CoreConfigChanged || PllConfigChanged) { PcieTopologyExecuteReconfigV4 (Wrapper, Pcie); } PcieTopologyCleanUpReconfig (Wrapper, Pcie); PcieTopologySetLinkReversalV4 (Wrapper, Pcie); if (Wrapper->Features.PowerOffUnusedPlls != 0) { PciePifPllPowerDown ( PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC | LANE_TYPE_DDI_PHY_NATIVE, Wrapper), Wrapper, Pcie ); PciePifPllInitForDdi (Wrapper, Pcie); PciePwrPowerDownDdiPllsV4 (Wrapper, Pcie); } PcieTopologyLaneControl ( DisableLanes, PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC, Wrapper), Wrapper, Pcie ); PcieSetReciverTerminationTN (Wrapper, Pcie); PcieSetDdiOwnPhyV4 (Wrapper, Pcie); PciePollPifForCompeletion (Wrapper, Pcie); PciePhyAvertClockPickers (Wrapper, Pcie); PcieEarlyCoreInitTN (Wrapper, Pcie); PcieSetSsidV4 (UserOptions.CfgGnbPcieSSID, Wrapper, Pcie); if (PcieConfigIsPcieWrapper (Wrapper)) { PcieSetDllCapTN (Wrapper, Pcie); } IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackTN Exit [%x]\n", Status); return Status; }