int main(int argc,char** argv)
{
uint8_t expected[8] = { 1,0,1,1,1,0,1,1 };
int a;
PinSetPIN_A(0);
PinSetPIN_A(0);
for (a=0;a<4;a++)
{
PinSetPIN_A(1);
if ((PinGetPIN_D() & 1) != expected[a * 2 + 0])
{
printf("Expected %d, but got %d, 0->1 transition",expected[a*2+0],(PinGetPIN_D()&1));
return 1;
}
PinSetPIN_A(0);
if ((PinGetPIN_D() & 1) != expected[a * 2 + 1])
{
printf("Expected %d, but got %d, 1->0 transition",expected[a*2+1],(PinGetPIN_D()&1));
return 1;
}
}
return 0;
}
int main(int argc,char** argv)
{
int a;
PinSetPIN_A(0);
PinSetPIN_A(0);
for (a=0;a<4;a++)
{
PinSetPIN_A(1);
printf("PIN_D == %d\n",PinGetPIN_D()&1);
PinSetPIN_A(0);
printf("PIN_D == %d\n",PinGetPIN_D()&1);
}
return 0;
}
int MEM_Handler()
{
int keepGoing=g_traceStep^1;
static unsigned char SYNC_LATCH;
static int SYNC_A_LATCH;
static int outOfRange=0;
static int NewInstructionBegun=-1;
// Watch for SYNC pulse and TYPE and latch them
if (PinGetPIN_SYNC())
{
SYNC_LATCH=PinGetPIN_D();
if (SYNC_LATCH==SYNC_FETCH)
{
SYNC_A_LATCH=PinGetPIN_A();
NewInstructionBegun=2;
if (dumpInstruction>0)
{
dumpInstruction--;
outOfRange=1;
}
else
{
outOfRange=0;
}
}
}
if (NewInstructionBegun>-1)
{
if (NewInstructionBegun==0)
{
if (outOfRange)
Disassemble(SYNC_A_LATCH);
if (isBreakpoint(SYNC_A_LATCH))
g_instructionStep=1;
if (g_instructionStep)
keepGoing=0;
}
NewInstructionBegun--;
}
// CPU INPUT expects data to be available on T2 state so we can do that work on the PIN_SYNC itself
// Assume memory has no latency
if (PinGetPIN_SYNC())
{
if (SYNC_LATCH==SYNC_FETCH || SYNC_LATCH==SYNC_STACK_READ || SYNC_LATCH==SYNC_MEM_READ)
{
if (PinGetPIN_A()>0x3FFF)
{
printf("Out of bounds read : %04X | masterClock : %d\n",PinGetPIN_A(),masterClock);
}
if ((PinGetPIN_A()&0x2000) == 0x2000)
{
PinSetPIN_D(Ram[PinGetPIN_A()&0x1FFF]);
}
else
{
PinSetPIN_D(Rom[PinGetPIN_A()&0x1FFF]);
}
if (dumpInstruction>0)
{
printf("Reading : %04X - %02X\n",PinGetPIN_A(),PinGetPIN_D());
}
PinSetPIN_READY(1);
PIN_BUFFER_READY=1;
}
else if (SYNC_LATCH==SYNC_STACK_WRITE || SYNC_LATCH==SYNC_MEM_WRITE || SYNC_LATCH==SYNC_OUTPUT)
{
PinSetPIN_READY(1);
PIN_BUFFER_READY=1;
}
else if (SYNC_LATCH==SYNC_INPUT)
{
PinSetPIN_D(HandleIOPortRead(PinGetPIN_A()&0xFF));
PinSetPIN_READY(1);
PIN_BUFFER_READY=1;
}
else if (SYNC_LATCH==SYNC_INT_ACK)
{
PinSetPIN_D(NEXTINT);
}
else
{
printf("Error unknown sync state!!! PIN_D = %02X\n",PinGetPIN_D());
exit(12);
}
}
// CPU OUTPUT expects device to have signalled readyness to capture at state T2, but capture occurs at T3 (when _WR is low)
if (PinGetPIN__WR() == 0)
{
if (SYNC_LATCH==SYNC_STACK_WRITE || SYNC_LATCH==SYNC_MEM_WRITE)
{
if ((PinGetPIN_A()&0x2000)==0x2000)
{
Ram[PinGetPIN_A()&0x1FFF]=PinGetPIN_D();
}
}
else if (SYNC_LATCH==SYNC_OUTPUT)
{
HandleIOPortWrite(PinGetPIN_A()&0xFF,PinGetPIN_D());
}
}
return keepGoing;
}
