/* * This is very similar to ide_setup_ports except that addresses * are pretranslated for q40 ISA access */ void q40_ide_setup_ports ( hw_regs_t *hw, unsigned long base, int *offsets, unsigned long ctrl, unsigned long intr, ide_ack_intr_t *ack_intr, /* * ide_io_ops_t *iops, */ int irq) { int i; memset(hw, 0, sizeof(hw_regs_t)); for (i = 0; i < IDE_NR_PORTS; i++) { /* BIG FAT WARNING: assumption: only DATA port is ever used in 16 bit mode */ if ( i==0 ) hw->io_ports[i] = Q40_ISA_IO_W(base + offsets[i]); else hw->io_ports[i] = Q40_ISA_IO_B(base + offsets[i]); } hw->irq = irq; hw->dma = NO_DMA; hw->ack_intr = ack_intr; /* * hw->iops = iops; */ }
static void q40_ide_setup_ports(struct ide_hw *hw, unsigned long base, int irq) { memset(hw, 0, sizeof(*hw)); hw->io_ports.data_addr = Q40_ISA_IO_W(base); hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1); hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2); hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3); hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4); hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5); hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6); hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7); hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206); hw->irq = irq; }
/* * Addresses are pretranslated for Q40 ISA access. */ static void q40_ide_setup_ports(hw_regs_t *hw, unsigned long base, ide_ack_intr_t *ack_intr, int irq) { memset(hw, 0, sizeof(hw_regs_t)); /* BIG FAT WARNING: assumption: only DATA port is ever used in 16 bit mode */ hw->io_ports.data_addr = Q40_ISA_IO_W(base); hw->io_ports.error_addr = Q40_ISA_IO_B(base + 1); hw->io_ports.nsect_addr = Q40_ISA_IO_B(base + 2); hw->io_ports.lbal_addr = Q40_ISA_IO_B(base + 3); hw->io_ports.lbam_addr = Q40_ISA_IO_B(base + 4); hw->io_ports.lbah_addr = Q40_ISA_IO_B(base + 5); hw->io_ports.device_addr = Q40_ISA_IO_B(base + 6); hw->io_ports.status_addr = Q40_ISA_IO_B(base + 7); hw->io_ports.ctl_addr = Q40_ISA_IO_B(base + 0x206); hw->irq = irq; hw->ack_intr = ack_intr; hw->chipset = ide_generic; }