/* Sample application for printing the Quark API version over stdout */
int main(void)
{
QM_PRINTF("Quark API version number (int) is %u\n", QM_VER_API_UINT);
QM_PRINTF("Quark API version number (string) is %s\n",
QM_VER_API_STRING);
return 0;
}
int main(void)
{
qm_rtc_config_t rtc_cfg;
unsigned int count = 0;
/* loop_max : Maximum number of iterations.
* A value of 50 will run the application for roughly 30s.
*/
const unsigned int loop_max = 50;
gpio_init();
pin_mux_setup();
gpio_set_out(BOARD_LED_PIN, 0); /* Configure the onboard LED pin. */
/* Clear Screen. */
QM_PUTS("Starting: Power Profiler");
QM_PUTS("Low power mode example.");
QM_PRINTF("Increment = %d\n", QM_RTC_ALARM_SECOND(CLK_RTC_DIV_1));
clk_periph_enable(CLK_PERIPH_RTC_REGISTER | CLK_PERIPH_CLK);
/* Initialise RTC configuration: Run, but don't interrupt. */
rtc_cfg.init_val = 0;
rtc_cfg.alarm_en = 0;
rtc_cfg.alarm_val = QM_RTC_ALARM_SECOND(CLK_RTC_DIV_1);
rtc_cfg.callback = rtc_example_callback;
rtc_cfg.prescaler = CLK_RTC_DIV_1;
qm_rtc_set_config(QM_RTC_0, &rtc_cfg);
QM_IR_UNMASK_INT(QM_IRQ_RTC_0_INT);
QM_IRQ_REQUEST(QM_IRQ_RTC_0_INT, qm_rtc_0_isr);
#if (!QM_SENSOR)
test_clock_rates();
#endif
/* Enable the RTC Interrupt. */
rtc_cfg.alarm_en = 1;
qm_rtc_set_config(QM_RTC_0, &rtc_cfg);
count = 0;
while (++count < loop_max) {
QM_PRINTF("\nC:%d R:%d => ", count, rtc_tick);
slow_mode_test();
halt_test();
core_sleep_test();
/* TODO : Enable soc_sleep test for c1000. */
soc_sleep_test();
/* TODO : Enable soc_deep_sleep test for d2000 and c1000. */
soc_deep_sleep_test();
}
SOC_WATCH_TRIGGER_FLUSH();
QM_PUTS("Finished: Power Profiler");
return 0;
}
static void spi_transfer_irq(void)
{
QM_PUTS("Reading CHIPID in IRQ mode.");
tx_buffer[0] = 0x80; /* Read chip ID. */
/* Set up transfer values. */
qm_ss_spi_async_transfer_t irq_trans;
irq_trans.rx = rx_buffer;
irq_trans.tx = tx_buffer;
irq_trans.rx_len = BUFFER_SIZE;
irq_trans.tx_len = BUFFER_SIZE;
irq_trans.callback_data = NULL;
irq_trans.callback = spi_cb;
/* Register interrupts. */
qm_ss_irq_request(QM_SS_IRQ_SPI_0_ERROR_INT, qm_ss_spi_0_error_isr);
qm_ss_irq_request(QM_SS_IRQ_SPI_0_RX_AVAIL_INT,
qm_ss_spi_0_rx_avail_isr);
qm_ss_irq_request(QM_SS_IRQ_SPI_0_TX_REQ_INT, qm_ss_spi_0_tx_req_isr);
tx_buffer[0] = 0x80; /* Read chip ID. */
err_code = 0;
xfer_active = true;
/* Set SPI configuration. */
qm_ss_spi_set_config(spi, &conf);
/* Enable clock for SPI 0. */
ss_clk_spi_enable(QM_SS_SPI_0);
/* Select slave and do the actual SPI transfer. */
qm_ss_spi_slave_select(spi, select);
qm_ss_spi_irq_transfer(spi, &irq_trans);
while (xfer_active)
;
/* Disable clock for SPI 0. */
ss_clk_spi_disable(QM_SS_SPI_0);
if (err_code != 0) {
QM_PRINTF(
"Error: SPI transfer failed. (%d frames transmitted)\n",
transfer_len);
} else if (rx_buffer[1] == 0xd1) {
QM_PUTS("CHIPID = 0x1d");
} else {
QM_PRINTF("Error: CHIPID doesn't match 0x%x != 0xd1.\n",
rx_buffer[1]);
}
}
/* Sample application for printing the QMSI API and ROM version over stdout */
int main(void)
{
uint32_t rom_version = qm_ver_rom();
QM_PRINTF("Starting: Version\n");
QM_PRINTF("QMSI API version number (int) is %u\n", QM_VER_API_UINT);
QM_PRINTF("QMSI API version number (string) is %s\n",
QM_VER_API_STRING);
QM_PRINTF("QMSI ROM version number (int) is %u\n",
(unsigned int)rom_version);
QM_PRINTF("Finished: Version\n");
return 0;
}
int main(void)
{
qm_gpio_port_config_t cfg;
QM_PUTS("Starting: AON GPIO");
/* Request IRQ and write GPIO port config. */
cfg.direction = 0; /* Set all pins as inputs. */
cfg.int_en = BIT(PIN_INTR); /* Interrupt enabled. */
cfg.int_type = BIT(PIN_INTR); /* Edge sensitive interrupt. */
cfg.int_polarity = ~BIT(PIN_INTR); /* Falling edge. */
cfg.int_debounce = BIT(PIN_INTR); /* Debounce enabled. */
cfg.int_bothedge = 0; /* Both edge disabled. */
cfg.callback = aon_gpio_example_callback;
cfg.callback_data = NULL;
qm_irq_request(QM_IRQ_AON_GPIO_0_INT, qm_aon_gpio_0_isr);
qm_gpio_set_config(QM_AON_GPIO_0, &cfg);
QM_PUTS("AON GPIO set up, press 'PB0' to trigger the interrupt");
/* Wait for the AON GPIO callback to be invoked and print the status. */
while (!callback_invoked)
;
QM_PRINTF("Status of AON GPIO callback = 0x%u \n", callback_status);
QM_PUTS("Finished: AON GPIO");
return 0;
}
void state_machine(int cur_state, bool *sleep_ready, bool *do_soc_sleep)
{
static int prev_state = -1;
/* Values for do_soc_sleep and sleep_ready for each states. */
#if !QM_SENSOR
bool states[5][2] = {{true, false}, /* x86 requests sleep, SS NAK */
{false, false}, /* SS requests sleep, x86 NAK */
{true, false}, /* x86 requests sleep, SS ACK */
{false, true}, /* SS requests sleep, x86 ACK */
{true, true}}; /* Both request sleep */
#else
bool states[5][2] = {{false, false}, /* x86 requests sleep, SS NAK */
{true, false}, /* SS requests sleep, x86 NAK */
{false, true}, /* x86 requests sleep, SS ACK */
{true, false}, /* SS requests sleep, x86 ACK */
{true, true}}; /* Both request sleep */
#endif
if (prev_state == cur_state) {
return;
}
QM_PRINTF("\nState number: %d\n", cur_state);
prev_state = cur_state;
if (cur_state < 5) {
*do_soc_sleep = states[cur_state][0];
*sleep_ready = states[cur_state][1];
}
}
int main(void)
{
qm_rtc_config_t rtc_cfg;
unsigned int count = 0;
/* Maximum number of 3-second iterations. */
const unsigned int loop_max = 5;
gpio_init();
gpio_set_out(BOARD_LED_PIN, 0); /* Configure the onboard LED pin. */
/* Clear Screen. */
QM_PUTS("Starting: Power Profiler");
QM_PUTS("Low power mode example.");
QM_PRINTF("Increment = %d\n", QM_RTC_ALARM_SECOND(CLK_RTC_DIV_1));
clk_periph_enable(CLK_PERIPH_RTC_REGISTER | CLK_PERIPH_CLK);
/* Initialise RTC configuration: Run, but don't interrupt. */
rtc_cfg.init_val = 0;
rtc_cfg.alarm_en = 0;
rtc_cfg.alarm_val = QM_RTC_ALARM_SECOND(CLK_RTC_DIV_1);
rtc_cfg.callback = rtc_example_callback;
rtc_cfg.prescaler = CLK_RTC_DIV_1;
qm_rtc_set_config(QM_RTC_0, &rtc_cfg);
qm_irq_request(QM_IRQ_RTC_0_INT, qm_rtc_0_isr);
test_clock_rates();
/* Enable the RTC Interrupt. */
rtc_cfg.alarm_en = 1;
qm_rtc_set_config(QM_RTC_0, &rtc_cfg);
count = 0;
while (++count < loop_max) {
QM_PRINTF("\nC:%d R:%d => ", count, rtc_tick);
slow_mode_test();
halt_test();
sleep_test();
#if DEEP_SLEEP
deep_sleep_test();
#endif
}
QM_PUTS("Finished: Power Profiler");
return 0;
}
int main(void)
{
uint32_t c_val = 0, pt_val = 0;
qm_aonpt_config_t cfg;
QM_PUTS("Starting: Always-on Counter");
/* Always-on Counter enable and read value. */
qm_aonc_enable(QM_AONC_0);
if (qm_aonc_get_value(QM_AONC_0, &c_val) == 0) {
QM_PRINTF("Always-on Counter value: %u\n", c_val);
} else {
QM_PUTS("Error: Could not read aonc value.");
}
/* Request an IRQ and write the Always-on Periodic Timer config. */
cfg.count = 0x1000; /* 0.125 seconds. */
cfg.int_en = true; /* Interrupts enabled. */
cfg.callback = aonpt_example_callback;
qm_irq_request(QM_IRQ_AONPT_0_INT, qm_aonpt_0_isr);
qm_aonpt_set_config(QM_AONC_0, &cfg);
/* Wait for the defined number of callbacks be invoked. */
while (NUM_CALLBACKS > callback_count)
;
QM_PRINTF("Periodic Timer callback fired %d times.\n", callback_count);
/* Get the value of the Always-on Periodic Timer. */
if (qm_aonpt_get_value(QM_AONC_0, &c_val) == 0) {
QM_PRINTF("Always-on Periodic Timer value: %u\n", pt_val);
} else {
QM_PUTS("Error: Could not read Periodic timer value");
}
/* Disable the always-on periodic timer interrupt. */
cfg.int_en = false;
qm_aonpt_set_config(QM_AONC_0, &cfg);
QM_PUTS("Finished: Always-on counter");
return 0;
}
int main(void)
{
volatile uint32_t delay;
uint32_t c_val = 0, pt_val = 0;
qm_aonpt_config_t cfg;
QM_PUTS("\nAlways-on Counter example app\n");
/* Always-on Counter enable, disable and read value */
qm_aonc_disable(QM_SCSS_AON_0);
qm_aonc_enable(QM_SCSS_AON_0);
c_val = qm_aonc_get_value(QM_SCSS_AON_0);
if (c_val) {
QM_PRINTF("Always-on Counter value: %lu\n", c_val);
} else {
QM_PRINTF("ERROR: Could not read aonc value\n");
}
/* Request an IRQ and write the Always-on Periodic Timer config */
cfg.count = 0x10000;
cfg.int_en = true;
cfg.callback = aonpt_example_callback;
qm_irq_request(QM_IRQ_AONPT_0, qm_aonpt_isr_0);
qm_aonpt_set_config(QM_SCSS_AON_0, &cfg);
/* The AON Periodic Timer runs from the RTC clock at 32KHz (rather than
* the system clock which is 32MHz) so we need to spin for a few cycles
* allow the register change to propagate */
for (delay = 500; delay--;) {
}
/* Get the value of the Always-on Periodic Timer */
pt_val = qm_aonpt_get_value(QM_SCSS_AON_0);
if (pt_val) {
QM_PRINTF("Always-on Periodic Timer value: %lu\n", pt_val);
} else {
QM_PRINTF("ERROR: Could not read Periodic timer value\n\n");
}
QM_PUTS("Always-on counter example app complete\n");
return 0;
}
static void read_and_echo_data(void)
{
/* Read all data and echo it back. */
size_t bytes_read = 0;
while (bytes_read == 0) {
read_data((uint8_t *)data_buf, &bytes_read, sizeof(data_buf));
}
write_data(data_buf, bytes_read);
QM_PRINTF("Echo done for %d bytes\n", bytes_read);
}
int send_msg(sleep_msg_t msg)
{
tx_data.ctrl = msg;
if (0 != qm_mbox_ch_write(mbox_tx, &tx_data)) {
QM_PRINTF("Error: mbox %d write\n", mbox_tx);
return 1;
}
return 0;
}
static void test_clock_rates(void)
{
uint64_t diff;
unsigned int rtc_start, rtc_end = 0;
/* Set clock to 32 MHz. */
clk_sys_set_mode(CLK_SYS_CRYSTAL_OSC, CLK_SYS_DIV_1);
diff = spin_loop(1000, &rtc_start, &rtc_end);
clk_sys_set_mode(CLK_SYS_CRYSTAL_OSC, CLK_SYS_DIV_1);
QM_PRINTF("Fast Clk loop: %d TSC ticks; RTC diff=%d : %d - %d\n",
(unsigned int)(diff & 0xffffffff), rtc_end - rtc_start,
rtc_end, rtc_start);
/* Set clock to 4 MHz. */
clk_sys_set_mode(CLK_SYS_CRYSTAL_OSC, CLK_SYS_DIV_8);
diff = spin_loop(1000, &rtc_start, &rtc_end);
clk_sys_set_mode(CLK_SYS_CRYSTAL_OSC, CLK_SYS_DIV_1);
/* Output is limited to 32 bits here. */
QM_PRINTF("Slow Clk loop: %d TSC ticks; RTC diff=%d : %d - %d\n",
(unsigned int)(diff & 0xffffffff), rtc_end - rtc_start,
rtc_end, rtc_start);
}
static void print_accel_callback(void)
{
bmc150_accel_t accel = {0};
qm_rc_t rc;
rc = bmc150_read_accel(&accel);
QM_PRINTF("rc %d x %d y %d z %d\n", rc, accel.x, accel.y, accel.z);
#if (__IPP_ENABLED__)
print_axis_stats(accel.z);
#endif
qm_rtc_set_alarm(QM_RTC_0, (QM_RTC[QM_RTC_0].rtc_ccvr + ALARM));
}
/* Check last error code and start a new transfer. */
void start_another_transfer(dma_channel_desc_t *p_chan_desc)
{
/*
* Check last error code. If last transfer ended with no
* error, another transfer can be started.
*/
if (irq_error_code) {
QM_PRINTF("Error: Transfer with error Code: %u\n",
irq_error_code);
} else {
QM_PRINTF("Transfer Loop %d Complete with Data Length: %u\n",
transfer_count, irq_len);
transfer_count++;
/* Start a new transfer. */
if (transfer_count < NUM_TRANSFERS) {
start_transfer(p_chan_desc, (uint32_t *)tx_data,
(uint32_t *)rx_data[transfer_count],
strlen(tx_data));
}
}
}
int main()
{
uint8_t payload[3];
QM_PRINTF("Simple nRF24L01 receive example\r\n");
#if defined(RF24_SPI_MULTIBYTE)
QM_PRINTF("Using multibyte SPI transfers\r\n");
#else
QM_PRINTF("Using single byte SPI transfers\r\n");
#endif
if (rf24_init()) {
QM_PRINTF("Failed to initialize nRF24L01\r\n");
} else {
QM_PRINTF("Initialized nRF24L01 radio. ");
if (rf24_is_plus()) {
QM_PRINTF("Detected nRF24L01+\r\n");
} else {
QM_PRINTF("Detected nRF24L01\r\n");
}
}
rf24_set_retries(15,15);
rf24_open_reading_pipe_uint64(0, 0xAA55AA55AA);
rf24_start_listening();
clk_sys_udelay(1000);
while(1) {
if (rf24_available()) {
rf24_read(payload, 3);
QM_PRINTF("Received data ... %d,%d,%d\r\n",payload[0],payload[1],payload[2]);
#if !defined (RF24_MINIMAL)
rf24_print_details();
#endif
}
}
return 0;
}
int main(void)
{
qm_ss_gpio_state_t state;
qm_ss_gpio_port_config_t conf;
QM_PUTS("Starting: SS GPIO");
pin_mux_setup();
/* Request IRQ and write SS GPIO port config. */
conf.direction = BIT(PIN_OUT); /* Set PIN_OUT to output. */
conf.int_en = BIT(PIN_INTR); /* Interrupt enabled. */
conf.int_type = BIT(PIN_INTR); /* Edge sensitive interrupt. */
conf.int_polarity = ~BIT(PIN_INTR); /* Falling edge. */
conf.int_debounce = BIT(PIN_INTR); /* Debounce enabled. */
conf.callback = gpio_example_callback;
conf.callback_data = NULL;
/* Enable clock. */
ss_clk_gpio_enable(QM_SS_GPIO_0);
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->ss_gpio_0_int_mask);
qm_ss_irq_request(QM_SS_IRQ_GPIO_0_INT, qm_ss_gpio_0_isr);
qm_ss_gpio_set_config(QM_SS_GPIO_0, &conf);
/* Clear PIN_OUT to trigger PIN_INTR interrupt. */
qm_ss_gpio_set_pin(QM_SS_GPIO_0, PIN_OUT);
qm_ss_gpio_clear_pin(QM_SS_GPIO_0, PIN_OUT);
/* Wait for callback to be invoked */
while (!callback_invoked)
;
QM_PRINTF("Callback fired, status: 0x%x\n", callback_status);
if (qm_ss_gpio_read_pin(QM_SS_GPIO_0, PIN_OUT, &state)) {
QM_PUTS("Error: read pin failed");
return 1;
}
if (state != QM_SS_GPIO_LOW) {
QM_PUTS("Error: SS GPIO pin out comparison failed");
return 1;
}
QM_PUTS("Finished: SS GPIO");
return 0;
}
int main(void)
{
bool do_soc_sleep, sleep_ready;
int current_state = 0;
QM_PRINTF("Starting: Sleep multicore %s\n", MYNAME);
#if !QM_SENSOR
sensor_activation();
#endif
init_mailbox();
while (current_state < 5) {
clk_sys_udelay(DELAY_1_SECOND);
state_machine(current_state, &sleep_ready, &do_soc_sleep);
/*
* In that order, we can force the race condition when both
* request sleep.
*/
if (do_soc_sleep) {
request_soc_sleep();
current_state++;
} else if (mbox_cb_fired) {
mbox_cb_fired = false;
qm_mbox_ch_read(mbox_rx, &rx_data);
if (rx_data.ctrl == SLEEP_REQ) {
soc_sleep_requested(sleep_ready);
current_state++;
}
}
}
QM_PRINTF("Finished: Sleep multicore %s\n", MYNAME);
return 0;
}
/* QMSI wdt app example */
int main(void)
{
qm_wdt_config_t wr_cfg;
QM_PRINTF("Starting: WDT\n");
wr_cfg.timeout = QM_WDT_2_POW_17_CYCLES;
wr_cfg.mode = QM_WDT_MODE_INTERRUPT_RESET;
wr_cfg.callback = wdt_example_callback;
wdt_fired = 0;
qm_wdt_set_config(QM_WDT_0, &wr_cfg);
qm_irq_request(QM_IRQ_WDT_0, qm_wdt_isr_0);
qm_wdt_start(QM_WDT_0);
/* Wait for WDT to fire 10 times and then finish. */
while (wdt_fired < MAX_WDT_FIRINGS) {
}
QM_PRINTF("Watchdog fired %d times\n", MAX_WDT_FIRINGS);
QM_PRINTF("Finished: WDT\n");
return 0;
}
int main(void)
{
unsigned int cnt;
QM_PUTS("Demonstrating QM_PUTS/QM_PRINTF functionality");
for (cnt = 0; cnt < 10; cnt++) {
QM_PRINTF("%d\n", cnt);
}
QM_PUTS("Demonstrating QM_ASSERT functionality");
QM_ASSERT(1 == 0);
return 0;
}
/* Helper function to compare two buffers of size EEPROM_PAGE_SIZE_BYTES. */
void eeprom_compare_page(uint8_t *write_data, uint8_t *read_data)
{
uint32_t i;
for (i = 0; i < EEPROM_PAGE_SIZE_BYTES; i++) {
/*
* Write_data contains the address in first 2 bytes, so offset
* comparison by 2 bytes.
*/
if (write_data[i + EEPROM_ADDR_SIZE_BYTES] != read_data[i]) {
QM_PUTS("Error: Data compare failed");
return;
}
}
QM_PRINTF("Data compare OK:\n%s \n", (const char *)read_data);
}
static void print_axis_stats(int16_t value)
{
static uint16_t index = 0;
static uint16_t count = 0;
float32_t mean, var, rms;
samples[index] = value;
index = (index + 1) % SAMPLES_SIZE;
count = count == SAMPLES_SIZE ? SAMPLES_SIZE : count + 1;
ippsq_rms_f32(samples, count, &rms);
ippsq_var_f32(samples, count, &var);
ippsq_mean_f32(samples, count, &mean);
QM_PRINTF("rms %d var %d mean %d\n", (int) rms, (int) var, (int) mean);
}
int main(void)
{
uint32_t baudrate, dtr = 0;
int bytes_read;
QM_PUTS("Starting: USB CDC ACM Example");
qm_irq_request(QM_IRQ_USB_0_INT, qm_usb_0_isr);
/* Enable the USB VBUS on Quark SE DevBoard. */
enable_usb_vbus();
/* Init USB CDC ACM. */
cdc_acm_init();
QM_PUTS("CDC ACM Initialized. Waiting for DTR.");
do {
cdc_acm_line_ctrl_get(LINE_CTRL_DTR, &dtr);
} while (!dtr);
QM_PUTS("DTR set, start test.");
/* Wait 1 sec for the host to do all settings. */
clk_sys_udelay(ONE_SEC_UDELAY);
if (cdc_acm_line_ctrl_get(LINE_CTRL_BAUD_RATE, &baudrate)) {
QM_PUTS("Failed to get baudrate, ret code.");
} else {
QM_PRINTF("Baudrate detected: %d\n", baudrate);
}
QM_PUTS("USB CDC ACM set. Switch to the USB Serial Console.");
cdc_acm_irq_callback_set(interrupt_handler);
write_data(banner1, strlen(banner1));
write_data(banner2, strlen(banner2));
/* Enable RX interrupts. */
cdc_acm_irq_rx_enable();
/* Echo the received data. */
while (1) {
read_and_echo_data(&bytes_read);
}
return 0;
}
static int write_data(const char *buf, int len)
{
int part = 0;
while (part < len) {
if (cdc_acm_tx_busy) {
QM_PUTS("CDC ACM Busy (Package dropped.)");
return -EIO;
}
int size = cdc_acm_fifo_fill((uint8_t *)buf, len - part);
if (size < 0) {
QM_PRINTF("CDC ACM Write Error %d.\n", size);
return size;
}
part += size;
buf += size;
}
return 0;
}
static void spi_transfer_polled(void)
{
QM_PUTS("Reading CHIPID in polled mode.");
tx_buffer[0] = 0x80; /* Read chip ID. */
/* Set up transfer values. */
qm_ss_spi_transfer_t trans;
trans.rx = rx_buffer;
trans.tx = tx_buffer;
trans.rx_len = BUFFER_SIZE;
trans.tx_len = BUFFER_SIZE;
err_code = 0;
/* Set SPI configuration. */
err_code = qm_ss_spi_set_config(spi, &conf);
/* Enable clock for SPI 0. */
ss_clk_spi_enable(QM_SS_SPI_0);
/* Select slave and do the actual SPI transfer. */
err_code |= qm_ss_spi_slave_select(spi, select);
err_code |= qm_ss_spi_transfer(spi, &trans, NULL);
/* Disable clock for SPI 0. */
ss_clk_spi_disable(QM_SS_SPI_0);
if (err_code != 0) {
QM_PUTS("Error: SPI transfer failed.");
} else if (rx_buffer[1] == 0xd1) {
QM_PUTS("CHIPID = 0x1d");
} else {
QM_PRINTF("Error: CHIPID doesn't match 0x%x != 0xd1.\n",
rx_buffer[1]);
}
}
/* Hello world example app */
int main(void)
{
QM_PRINTF("hello, world\n");
return 0;
}
int main(void)
{
#if (QUARK_D2000)
int i;
qm_adc_config_t cfg;
qm_adc_xfer_t xfer;
qm_adc_channel_t channels[] = {QM_ADC_CH_8, QM_ADC_CH_9};
uint32_t samples_polled[NUM_SAMPLES_POLLED] = {0};
uint32_t samples_interrupt[NUM_SAMPLES_INTERRUPT] = {0};
QM_PUTS("\nADC example app start");
/* Enable the ADC and set the clock divisor */
clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_ADC |
CLK_PERIPH_ADC_REGISTER);
clk_adc_set_div(100); /* ADC clock is 320KHz @ 32MHz */
/* Set up pinmux */
qm_pmux_select(QM_PIN_ID_8, QM_PMUX_FN_1);
qm_pmux_select(QM_PIN_ID_9, QM_PMUX_FN_1);
qm_pmux_input_en(QM_PIN_ID_8, true);
qm_pmux_input_en(QM_PIN_ID_9, true);
/* Set the mode and calibrate */
qm_adc_set_mode(QM_ADC_0, QM_ADC_MODE_NORM_CAL);
qm_adc_calibrate(QM_ADC_0);
/* Set up config */
cfg.window = 20; /* Clock cycles between the start of each sample */
cfg.resolution = QM_ADC_RES_12_BITS;
qm_adc_set_config(QM_ADC_0, &cfg);
/*******************************
* ADC polled mode example
******************************/
QM_PUTS("ADC polled mode");
/* Set up xfer */
xfer.ch = channels;
xfer.ch_len = NUM_CHANNELS;
xfer.samples = samples_polled;
xfer.samples_len = NUM_SAMPLES_POLLED;
/* Run the conversion */
if (qm_adc_convert(QM_ADC_0, &xfer)) {
QM_PUTS("ERROR: qm_adc_convert failed");
return 1;
}
/* Print the values of the samples */
for (i = 0; i < NUM_SAMPLES_POLLED; i++) {
QM_PRINTF("%d:%x ", i, (unsigned int)samples_polled[i]);
}
/*******************************
* ADC interrupt mode example
******************************/
QM_PUTS("\nADC interrupt mode");
qm_irq_request(QM_IRQ_ADC_0, qm_adc_0_isr);
/* Set up xfer */
xfer.ch = channels;
xfer.ch_len = NUM_CHANNELS;
xfer.samples = samples_interrupt;
xfer.samples_len = NUM_SAMPLES_INTERRUPT;
xfer.complete_callback = complete_callback;
xfer.error_callback = error_callback;
if (qm_adc_irq_convert(QM_ADC_0, &xfer)) {
QM_PUTS("ERROR: qm_adc_irq_convert failed");
return 1;
}
/* Wait for the callback */
while (false == complete)
;
for (i = 0; i < NUM_SAMPLES_INTERRUPT; i++) {
QM_PRINTF("%d:%x ", i, (unsigned int)samples_interrupt[i]);
}
QM_PUTS("\nADC example app complete");
#endif /* QUARK_D2000 */
return 0;
}
int main(void)
{
qm_dma_channel_config_t cfg = {0};
static dma_channel_desc_t chan_desc;
int return_code, i;
QM_PUTS("Starting: DMA");
/*
* Request the required interrupts. Depending on the channel used a
* different isr is set:
* qm_irq_request(QM_IRQ_DMA_0_INT_<channel>,
* qm_dma_0_isr_<channel>)
*/
qm_irq_request(QM_IRQ_DMA_0_INT_0, qm_dma_0_isr_0);
qm_irq_request(QM_IRQ_DMA_0_ERROR_INT, qm_dma_0_error_isr);
/* Set the controller and channel IDs. */
chan_desc.controller_id = QM_DMA_0;
chan_desc.channel_id = QM_DMA_CHANNEL_0;
return_code = qm_dma_init(chan_desc.controller_id);
if (return_code) {
QM_PUTS("ERROR: qm_dma_init");
}
/* Configure DMA channel. */
cfg.channel_direction = QM_DMA_MEMORY_TO_MEMORY;
cfg.source_transfer_width = QM_DMA_TRANS_WIDTH_8;
cfg.destination_transfer_width = QM_DMA_TRANS_WIDTH_8;
cfg.source_burst_length = QM_DMA_BURST_TRANS_LENGTH_1;
cfg.destination_burst_length = QM_DMA_BURST_TRANS_LENGTH_1;
cfg.client_callback = transfer_callback;
cfg.transfer_type = QM_DMA_TYPE_SINGLE;
/*
* Set the context as the channel descriptor. This will allow the
* descriptor to be available in the callback.
* The callback context is not actually used in this app. It is
* provided as an example.
*/
cfg.callback_context = (void *)&chan_desc;
return_code = qm_dma_channel_set_config(chan_desc.controller_id,
chan_desc.channel_id, &cfg);
if (return_code) {
QM_PUTS("ERROR: qm_dma_channel_set_config");
}
/* Do the transfers. */
do_transfer(&chan_desc);
QM_PUTS("Each RX buffer should contain the full TX buffer string.");
QM_PRINTF("TX data: %s\n", tx_data);
/* Print copied data. */
for (i = 0; i < NUM_TRANSFERS; i++) {
QM_PRINTF("RX data Loop %d: %s\n", i, rx_data[i]);
}
/* Configure DMA channel for multiblock usage. */
cfg.transfer_type = QM_DMA_TYPE_MULTI_LL;
return_code = qm_dma_channel_set_config(chan_desc.controller_id,
chan_desc.channel_id, &cfg);
if (return_code) {
QM_PUTS("ERROR: qm_dma_channel_set_config");
}
/* Do the multiblock transfer. */
do_transfer_multi(&chan_desc);
QM_PRINTF("RX data (multiblock transfer):\n");
rx_data[1][0] = '\0';
printf("%s\n", (char *)&rx_data[0][0]);
QM_PUTS("Finished: DMA");
return 0;
}
static void do_transfer_multi(dma_channel_desc_t *p_chan_desc)
{
int return_code;
qm_dma_multi_transfer_t multi_transfer = {0};
/*
* We own the memory where the driver will set the linked lists. 2 LLIs
* are needed for each DMA transfer configuration call.
*/
qm_dma_linked_list_item_t
lli_buf[MULTIBLOCK_NUM_BUFFERS * MULTIBLOCK_NUM_LLI_PER_BUFFER];
/* Clear RX buffer. */
for (unsigned int i = 0; i < RX_BUFF_SIZE; i++) {
rx_data[0][i] = '.';
}
/*
* Linked list multiblock transfer with 4 blocks, using 2 calls to the
* DMA transfer configuration function.
*
* tx_data:
* <------+ TX Buffer 2 +------><-------+ TX Buffer 1 +------>
* +---------------------------------------------------------+
* | Block A | Block B | Block C | Block D |
* +---------------------------------------------------------+
*
* RX Buffer:
* +--------------------------+ +------------------------------+
* | Block C | Block D |.....| Block A | Block B |
* +--------------------------+ +------------------------------+
*/
/* Add LLIs for second half of tx_data (blocks C and D). */
multi_transfer.block_size =
strlen(tx_data_multiblock) /
(MULTIBLOCK_NUM_BUFFERS * MULTIBLOCK_NUM_LLI_PER_BUFFER);
multi_transfer.num_blocks = MULTIBLOCK_NUM_LLI_PER_BUFFER;
multi_transfer.source_address =
(uint32_t *)&tx_data_multiblock[strlen(tx_data_multiblock) /
MULTIBLOCK_NUM_BUFFERS];
multi_transfer.destination_address = (uint32_t *)&rx_data[0][0];
multi_transfer.linked_list_first = &lli_buf[0];
return_code = qm_dma_multi_transfer_set_config(
p_chan_desc->controller_id, p_chan_desc->channel_id,
&multi_transfer);
if (return_code) {
QM_PRINTF("ERROR: qm_dma_mem_to_mem_transfer\n");
}
/* Add LLIs for first half of tx_data (blocks A and B). */
multi_transfer.source_address = (uint32_t *)&tx_data_multiblock[0];
multi_transfer.destination_address =
(uint32_t *)&rx_data[0][RX_BUFF_SIZE - (strlen(tx_data_multiblock) /
MULTIBLOCK_NUM_BUFFERS)];
multi_transfer.linked_list_first =
&lli_buf[MULTIBLOCK_NUM_LLI_PER_BUFFER];
return_code = qm_dma_multi_transfer_set_config(
p_chan_desc->controller_id, p_chan_desc->channel_id,
&multi_transfer);
if (return_code) {
QM_PRINTF("ERROR: qm_dma_mem_to_mem_transfer\n");
}
irq_fired = false;
return_code = qm_dma_transfer_start(p_chan_desc->controller_id,
p_chan_desc->channel_id);
if (return_code) {
QM_PRINTF("ERROR: qm_dma_transfer_start\n");
}
/* Wait for completion callback. */
while (!irq_fired)
;
}
/* QMSI SPI app example */
int main(void)
{
/* Variables */
qm_spi_config_t cfg;
qm_spi_transfer_t polled_xfer_desc;
qm_spi_async_transfer_t irq_xfer_desc;
unsigned int i;
for (i = 0; i < BUFFERSIZE; i++) {
tx_buff[i] = i;
}
/* Mux out SPI tx/rx pins and enable input for rx. */
#if (QUARK_SE)
qm_pmux_select(QM_PIN_ID_55, QM_PMUX_FN_1); /* SPI0_M SCK */
qm_pmux_select(QM_PIN_ID_56, QM_PMUX_FN_1); /* SPI0_M MISO */
qm_pmux_select(QM_PIN_ID_57, QM_PMUX_FN_1); /* SPI0_M MOSI */
qm_pmux_select(QM_PIN_ID_58, QM_PMUX_FN_1); /* SPI0_M SS0 */
qm_pmux_select(QM_PIN_ID_59, QM_PMUX_FN_1); /* SPI0_M SS1 */
qm_pmux_select(QM_PIN_ID_60, QM_PMUX_FN_1); /* SPI0_M SS2 */
qm_pmux_select(QM_PIN_ID_61, QM_PMUX_FN_1); /* SPI0_M SS3 */
qm_pmux_input_en(QM_PIN_ID_56, true);
#elif(QUARK_D2000)
qm_pmux_select(QM_PIN_ID_0, QM_PMUX_FN_2); /* SS0 */
qm_pmux_select(QM_PIN_ID_1, QM_PMUX_FN_2); /* SS1 */
qm_pmux_select(QM_PIN_ID_2, QM_PMUX_FN_2); /* SS2 */
qm_pmux_select(QM_PIN_ID_3, QM_PMUX_FN_2); /* SS3 */
qm_pmux_select(QM_PIN_ID_16, QM_PMUX_FN_2); /* SCK */
qm_pmux_select(QM_PIN_ID_17, QM_PMUX_FN_2); /* TXD */
qm_pmux_select(QM_PIN_ID_18, QM_PMUX_FN_2); /* RXD */
qm_pmux_input_en(QM_PIN_ID_18, true); /* RXD input */
#else
#error("Unsupported / unspecified processor detected.")
#endif
/* Enable the clock to the controller. */
clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_SPI_M0_REGISTER);
/* Initialise SPI configuration */
cfg.frame_size = QM_SPI_FRAME_SIZE_8_BIT;
cfg.transfer_mode = QM_SPI_TMOD_TX_RX;
cfg.bus_mode = QM_SPI_BMODE_0;
cfg.clk_divider = SPI_CLOCK_DIV;
qm_spi_set_config(QM_SPI_MST_0, &cfg);
/* Set up loopback mode by RMW directly to the ctrlr0 register. */
QM_SPI[QM_SPI_MST_0]->ctrlr0 |= BIT(11);
qm_spi_slave_select(QM_SPI_MST_0, QM_SPI_SS_0);
QM_PRINTF("\nStatus = 0x%08x", qm_spi_get_status(QM_SPI_MST_0));
/* Set up the sync transfer struct and call a polled transfer. */
polled_xfer_desc.tx = tx_buff;
polled_xfer_desc.rx = rx_buff;
polled_xfer_desc.tx_len = BUFFERSIZE;
polled_xfer_desc.rx_len = BUFFERSIZE;
qm_spi_transfer(QM_SPI_MST_0, &polled_xfer_desc);
/* Compare RX and TX buffers */
/* Also reset the buffers for the IRQ example */
for (i = 0; i < BUFFERSIZE; i++) {
QM_CHECK(tx_buff[i] == rx_buff[i], QM_RC_EINVAL);
tx_buff[i] = i;
rx_buff[i] = 0;
}
/* Set up the async transfer struct. */
irq_xfer_desc.tx = tx_buff;
irq_xfer_desc.rx = rx_buff;
irq_xfer_desc.tx_len = BUFFERSIZE;
irq_xfer_desc.rx_len = BUFFERSIZE;
irq_xfer_desc.id = SPI_EXAMPLE_IRQ_ID;
irq_xfer_desc.rx_callback = spi_rx_example_cb;
irq_xfer_desc.tx_callback = spi_tx_example_cb;
irq_xfer_desc.err_callback = spi_err_example_cb;
/* Register driver IRQ. */
qm_irq_request(QM_IRQ_SPI_MASTER_0, qm_spi_master_0_isr);
/* Start the async (irq-based) transfer. */
qm_spi_irq_transfer(QM_SPI_MST_0, &irq_xfer_desc);
while (1)
;
return 0;
}
void aon_gpio_example_callback(uint32_t status)
{
QM_PRINTF("AON GPIO callback - status register = 0x%u\n", status);
}