unsigned int _read(struct Process *proc) {
struct Process *wakeproc;
size_t buf_size = (size_t)proc->stackptr[2+0];
size_t msg_size;
char *buf = (char*)proc->stackptr[2+1];
msg_size = pipe_pop_message(&(proc->msgs),buf_size,buf);
if(msg_size == 0) {
/* not enough data to complete the read */
proc->blocked = (unsigned int)&_read;
} else {
proc->stackptr[2+0] = msg_size; /* return number of bytes in the message */
/* unblock writers */
if(QUEUE_LEN(proc->writers) > 0) {
QUEUE_POP(proc->writers,wakeproc);
wakeproc->blocked = 0;
_write(wakeproc,proc);
}
}
return proc->blocked;
}
void ccci_modem_restore_reg(struct ccci_modem *md)
{
struct md_cd_ctrl *md_ctrl = (struct md_cd_ctrl *)md->private_data;
int i;
unsigned long flags;
if(md->md_state == GATED||md->md_state == RESET||md->md_state == INVALID){
CCCI_INF_MSG(md->index, TAG, "Resume no need reset cldma for md_state=%d\n",md->md_state);
return;
}
cldma_write32(md_ctrl->ap_ccif_base, APCCIF_CON, 0x01); // arbitration
if(cldma_read32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_TQSAR(0)))
{
CCCI_INF_MSG(md->index, TAG, "Resume cldma pdn register: No need ...\n");
}
else
{
CCCI_INF_MSG(md->index, TAG, "Resume cldma pdn register ...11\n");
spin_lock_irqsave(&md_ctrl->cldma_timeout_lock, flags);
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_HPQR, 0x00);
// set checksum
switch (CHECKSUM_SIZE) {
case 0:
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_UL_CHECKSUM_CHANNEL_ENABLE, 0);
break;
case 12:
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_UL_CHECKSUM_CHANNEL_ENABLE, CLDMA_BM_ALL_QUEUE);
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_UL_CFG, cldma_read32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_UL_CFG)&~0x10);
break;
case 16:
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_UL_CHECKSUM_CHANNEL_ENABLE, CLDMA_BM_ALL_QUEUE);
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_UL_CFG, cldma_read32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_UL_CFG)|0x10);
break;
}
// set start address
for(i=0; i<QUEUE_LEN(md_ctrl->txq); i++) {
if(cldma_read32(md_ctrl->cldma_ap_ao_base, CLDMA_AP_TQCPBAK(md_ctrl->txq[i].index)) == 0){
CCCI_INF_MSG(md->index, TAG, "Resume CH(%d) current bak:== 0\n", i);
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_TQSAR(md_ctrl->txq[i].index), md_ctrl->txq[i].tr_done->gpd_addr);
cldma_write32(md_ctrl->cldma_ap_ao_base, CLDMA_AP_TQSABAK(md_ctrl->txq[i].index), md_ctrl->txq[i].tr_done->gpd_addr);
}
else{
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_TQSAR(md_ctrl->txq[i].index), cldma_read32(md_ctrl->cldma_ap_ao_base, CLDMA_AP_TQCPBAK(md_ctrl->txq[i].index)));
cldma_write32(md_ctrl->cldma_ap_ao_base, CLDMA_AP_TQSABAK(md_ctrl->txq[i].index), cldma_read32(md_ctrl->cldma_ap_ao_base, CLDMA_AP_TQCPBAK(md_ctrl->txq[i].index)));
}
}
wmb();
// start all Tx and Rx queues
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_UL_START_CMD, CLDMA_BM_ALL_QUEUE);
cldma_read32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_UL_START_CMD); // dummy read
md_ctrl->txq_active |= CLDMA_BM_ALL_QUEUE;
//cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_SO_START_CMD, CLDMA_BM_ALL_QUEUE);
//cldma_read32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_SO_START_CMD); // dummy read
//md_ctrl->rxq_active |= CLDMA_BM_ALL_QUEUE;
// enable L2 DONE and ERROR interrupts
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_L2TIMCR0, CLDMA_BM_INT_DONE|CLDMA_BM_INT_ERROR);
// enable all L3 interrupts
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_L3TIMCR0, CLDMA_BM_INT_ALL);
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_L3TIMCR1, CLDMA_BM_INT_ALL);
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_L3RIMCR0, CLDMA_BM_INT_ALL);
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_L3RIMCR1, CLDMA_BM_INT_ALL);
spin_unlock_irqrestore(&md_ctrl->cldma_timeout_lock, flags);
CCCI_INF_MSG(md->index, TAG, "Resume cldma pdn register done\n");
}
}
