static void early_ich7_init(void)
{
uint8_t reg8;
uint32_t reg32;
// program secondary mlt XXX byte?
pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
// reset rtc power status
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
reg8 &= ~(1 << 2);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
// usb transient disconnect
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
reg8 |= (3 << 0);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
reg32 |= (1 << 29) | (1 << 17);
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
reg32 |= (1 << 31) | (1 << 27);
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
RCBA32(0x0088) = 0x0011d000;
RCBA16(0x01fc) = 0x060f;
RCBA32(0x01f4) = 0x86000040;
RCBA32(0x0214) = 0x10030549;
RCBA32(0x0218) = 0x00020504;
RCBA8(0x0220) = 0xc5;
reg32 = RCBA32(0x3410);
reg32 |= (1 << 6);
RCBA32(0x3410) = reg32;
reg32 = RCBA32(0x3430);
reg32 &= ~(3 << 0);
reg32 |= (1 << 0);
RCBA32(0x3430) = reg32;
RCBA32(0x3418) |= (1 << 0);
RCBA16(0x0200) = 0x2008;
RCBA8(0x2027) = 0x0d;
RCBA16(0x3e08) |= (1 << 7);
RCBA16(0x3e48) |= (1 << 7);
RCBA32(0x3e0e) |= (1 << 7);
RCBA32(0x3e4e) |= (1 << 7);
// next step only on ich7m b0 and later:
reg32 = RCBA32(0x2034);
reg32 &= ~(0x0f << 16);
reg32 |= (5 << 16);
RCBA32(0x2034) = reg32;
}
static void rcba_config(void)
{
/* Set up virtual channel 0 */
//RCBA32(0x0014) = 0x80000001;
//RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */
RCBA32(0x3100) = 0x00042210;
/* Device 1d interrupt pin register */
RCBA32(0x310c) = 0x00214321;
/* dev irq route register */
RCBA16(0x3140) = 0x0132;
RCBA16(0x3142) = 0x0146;
RCBA16(0x3144) = 0x0237;
RCBA16(0x3146) = 0x3201;
RCBA16(0x3148) = 0x0146;
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
/* Disable unused devices */
//RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
// RCBA32(0x3418) |= (1 << 0); // Required.
// FIXME look me up!
RCBA32(0x3418) = 0x003204e1;
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
}
static void rcba_config(void)
{
/* Set up virtual channel 0 */
RCBA32(0x0014) = 0x80000001;
RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */
RCBA32(0x3100) = 0x00042210;
RCBA32(0x3108) = 0x10004321;
RCBA32(0x3104) = 0x00002100;
/* PCIe Interrupts */
RCBA32(0x310c) = 0x00214321;
/* HD Audio Interrupt */
RCBA32(0x3110) = 0x00000001;
/* dev irq route register */
RCBA16(0x3140) = 0x0132;
RCBA16(0x3142) = 0x0146;
RCBA16(0x3144) = 0x0237;
RCBA16(0x3146) = 0x3201;
RCBA16(0x3148) = 0x0146;
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
RCBA32(0x3418) = 0x003000e2;
RCBA32(0x3418) |= 1;
}
static void i82801ix_enable_apic(struct device *dev)
{
u32 reg32;
volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
/* Enable IOAPIC. Keep APIC Range Select at zero. */
RCBA8(0x31ff) = 0x03;
/* We have to read 0x31ff back if bit0 changed. */
RCBA8(0x31ff);
/* Lock maximum redirection entries (MRE), R/WO register. */
*ioapic_index = 0x01;
reg32 = *ioapic_data;
*ioapic_index = 0x01;
*ioapic_data = reg32;
setup_ioapic(IO_APIC_ADDR, 2); /* ICH7 code uses id 2. */
}
static void set_spi_speed(void)
{
u32 fdod;
u8 ssfc;
/* Observe SPI Descriptor Component Section 0 */
RCBA32(0x38b0) = 0x1000;
/* Extract the Write/Erase SPI Frequency from descriptor */
fdod = RCBA32(0x38b4);
fdod >>= 24;
fdod &= 7;
/* Set Software Sequence frequency to match */
ssfc = RCBA8(0x3893);
ssfc &= ~7;
ssfc |= fdod;
RCBA8(0x3893) = ssfc;
}
static void mb_lpc_setup(void)
{
u32 reg32;
/* Set the value for GPIO base address register and enable GPIO. */
pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&mainboard_gpio_map);
/* Set GPIOs on superio, enable UART */
if (IS_ENABLED(CONFIG_SUPERIO_NUVOTON_NCT6776)) {
nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2);
pnp_set_logical_device(SERIAL_DEV_R2);
pnp_write_config(SERIAL_DEV_R2, 0x1c, 0x80);
pnp_write_config(SERIAL_DEV_R2, 0x27, 0x80);
pnp_write_config(SERIAL_DEV_R2, 0x2a, 0x60);
nuvoton_pnp_exit_conf_state(SERIAL_DEV_R2);
nuvoton_enable_serial(SERIAL_DEV_R2, CONFIG_TTYS0_BASE);
} else {
winbond_enable_serial(SERIAL_DEV_R1, CONFIG_TTYS0_BASE);
}
/* IRQ routing */
RCBA16(D31IR) = 0x0132;
RCBA16(D29IR) = 0x0237;
/* Enable IOAPIC */
RCBA8(OIC) = 0x03;
RCBA8(OIC);
reg32 = RCBA32(GCS);
reg32 |= (1 << 5);
RCBA32(GCS) = reg32;
RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
| FD_ACAUD | 1;
RCBA32(CG) = 0x00000001;
}
static void rcba_config(void)
{
/* Set up virtual channel 0 */
//RCBA32(0x0014) = 0x80000001;
//RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */
RCBA32(0x3100) = 0x00042220;
/* Device 1d interrupt pin register */
RCBA32(0x310c) = 0x00214321;
/* dev irq route register */
RCBA16(0x3140) = 0x0232;
RCBA16(0x3142) = 0x3246;
RCBA16(0x3144) = 0x0237;
RCBA16(0x3146) = 0x3201;
RCBA16(0x3148) = 0x3216;
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 |
FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA;
RCBA32(0x3418) |= (1 << 0); // Required.
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
/* This should probably go into the ACPI OS Init trap */
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
RCBA32(0x1e84) = 0x00020001;
RCBA32(0x1e80) = 0x0000fe01;
/* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
RCBA32(0x1e9c) = 0x000200f0;
RCBA32(0x1e98) = 0x000c0801;
}
static void rcba_config(void)
{
/* V0CTL Virtual Channel 0 Resource Control */
RCBA32(0x0014) = 0x80000001;
/* V1CAP Virtual Channel 1 Resource Capability */
RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */
RCBA32(0x3100) = 0x00042210;
RCBA32(0x3108) = 0x10004321;
/* PCIe Interrupts */
RCBA32(0x310c) = 0x00214321;
/* HD Audio Interrupt */
RCBA32(0x3110) = 0x00000001;
/* dev irq route register */
RCBA16(0x3140) = 0x0232;
RCBA16(0x3142) = 0x3246;
RCBA16(0x3144) = 0x0235;
RCBA16(0x3146) = 0x3201;
RCBA16(0x3148) = 0x3216;
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
RCBA32(0x3418) |= (1 << 0); // Required.
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
// RCBA32(0x1e84) = 0x00020001;
// RCBA32(0x1e80) = 0x0000fe01;
/* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
RCBA32(0x1e9c) = 0x000200f0;
RCBA32(0x1e98) = 0x000c0801;
}
static void rcba_config(void)
{
/* Set up virtual channel 0 */
RCBA32(0x0014) = 0x80000001;
RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */
RCBA32(0x3100) = 0x00001230;
RCBA32(0x3108) = 0x40004321;
/* PCIe Interrupts */
RCBA32(0x310c) = 0x00004321;
/* HD Audio Interrupt */
RCBA32(0x3110) = 0x00000002;
/* dev irq route register */
RCBA16(0x3140) = 0x1007;
RCBA16(0x3142) = 0x0076;
RCBA16(0x3144) = 0x3210;
RCBA16(0x3146) = 0x7654;
RCBA16(0x3148) = 0x0010;
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
/* Disable unused devices */
RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
RCBA32(0x3418) |= (1 << 0); // Required.
/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
RCBA32(0x1e84) = 0x00020001;
RCBA32(0x1e80) = 0x0000fe01;
/* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
RCBA32(0x1e9c) = 0x000200f0;
RCBA32(0x1e98) = 0x000c0801;
}
static void rcba_config(void)
{
/* Set up virtual channel 0 */
//RCBA32(0x0014) = 0x80000001;
//RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */
RCBA32(0x3100) = 0x00042210;
/* Device 1d interrupt pin register */
RCBA32(0x310c) = 0x00214321;
/* dev irq route register */
RCBA16(0x3140) = 0x0132;
RCBA16(0x3142) = 0x0146;
RCBA16(0x3144) = 0x0237;
RCBA16(0x3146) = 0x3201;
RCBA16(0x3148) = 0x0146;
/* Enable IOAPIC */
RCBA8(0x31ff) = 0x03;
/* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001;
}
static void init_dmi(void)
{
u32 reg32;
u16 reg16;
/* Assume IGD present */
/* Clear error status */
DMIBAR32(0x1c4) = 0xffffffff;
DMIBAR32(0x1d0) = 0xffffffff;
/* VC0: TC0 only */
DMIBAR8(DMIVC0RCTL) = 1;
DMIBAR8(0x4) = 1;
/* VC1: ID1, TC7 */
reg32 = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24);
reg32 = (reg32 & ~0xff) | 1 << 7;
/* VC1: enable */
reg32 |= 1 << 31;
reg32 = (reg32 & ~(0x7 << 17)) | (0x4 << 17);
DMIBAR32(DMIVC1RCTL) = reg32;
/* Set up VCs in southbridge RCBA */
RCBA8(0x3022) &= ~1;
reg32 = (0x5 << 28) | (1 << 6); /* PCIe x4 */
RCBA32(0x2020) = (RCBA32(0x2020) & ~((0xf << 28) | (0x7 << 6))) | reg32;
/* Assign VC1 id 1 */
RCBA32(0x20) = (RCBA32(0x20) & ~(0x7 << 24)) | (1 << 24);
/* Map TC7 to VC1 */
RCBA8(0x20) &= 1;
RCBA8(0x20) |= 1 << 7;
/* Map TC0 to VC0 */
RCBA8(0x14) &= 1;
/* Init DMI VC1 port arbitration table */
RCBA32(0x20) &= 0xfff1ffff;
RCBA32(0x20) |= 1 << 19;
RCBA32(0x30) = 0x0000000f;
RCBA32(0x34) = 0x000f0000;
RCBA32(0x38) = 0;
RCBA32(0x3c) = 0x000000f0;
RCBA32(0x40) = 0x0f000000;
RCBA32(0x44) = 0;
RCBA32(0x48) = 0x0000f000;
RCBA32(0x4c) = 0;
RCBA32(0x50) = 0x0000000f;
RCBA32(0x54) = 0x000f0000;
RCBA32(0x58) = 0;
RCBA32(0x5c) = 0x000000f0;
RCBA32(0x60) = 0x0f000000;
RCBA32(0x64) = 0;
RCBA32(0x68) = 0x0000f000;
RCBA32(0x6c) = 0;
RCBA32(0x20) |= 1 << 16;
/* Enable VC1 */
RCBA32(0x20) |= 1 << 31;
/* Wait for VC1 */
while ((RCBA8(0x26) & (1 << 1)) != 0);
/* Wait for table load */
while ((RCBA8(0x26) & (1 << 0)) != 0);
/* ASPM on DMI link */
RCBA16(0x1a8) &= ~0x3;
reg16 = RCBA16(0x1a8);
RCBA32(0x2010) = (RCBA32(0x2010) & ~(0x3 << 10)) | (1 << 10);
reg32 = RCBA32(0x2010);
/* Set up VC1 max time */
RCBA32(0x1c) = (RCBA32(0x1c) & ~0x7f0000) | 0x120000;
while ((DMIBAR32(0x26) & (1 << 1)) != 0);
printk(BIOS_DEBUG, "Done DMI setup\n");
/* ASPM on DMI */
DMIBAR32(0x200) &= ~(0x3 << 26);
DMIBAR16(0x210) = (DMIBAR16(0x210) & ~(0xff7)) | 0x101;
DMIBAR32(0x88) &= ~0x3;
DMIBAR32(0x88) |= 0x3;
reg16 = DMIBAR16(0x88);
}
