/**
* Read data from HDMI RX CTRL
* @param[in] addr register address
* @return data read value
*/
uint32_t hdmirx_rd_dwc(uint16_t addr)
{
unsigned long dev_offset = 0x10; // TOP ADDR_PORT: 0xc800e000; DWC ADDR_PORT: 0xc800e010
unsigned long data;
WRITE_APB_REG((HDMIRX_ADDR_PORT | dev_offset), addr);
data = READ_APB_REG((HDMIRX_DATA_PORT | dev_offset));
return (data);
} /* hdmirx_rd_DWC */
unsigned long hdmirx_rd_top (unsigned long addr)
{
unsigned long dev_offset = 0; // TOP ADDR_PORT: 0xc800e000; DWC ADDR_PORT: 0xc800e010
unsigned long data;
WRITE_APB_REG((HDMIRX_ADDR_PORT | dev_offset), addr);
data = READ_APB_REG((HDMIRX_DATA_PORT | dev_offset));
return (data);
} /* hdmirx_rd_TOP */
static unsigned int hdmi_rd_reg(unsigned long addr)
{
unsigned long data;
WRITE_APB_REG(HDMI_ADDR_PORT, addr);
WRITE_APB_REG(HDMI_ADDR_PORT, addr);
data = READ_APB_REG(HDMI_DATA_PORT);
return (data);
}
/**
* Read data from HDMI RX CTRL
* @param[in] addr register address
* @return data read value
*/
uint32_t hdmirx_rd_dwc(uint16_t addr)
{
ulong flags;
unsigned long dev_offset = 0x10; // TOP ADDR_PORT: 0xc800e000; DWC ADDR_PORT: 0xc800e010
unsigned long data;
spin_lock_irqsave(®_rw_lock, flags);
WRITE_APB_REG((HDMIRX_ADDR_PORT | dev_offset), addr);
data = READ_APB_REG((HDMIRX_DATA_PORT | dev_offset));
spin_unlock_irqrestore(®_rw_lock, flags);
return (data);
} /* hdmirx_rd_DWC */
static void aml_audio_adc_power_gating(int flag)//flag=1 : on; flag=0 : off
{
u32 value;
value = READ_APB_REG(APB_ADAC_POWER_CTRL_REG2);
if(flag){
value |= 3;
}
else{
value &= ~3;
}
WRITE_APB_REG(APB_ADAC_POWER_CTRL_REG2, value);
}
void mute_headphone(void* codec, int flag)
{
int reg_val;
#ifdef _AML_M3_HW_DEBUG_
printk("***Entered %s:%s\n", __FILE__,__func__);
#endif
reg_val = READ_APB_REG(APB_BASE+(0x18<<2));
if(flag){
reg_val |= 0xc0;
WRITE_APB_REG((APB_BASE+(0x18<<2)), reg_val); // mute headphone
}else{
reg_val &= ~0xc0;
WRITE_APB_REG((APB_BASE+(0x18<<2)), reg_val); // unmute headphone
}
}
static void read_reg(char *para)
{
char count=1;
vout_reg_t reg;
memcpy(®.addr,parse_para(para+1,&count),sizeof(unsigned int));
if (((*para) == 'm') || ((*para) == 'M'))
{
amlog_level(LOG_LEVEL_HIGH,"[0x%x] : 0x%x\r\n", CBUS_REG_ADDR(reg.addr), READ_MPEG_REG(reg.addr));
}else if (((*para) == 'p') || ((*para) == 'P')) {
if (APB_REG_ADDR_VALID(reg.addr))
amlog_level(LOG_LEVEL_HIGH,"[0x%x] : 0x%x\r\n", APB_REG_ADDR(reg.addr), READ_APB_REG(reg.addr));
}else if (((*para) == 'h') || ((*para) == 'H')) {
amlog_level(LOG_LEVEL_HIGH,"[0x%x] : 0x%x\r\n", AHB_REG_ADDR(reg.addr), READ_AHB_REG(reg.addr));
}
}
static void aml_audio_clock_gating_disable(void)
{
struct snd_soc_codec* codec;
//printk("***Entered %s:%s\n", __FILE__,__func__);
//WRITE_CBUS_REG(HHI_GCLK_MPEG0, READ_CBUS_REG(HHI_GCLK_MPEG0)&~(1<<18));
WRITE_CBUS_REG(HHI_GCLK_MPEG1, READ_CBUS_REG(HHI_GCLK_MPEG1)&~(1<<2)
//&~(0xFF<<6)
);
//WRITE_CBUS_REG(HHI_GCLK_MPEG2, READ_CBUS_REG(HHI_GCLK_MPEG2)&~(1<<10));
//WRITE_CBUS_REG(HHI_GCLK_OTHER, READ_CBUS_REG(HHI_GCLK_OTHER)&~(1<<10)
//&~(1<<18)
//&~(0x7<<14));
mute_spk(codec,1);
WRITE_APB_REG(APB_ADAC_POWER_CTRL_REG2, READ_APB_REG(APB_ADAC_POWER_CTRL_REG2)&(~(1<<7)));
adac_latch();
}
static void aml_audio_clock_gating_enable(void)
{
struct snd_soc_codec* codec;
printk("***Entered %s:%s\n", __FILE__,__func__);
//WRITE_CBUS_REG(HHI_GCLK_MPEG0, READ_CBUS_REG(HHI_GCLK_MPEG0)|(1<<18));
WRITE_CBUS_REG(HHI_GCLK_MPEG1, READ_CBUS_REG(HHI_GCLK_MPEG1)|(1<<2)
//|(0xFF<<6)
);
//WRITE_CBUS_REG(HHI_GCLK_MPEG2, READ_CBUS_REG(HHI_GCLK_MPEG2)|(1<<10));
//WRITE_CBUS_REG(HHI_GCLK_OTHER, READ_CBUS_REG(HHI_GCLK_OTHER)|(1<<10)
//|(1<<18)
//|(0x7<<14));
WRITE_APB_REG(APB_ADAC_POWER_CTRL_REG2, READ_APB_REG(APB_ADAC_POWER_CTRL_REG2)|(1<<7));
if(aml_m3_is_hp_pluged()){
mute_spk(codec,1);
}
else
mute_spk(codec,0);
adac_latch();
}
unsigned long adac_rd_reg (unsigned long addr)
{
unsigned long data;
data = READ_APB_REG(APB_BASE+(addr<<2));
return (data);
} /* adac_rd_reg */
void am_set_regmap(struct am_regs_s *p)
{
unsigned short i;
unsigned int temp = 0;
for (i=0; i<p->length; i++) {
switch (p->am_reg[i].type)
{
case REG_TYPE_PHY:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: phy..............\n", __func__);
#endif
break;
case REG_TYPE_CBUS:
if (p->am_reg[i].mask == 0xffffffff)
WRITE_CBUS_REG(p->am_reg[i].addr, p->am_reg[i].val);
else
WRITE_CBUS_REG(p->am_reg[i].addr, (READ_CBUS_REG(p->am_reg[i].addr) & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: cbus: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_APB:
if (p->am_reg[i].mask == 0xffffffff)
WRITE_APB_REG(p->am_reg[i].addr, p->am_reg[i].val);
else
WRITE_APB_REG(p->am_reg[i].addr, (READ_APB_REG(p->am_reg[i].addr) & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: apb: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_MPEG:
if (p->am_reg[i].mask == 0xffffffff)
WRITE_MPEG_REG(p->am_reg[i].addr, p->am_reg[i].val);
else
WRITE_MPEG_REG(p->am_reg[i].addr, (READ_MPEG_REG(p->am_reg[i].addr) & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: mpeg: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_AXI:
if (p->am_reg[i].mask == 0xffffffff)
WRITE_AXI_REG(p->am_reg[i].addr, p->am_reg[i].val);
else
WRITE_AXI_REG(p->am_reg[i].addr, (READ_AXI_REG(p->am_reg[i].addr) & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: axi: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_AHB:
if (p->am_reg[i].mask == 0xffffffff)
WRITE_AHB_REG(p->am_reg[i].addr, p->am_reg[i].val);
else
WRITE_AHB_REG(p->am_reg[i].addr, (READ_AHB_REG(p->am_reg[i].addr) & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: ahb: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_INDEX_VPPCHROMA:
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->am_reg[i].addr);
if (p->am_reg[i].mask == 0xffffffff)
{
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->am_reg[i].val);
}
else
{
temp = READ_CBUS_REG(VPP_CHROMA_DATA_PORT);
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->am_reg[i].addr);
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, (temp & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
}
#ifdef PQ_DEBUG_EN
pr_info("%s: chroma: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_INDEX_GAMMA:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: REG_TYPE_INDEX_GAMMA..............\n", __func__);
#endif
break;
case VALUE_TYPE_CONTRAST_BRIGHTNESS:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: VALUE_TYPE_CONTRAST_BRIGHTNESS..............\n", __func__);
#endif
break;
case REG_TYPE_INDEX_VPP_COEF:
if (((p->am_reg[i].addr&0xf) == 0)||((p->am_reg[i].addr&0xf) == 0x8))
{
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->am_reg[i].addr);
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->am_reg[i].val);
}
else
{
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->am_reg[i].val);
}
#ifdef PQ_DEBUG_EN
pr_info("%s: coef: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
default:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type error!!!bustype = 0x%x................\n", __func__, p->am_reg[i].type);
#endif
break;
}
}
return;
}
static void write_reg(char *para)
{
char count=2;
vout_reg_t reg;
memcpy(®, parse_para(para+1,&count), sizeof(vout_reg_t));
if (((*para) == 'm') || ((*para) == 'M')){
WRITE_MPEG_REG(reg.addr,reg.value);
amlog_level(LOG_LEVEL_HIGH,"[0x%x] = 0x%x 0x%x\r\n", CBUS_REG_ADDR(reg.addr), reg.value, READ_MPEG_REG(reg.addr));
}
else if (((*para) == 'p') || ((*para) == 'P')) {
if (APB_REG_ADDR_VALID(reg.addr)){
WRITE_APB_REG(reg.addr,reg.value);
amlog_level(LOG_LEVEL_HIGH,"[0x%x] = 0x%x 0x%x\r\n", APB_REG_ADDR(reg.addr), reg.value, READ_APB_REG(reg.addr));
}
}
else if (((*para) == 'h') || ((*para) == 'H')) {
WRITE_AHB_REG(reg.addr,reg.value);
amlog_level(LOG_LEVEL_HIGH,"[0x%x] = 0x%x 0x%x\r\n", AHB_REG_ADDR(reg.addr), reg.value, READ_AHB_REG(reg.addr));
}
}
/*
* rc 0x12345678
* rw 0x12345678 1234
* adress must be hexadecimal and prefix with ox.
*/
ssize_t vdin_dbg_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
char strcmd[16];
char straddr[10];
char strval[32];
int i = 0;
int j = 0;
unsigned long addr;
unsigned int value=0;
unsigned int retval;
/* get parameter command string */
j = 0;
while( (i < count) && (buf[i]) && (buf[i] != ',') && (buf[i] != ' ') && (buf[i] != 10)){
strcmd[j] = buf[i];
i++;
j++;
}
strcmd[j] = '\0';
/* ignore */
while( (i < count) && (buf[i]) && ((buf[i] ==',') || (buf[i] == ' ') || (buf[i] == 10))){
i++;
}
/* check address */
if (strncmp(&buf[i], "0x", 2) != 0){
pr_info("invalid parameter address\n");
tvin_dbg_usage();
return 32;
}
/* get parameter address string */
j = 0;
while( (i < count) && (buf[i]) && (buf[i] != ',') && (buf[i] != ' ' && (buf[i] != 10))){
straddr[j] = buf[i];
i++;
j++;
}
straddr[j] = 0;
addr = simple_strtoul(straddr, NULL, 16); //hex data
/* rc read cbus */
if (strncmp(strcmd, "rc", 2) == 0){
retval = READ_CBUS_REG(addr);
pr_info("%s: 0x%x --> 0x%x\n", strcmd, addr, retval);
return 32;
}
/* rp read apb */
else if (strncmp(strcmd, "rp", 2) == 0){
retval = READ_APB_REG(addr);
pr_info("%s: 0x%x --> 0x%x\n", strcmd, addr, retval);
return 32;
}
/* wc write cbus */
else if (strncmp(strcmd, "wc", 2) == 0){
/* get parameter value string*/
/* ignore */
while( (i < count) && (buf[i]) && ((buf[i] ==',') || (buf[i] == ' ') || (buf[i] == 10))){
i++;
}
if (!buf[i]){
pr_info("no parameter value\n");
tvin_dbg_usage();
return 32;
}
j = 0;
while( (i < count) && (buf[i]) && (buf[i] != ',') && (buf[i] != ' ')&& (buf[i] != 10)){
strval[j] = buf[i];
i++;
j++;
}
strval[j] = '\0';
value = simple_strtol(strval, NULL, 16); //hex data
WRITE_CBUS_REG(addr, value);
pr_info("%s: 0x%x <-- 0x%x\n", strcmd, addr, value);
return 32;
}
/* wp write apb */
else if (strncmp(strcmd, "wp", 2) == 0){
/* get parameter value string*/
/* ignore */
while( (i < count) && (buf[i]) && ((buf[i] ==',') || (buf[i] == ' ') || (buf[i] == 10))){
i++;
}
if (!buf[i]){
pr_info("no parameter value\n");
tvin_dbg_usage();
return 32;
}
j = 0;
while( (i < count) && (buf[i]) && (buf[i] != ',') && (buf[i] != ' ')&& (buf[i] != 10)){
strval[j] = buf[i];
i++;
j++;
}
strval[j] = '\0';
value = simple_strtol(strval, NULL, 16); //hex data
WRITE_APB_REG(addr, value);
pr_info("%s: 0x%x <-- 0x%x\n", strcmd, addr, value);
return 32;
}
else{
pr_info("invalid parameter\n");
tvin_dbg_usage();
return 32;
}
return 32;
}
static unsigned int aml_m1_read(struct snd_soc_codec *codec,
unsigned int reg)
{
return READ_APB_REG(APB_BASE+(reg<<2));
}
static ssize_t store_dbg(struct device * dev, struct device_attribute *attr, const char * buf, size_t count)
{
char tmpbuf[128];
int i=0;
unsigned int adr;
unsigned int value=0;
while((buf[i])&&(buf[i]!=',')&&(buf[i]!=' ')){
tmpbuf[i]=buf[i];
i++;
}
tmpbuf[i]=0;
if(strncmp(tmpbuf, "config_dvin", 11)==0){
#ifdef DEBUG_DVIN
config_dvin (hs_pol_inv,
vs_pol_inv,
de_pol_inv,
field_pol_inv,
ext_field_sel,
de_mode,
data_comp_map,
mode_422to444,
dvin_clk_inv,
vs_hs_tim_ctrl,
hs_lead_vs_odd_min,
hs_lead_vs_odd_max,
active_start_pix_fe,
active_start_pix_fo,
active_start_line_fe,
active_start_line_fo,
line_width,
field_height);
#endif
}
else if(strncmp(tmpbuf, "pause", 5)==0){
hdmirx_device.task_pause = 1;
printk("Pause %s\n", __func__);
}
else if(strncmp(tmpbuf, "start", 5)==0){
hdmirx_device.task_pause = 0;
printk("Start %s\n", __func__);
}
else if(strncmp(tmpbuf, "spdif", 5)==0){
setHDMIRX_SPDIFOutput();
}
else if(strncmp(tmpbuf, "i2s", 3)==0){
setHDMIRX_I2SOutput(0x1);
}
else if(strncmp(tmpbuf, "hpd", 3)==0){
if(tmpbuf[3]=='0'){
CLEAR_HPD;
}
else if(tmpbuf[3]=='1'){
SET_HPD;
}
}
else if(tmpbuf[0]=='w'){
adr=simple_strtoul(tmpbuf+2, NULL, 16);
value=simple_strtoul(buf+i+1, NULL, 16);
if(buf[1]=='h'){
HDMIRX_WriteI2C_Byte(adr, value);
}
else if(buf[1]=='c'){
WRITE_MPEG_REG(adr, value);
pr_info("write %x to CBUS reg[%x]\n",value,adr);
}
else if(buf[1]=='p'){
WRITE_APB_REG(adr, value);
pr_info("write %x to APB reg[%x]\n",value,adr);
}
}
else if(tmpbuf[0]=='r'){
adr=simple_strtoul(tmpbuf+2, NULL, 16);
if(buf[1]=='h'){
value = HDMIRX_ReadI2C_Byte(adr);
pr_info("HDMI reg[%x]=%x\n", adr, value);
}
else if(buf[1]=='c'){
value = READ_MPEG_REG(adr);
pr_info("CBUS reg[%x]=%x\n", adr, value);
}
else if(buf[1]=='p'){
value = READ_APB_REG(adr);
pr_info("APB reg[%x]=%x\n", adr, value);
}
}
return 16;
}
void am_set_regmap(unsigned int cnt, struct am_reg_s *p)
{
unsigned short i;
unsigned int temp = 0;
for (i=0; i<cnt; i++) {
switch (p->type)
{
case REG_TYPE_PHY:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: phy..............\n", __func__);
#endif
break;
case REG_TYPE_CBUS:
if (p->mask == 0xffffffff)
WRITE_CBUS_REG(p->addr, p->val);
else
WRITE_CBUS_REG(p->addr, (READ_CBUS_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: cbus: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_APB:
if (p->mask == 0xffffffff)
WRITE_APB_REG(p->addr, p->val);
else
WRITE_APB_REG(p->addr, (READ_APB_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: apb bus: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_MPEG:
if (p->mask == 0xffffffff)
WRITE_MPEG_REG(p->addr, p->val);
else
WRITE_MPEG_REG(p->addr, (READ_MPEG_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: mpeg: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_AXI:
if (p->mask == 0xffffffff)
WRITE_AXI_REG(p->addr, p->val);
else
WRITE_AXI_REG(p->addr, (READ_AXI_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: axi: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_AHB:
if (p->mask == 0xffffffff)
WRITE_AHB_REG(p->addr, p->val);
else
WRITE_AHB_REG(p->addr, (READ_AHB_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: ahb: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_INDEX_VPPCHROMA:
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->addr);
if (p->mask == 0xffffffff)
{
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->val);
}
else
{
temp = READ_CBUS_REG(VPP_CHROMA_DATA_PORT);
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->addr);
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, (temp & (~p->mask)) | (p->val & p->mask));
}
#ifdef PQ_DEBUG_EN
pr_info("%s: vppchroma: 0x1d70:port0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_INDEX_GAMMA:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: REG_TYPE_INDEX_GAMMA..............\n", __func__);
#endif
break;
case VALUE_TYPE_CONTRAST_BRIGHTNESS:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: VALUE_TYPE_CONTRAST_BRIGHTNESS..............\n", __func__);
#endif
break;
case REG_TYPE_INDEX_VPP_COEF:
if (((p->addr&0xf) == 0)||((p->addr&0xf) == 0x8))
{
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->addr);
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->val);
}
else
{
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->val);
}
#ifdef PQ_DEBUG_EN
pr_info("%s: vppcoef: 0x1d70:port0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
default:
pr_info("%s: bus type error!!!bustype = 0x%x................\n", __func__, p->type);
break;
}
p++;
}
return;
}
void analog_switch(int flag)
{
int i;
unsigned reg_value = 0;
if (flag) {
printf("analog on\n");
SET_CBUS_REG_MASK(AM_ANALOG_TOP_REG0, 1 << 1); // set 0x206e bit[1] 1 to power on top analog
for (i = 0; i < ANALOG_COUNT; i++) {
if (analog_regs[i].enable && (analog_regs[i].set_bits || analog_regs[i].clear_bits)) {
if (analog_regs[i].enable == 1) {
WRITE_CBUS_REG(analog_regs[i].reg_addr, analog_regs[i].reg_value);
} else if (analog_regs[i].enable == 2) {
WRITE_APB_REG(analog_regs[i].reg_addr, analog_regs[i].reg_value);
} else if (analog_regs[i].enable == 3) {
WRITE_AHB_REG(analog_regs[i].reg_addr, analog_regs[i].reg_value);
}
}
}
} else {
printf("analog off\n");
for (i = 0; i < ANALOG_COUNT; i++) {
if (analog_regs[i].enable && (analog_regs[i].set_bits || analog_regs[i].clear_bits)) {
if (analog_regs[i].enable == 1) {
analog_regs[i].reg_value = READ_CBUS_REG(analog_regs[i].reg_addr);
printf("%s(0x%x):0x%x", analog_regs[i].name, CBUS_REG_ADDR(analog_regs[i].reg_addr), analog_regs[i].reg_value);
if (analog_regs[i].clear_bits) {
CLEAR_CBUS_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].clear_bits);
printf(" & ~0x%x", analog_regs[i].clear_bits);
}
if (analog_regs[i].set_bits) {
SET_CBUS_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].set_bits);
printf(" | 0x%x", analog_regs[i].set_bits);
}
reg_value = READ_CBUS_REG(analog_regs[i].reg_addr);
printf(" = 0x%x\n", reg_value);
} else if (analog_regs[i].enable == 2) {
analog_regs[i].reg_value = READ_APB_REG(analog_regs[i].reg_addr);
printf("%s(0x%x):0x%x", analog_regs[i].name, APB_REG_ADDR(analog_regs[i].reg_addr), analog_regs[i].reg_value);
if (analog_regs[i].clear_bits) {
CLEAR_APB_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].clear_bits);
printf(" & ~0x%x", analog_regs[i].clear_bits);
}
if (analog_regs[i].set_bits) {
SET_APB_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].set_bits);
printf(" | 0x%x", analog_regs[i].set_bits);
}
reg_value = READ_APB_REG(analog_regs[i].reg_addr);
printf(" = 0x%x\n", reg_value);
} else if (analog_regs[i].enable == 3) {
analog_regs[i].reg_value = READ_AHB_REG(analog_regs[i].reg_addr);
printf("%s(0x%x):0x%x", analog_regs[i].name, AHB_REG_ADDR(analog_regs[i].reg_addr), analog_regs[i].reg_value);
if (analog_regs[i].clear_bits) {
CLEAR_AHB_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].clear_bits);
printf(" & ~0x%x", analog_regs[i].clear_bits);
}
if (analog_regs[i].set_bits) {
SET_AHB_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].set_bits);
printf(" | 0x%x", analog_regs[i].set_bits);
}
reg_value = READ_AHB_REG(analog_regs[i].reg_addr);
printf(" = 0x%x\n", reg_value);
}
}
}
CLEAR_CBUS_REG_MASK(AM_ANALOG_TOP_REG0, 1 << 1); // set 0x206e bit[1] 0 to shutdown top analog
}
}
