_mali_osk_errcode_t mali_platform_power_mode_change(mali_power_mode power_mode)
{
/* turn off MALI clock gating */
unsigned long flags;
unsigned cpu_divider, mali_divider;
unsigned ddr_pll_setting, sys_pll_setting;
unsigned cpu_freq, ddr_freq;
int mali_flag;
switch (power_mode) {
case MALI_POWER_MODE_LIGHT_SLEEP:
/* turn on MALI clock gating */
CLEAR_CBUS_REG_MASK(HHI_MALI_CLK_CNTL, 1 << 8);
break;
case MALI_POWER_MODE_DEEP_SLEEP:
/* turn on MALI clock gating */
CLEAR_CBUS_REG_MASK(HHI_MALI_CLK_CNTL, 1 << 8);
break;
case MALI_POWER_MODE_ON:
/* turn off MALI clock gating */
local_irq_save(flags);
CLEAR_CBUS_REG_MASK(HHI_MALI_CLK_CNTL, 1 << 8);
sys_pll_setting = READ_MPEG_REG(HHI_SYS_PLL_CNTL);
cpu_freq = ((sys_pll_setting&0x1ff)*24)>>(sys_pll_setting>>16); // assume 24M xtal
cpu_divider = READ_MPEG_REG_BITS(HHI_SYS_CPU_CLK_CNTL, 2, 2);
if (cpu_divider == 3)
cpu_divider = 2; // now fix at /4
cpu_freq >>= cpu_divider;
ddr_pll_setting = READ_MPEG_REG(HHI_DDR_PLL_CNTL);
ddr_freq = ((ddr_pll_setting&0x1ff)*24)>>((ddr_pll_setting>>16)&3);
mali_divider = 1;
while ((mali_divider * cpu_freq < ddr_freq) || (264 * mali_divider < ddr_freq)) // assume mali max 264M
mali_divider++;
mali_flag = ((mali_divider-1) != (READ_MPEG_REG(HHI_MALI_CLK_CNTL)&0x7f));
if (mali_flag){
WRITE_CBUS_REG(HHI_MALI_CLK_CNTL,
(3 << 9) | // select ddr pll as clock source
((mali_divider-1) << 0)); // ddr clk / divider
READ_CBUS_REG(HHI_MALI_CLK_CNTL); // delay
}
SET_CBUS_REG_MASK(HHI_MALI_CLK_CNTL, 1 << 8);
local_irq_restore(flags);
if (mali_flag)
printk("(CTS_MALI_CLK) = %d/%d = %dMHz --- when mali gate on\n", ddr_freq, mali_divider, ddr_freq/mali_divider);
mali_meson_poweron();
break;
}
last_power_mode = power_mode;
MALI_SUCCESS;
}
unsigned int audio_hdmi_init_ready()
{
return READ_MPEG_REG_BITS(AIU_HDMI_CLK_DATA_CTRL, 0, 2);
}
int if_audio_out_enable()
{
return READ_MPEG_REG_BITS(AIU_MEM_I2S_CONTROL, 1, 2);
}
int if_audio_in_i2s_enable()
{
return READ_MPEG_REG_BITS(AUDIN_I2SIN_CTRL, I2SIN_EN, 1);
}
int pcm_out_is_mute(void)
{
int value = (READ_MPEG_REG_BITS(PCMOUT_CTRL2, 31, 1) & 0x01);
return value;
}
int pcm_in_is_enable(void)
{
int value = (READ_MPEG_REG_BITS(PCMIN_CTRL0, 31, 1) & 0x01);
return value;
}
int if_audio_in_spdif_enable()
{
return READ_MPEG_REG_BITS(AUDIN_SPDIF_MODE, 31, 1);
}
