static const struct reg_script pch_misc_init_script[] = {
/* Setup SLP signal assertion, SLP_S4=4s, SLP_S3=50ms */
REG_PCI_RMW16(GEN_PMCON_3, ~((3 << 4)|(1 << 10)),
(1 << 3)|(1 << 11)|(1 << 12)),
/* Prepare sleep mode */
REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN),
/* Setup NMI on errors, disable SERR */
REG_IO_RMW8(0x61, ~0xf0, (1 << 2)),
/* Disable NMI sources */
REG_IO_OR8(0x70, (1 << 7)),
/* Indicate DRAM init done for MRC */
REG_PCI_OR8(GEN_PMCON_2, (1 << 7)),
/* Enable BIOS updates outside of SMM */
REG_PCI_RMW8(0xdc, ~(1 << 5), 0),
/* Clear status bits to prevent unexpected wake */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x3310, 0x0000002f),
REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3f02, ~0x0000000f, 0),
/* Enable PCIe Releaxed Order */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2314, (1 << 31) | (1 << 7)),
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1114, (1 << 15) | (1 << 14)),
/* Setup SERIRQ, enable continuous mode */
REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)),
#if !CONFIG_SERIRQ_CONTINUOUS_MODE
REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0),
#endif
REG_SCRIPT_END
};
/* Magic register settings for power management */
static const struct reg_script pch_pm_init_script[] = {
REG_PCI_WRITE8(0xa9, 0x46),
static const struct reg_script ehci_disable_script[] = {
/* Clear Run/Stop Bit */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, ~USB2CMD_RS, 0),
/* Wait for HC Halted */
REG_RES_POLL32(PCI_BASE_ADDRESS_0, USB2STS,
USB2STS_HCHALT, USB2STS_HCHALT, 10000),
/* Disable Interrupts */
REG_PCI_OR32(EHCI_CMD_STS, INTRDIS),
/* Disable Asynchronous and Periodic Scheduler */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD,
~(USB2CMD_ASE | USB2CMD_PSE), 0),
/* Disable port wake */
REG_PCI_RMW32(EHCI_SBRN_FLA_PWC, ~(PORTWKIMP | PORTWKCAPMASK), 0),
/* Set Function Disable bit in RCBA */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + RCBA_FUNC_DIS, RCBA_EHCI_DIS),
REG_SCRIPT_END
};
static const struct reg_script ehci_hc_reset[] = {
REG_RES_OR16(PCI_BASE_ADDRESS_0, USB2CMD, USB2CMD_HCRESET),
REG_SCRIPT_END
};
static void usb2_phy_init(device_t dev)
{
struct soc_intel_baytrail_config *config = dev->chip_info;
struct reg_script usb2_phy_script[] = {
/* USB3PHYInit() */
REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, 0x4700),
/* Per port phy settings, set in devicetree.cb */
#include <soc/spi.h>
#include <soc/systemagent.h>
const struct reg_script system_agent_finalize_script[] = {
REG_PCI_OR16(0x50, 1 << 0), /* GGC */
REG_PCI_OR32(0x5c, 1 << 0), /* DPR */
REG_PCI_OR32(0x78, 1 << 10), /* ME */
REG_PCI_OR32(0x90, 1 << 0), /* REMAPBASE */
REG_PCI_OR32(0x98, 1 << 0), /* REMAPLIMIT */
REG_PCI_OR32(0xa0, 1 << 0), /* TOM */
REG_PCI_OR32(0xa8, 1 << 0), /* TOUUD */
REG_PCI_OR32(0xb0, 1 << 0), /* BDSM */
REG_PCI_OR32(0xb4, 1 << 0), /* BGSM */
REG_PCI_OR32(0xb8, 1 << 0), /* TSEGMB */
REG_PCI_OR32(0xbc, 1 << 0), /* TOLUD */
REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5500, 1 << 0), /* PAVP */
REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5f00, 1 << 31), /* SA PM */
REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6020, 1 << 0), /* UMA GFX */
REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x63fc, 1 << 0), /* VTDTRK */
REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6800, 1 << 31),
REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7000, 1 << 31),
REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x77fc, 1 << 0),
REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x50fc, 0x8f),
REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7ffc, 1 << 0),
REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5880, 1 << 5),
REG_MMIO_WRITE8(MCH_BASE_ADDRESS + 0x50fc, 0x8f), /* MC */
REG_SCRIPT_END
};
const struct reg_script pch_finalize_script[] = {
REG_PCI_WRITE16(LPC_IO_DEC, 0x0010), /* Enable legacy decode ranges */ REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN), /* Enable IOAPIC */ REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100), /* Read back for posted write */ REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC), /* Set HPET address and enable it */ REG_MMIO_RMW32(RCBA_BASE_ADDRESS + HPTC, ~3, (1 << 7)), /* Read back for posted write */ REG_MMIO_READ32(RCBA_BASE_ADDRESS + HPTC), /* Enable HPET to start counter */ REG_MMIO_OR32(HPET_BASE_ADDRESS + 0x10, (1 << 0)), /* Disable reset */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 5)), /* TCO timer halt */ REG_IO_OR16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT), /* Enable upper 128 bytes of CMOS */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + RC, (1 << 2)), /* Disable unused device (always) */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + FD, PCH_DISABLE_ALWAYS), REG_SCRIPT_END };
#include <uart8250.h>
#include <soc/iobp.h>
#include <soc/serialio.h>
const struct reg_script uart_init[] = {
/* Set MMIO BAR */
REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, CONFIG_TTYS0_BASE),
/* Enable Memory access and Bus Master */
REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER),
/* Initialize LTR */
REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_GEN,
~SIO_REG_PPR_GEN_LTR_MODE_MASK, 0),
REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST,
~(SIO_REG_PPR_RST_ASSERT), 0),
/* Take UART out of reset */
REG_MMIO_OR32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST,
SIO_REG_PPR_RST_ASSERT),
/* Set M and N divisor inputs and enable clock */
REG_MMIO_WRITE32(CONFIG_TTYS0_BASE + SIO_REG_PPR_CLOCK,
SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE |
(SIO_REG_PPR_CLOCK_N_DIV << 16) |
(SIO_REG_PPR_CLOCK_M_DIV << 1)),
REG_SCRIPT_END
};
void pch_uart_init(void)
{
/* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */
u32 gpiodf = 0x131f;
#if defined(__SIMPLE_DEVICE__)
pci_devfn_t dev;
#else
