void emac_set_clk_rmii(void) { //select ex clock source REG_SET_BIT(EMAC_EX_CLK_CTRL_REG, EMAC_EX_EXT_OSC_EN); //ex clk enable REG_SET_BIT(EMAC_EX_OSCCLK_CONF_REG, EMAC_EX_OSC_CLK_SEL); }
void emac_mac_init(void) { REG_SET_BIT(EMAC_GMACCONFIG_REG, EMAC_GMACDUPLEX); REG_SET_BIT(EMAC_GMACCONFIG_REG, EMAC_GMACMIIGMII); REG_CLR_BIT(EMAC_GMACCONFIG_REG, EMAC_GMACFESPEED); REG_SET_BIT(EMAC_GMACFRAMEFILTER_REG, EMAC_PROMISCUOUS_MODE); }
void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool force) { struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; if (!mci->update_2g5g && !force) return; if (mci->is_2g) { ar9003_mci_send_2g5g_status(ah, true); ar9003_mci_send_lna_transfer(ah, true); udelay(5); REG_CLR_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); if (!(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA)) ar9003_mci_osla_setup(ah, true); } else { ar9003_mci_send_lna_take(ah, true); udelay(5); REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); ar9003_mci_osla_setup(ah, false); ar9003_mci_send_2g5g_status(ah, true); } }
void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done) { struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; if (mci->update_2g5g) { if (mci->is_2g) { ar9003_mci_send_2g5g_status(ah, true); ar9003_mci_send_lna_transfer(ah, true); udelay(5); REG_CLR_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); if (!(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA)) { REG_SET_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN); } } else { ar9003_mci_send_lna_take(ah, true); udelay(5); REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); REG_CLR_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN); ar9003_mci_send_2g5g_status(ah, true); } } }
void emac_dma_init(void) { REG_SET_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_FORWARD_UNDERSIZED_GOOD_FRAMES); REG_SET_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_OPERATE_SECOND_FRAME); REG_SET_FIELD(EMAC_DMABUSMODE_REG, EMAC_PROG_BURST_LEN, 4); REG_SET_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_DMAOPERATION_MODE_REG); }
void ath9k_hw_abort_tx_dma(struct ath_hw *ah) { int maxdelay = 1000; int i, q; if (ah->curchan) { if (IS_CHAN_HALF_RATE(ah->curchan)) maxdelay *= 2; else if (IS_CHAN_QUARTER_RATE(ah->curchan)) maxdelay *= 4; } REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); for (q = 0; q < AR_NUM_QCU; q++) { for (i = 0; i < maxdelay; i++) { if (i) udelay(5); if (!ath9k_hw_numtxpending(ah, q)) break; } } REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); REG_WRITE(ah, AR_Q_TXD, 0); }
void ath9k_hw_abort_tx_dma(struct ath_hw *ah) { int i, q; REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); for (q = 0; q < AR_NUM_QCU; q++) { for (i = 0; i < 1000; i++) { if (i) udelay(5); if (!ath9k_hw_numtxpending(ah, q)) break; } } REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); REG_WRITE(ah, AR_Q_TXD, 0); }
void ath9k_hw_start_nfcal(struct ath_hw *ah) { REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); }
void emac_enable_flowctrl(void) { REG_SET_BIT(EMAC_GMACFLOWCONTROL_REG, EMAC_TRANSMIT_FLOW_CONTROL_ENABLE); REG_SET_BIT(EMAC_GMACFLOWCONTROL_REG, EMAC_RECEIVE_FLOW_CONTROL_ENABLE); REG_CLR_BIT(EMAC_GMACFLOWCONTROL_REG, EMAC_DISABLE_ZERO_QUANTA_PAUSE); REG_SET_FIELD(EMAC_GMACFLOWCONTROL_REG, EMAC_PAUSE_TIME, 0x1648); REG_SET_FIELD(EMAC_GMACFLOWCONTROL_REG, EMAC_PAUSE_LOW_THRESHOLD, 0x1); }
void esp_mpi_release_hardware( void ) { REG_SET_BIT(DPORT_RSA_PD_CTRL_REG, DPORT_RSA_PD); /* don't reset digital signature unit, as this resets AES also */ REG_SET_BIT(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_RSA); REG_CLR_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_RSA); _lock_release(&mpi_lock); }
void emac_set_clk_mii(void) { //select ex clock source REG_SET_BIT(EMAC_EX_CLK_CTRL_REG, EMAC_EX_EXT_OSC_EN); //ex clk enable REG_SET_BIT(EMAC_EX_OSCCLK_CONF_REG, EMAC_EX_OSC_CLK_SEL); //set mii mode rx/tx clk enable REG_SET_BIT(EMAC_EX_CLK_CTRL_REG, EMAC_EX_MII_CLK_RX_EN); REG_SET_BIT(EMAC_EX_CLK_CTRL_REG, EMAC_EX_MII_CLK_TX_EN); }
static void ar9003_mci_observation_set_up(struct ath_hw *ah) { struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; if (mci->config & ATH_MCI_CONFIG_MCI_OBS_MCI) { ath9k_hw_gpio_request_out(ah, 3, NULL, AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA); ath9k_hw_gpio_request_out(ah, 2, NULL, AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK); ath9k_hw_gpio_request_out(ah, 1, NULL, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA); ath9k_hw_gpio_request_out(ah, 0, NULL, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK); } else if (mci->config & ATH_MCI_CONFIG_MCI_OBS_TXRX) { ath9k_hw_gpio_request_out(ah, 3, NULL, AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX); ath9k_hw_gpio_request_out(ah, 2, NULL, AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX); ath9k_hw_gpio_request_out(ah, 1, NULL, AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX); ath9k_hw_gpio_request_out(ah, 0, NULL, AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX); ath9k_hw_gpio_request_out(ah, 5, NULL, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); } else if (mci->config & ATH_MCI_CONFIG_MCI_OBS_BT) { ath9k_hw_gpio_request_out(ah, 3, NULL, AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX); ath9k_hw_gpio_request_out(ah, 2, NULL, AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX); ath9k_hw_gpio_request_out(ah, 1, NULL, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA); ath9k_hw_gpio_request_out(ah, 0, NULL, AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK); } else return; REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, AR_GLB_DS_JTAG_DISABLE, 1); REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, AR_GLB_WLAN_UART_INTF_EN, 0); REG_SET_BIT(ah, AR_GLB_GPIO_CONTROL, ATH_MCI_CONFIG_MCI_OBS_GPIO); REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_GPIO_OBS_SEL, 0); REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL, 1); REG_WRITE(ah, AR_OBS, 0x4b); REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL1, 0x03); REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL2, 0x01); REG_RMW_FIELD(ah, AR_MACMISC, AR_MACMISC_MISC_OBS_BUS_LSB, 0x02); REG_RMW_FIELD(ah, AR_MACMISC, AR_MACMISC_MISC_OBS_BUS_MSB, 0x03); REG_RMW_FIELD(ah, AR_PHY_TEST_CTL_STATUS, AR_PHY_TEST_CTL_DEBUGPORT_SEL, 0x07); }
void hw_trng_enable(hw_trng_cb callback) { if (callback != NULL) { trng_cb = callback; hw_trng_clear_pending(); NVIC_EnableIRQ(TRNG_IRQn); } GLOBAL_INT_DISABLE(); REG_SET_BIT(CRG_TOP, CLK_AMBA_REG, TRNG_CLK_ENABLE); GLOBAL_INT_RESTORE(); REG_SET_BIT(TRNG, TRNG_CTRL_REG, TRNG_ENABLE); }
void ar9003_mci_set_power_awake(struct ath_hw *ah) { u32 btcoex_ctrl2, diag_sw; int i; u8 lna_ctrl, bt_sleep; for (i = 0; i < AH_WAIT_TIMEOUT; i++) { btcoex_ctrl2 = REG_READ(ah, AR_BTCOEX_CTRL2); if (btcoex_ctrl2 != 0xdeadbeef) break; udelay(AH_TIME_QUANTUM); } REG_WRITE(ah, AR_BTCOEX_CTRL2, (btcoex_ctrl2 | BIT(23))); for (i = 0; i < AH_WAIT_TIMEOUT; i++) { diag_sw = REG_READ(ah, AR_DIAG_SW); if (diag_sw != 0xdeadbeef) break; udelay(AH_TIME_QUANTUM); } REG_WRITE(ah, AR_DIAG_SW, (diag_sw | BIT(27) | BIT(19) | BIT(18))); lna_ctrl = REG_READ(ah, AR_OBS_BUS_CTRL) & 0x3; bt_sleep = REG_READ(ah, AR_MCI_RX_STATUS) & AR_MCI_RX_REMOTE_SLEEP; REG_WRITE(ah, AR_BTCOEX_CTRL2, btcoex_ctrl2); REG_WRITE(ah, AR_DIAG_SW, diag_sw); if (bt_sleep && (lna_ctrl == 2)) { REG_SET_BIT(ah, AR_BTCOEX_RC, 0x1); REG_CLR_BIT(ah, AR_BTCOEX_RC, 0x1); udelay(50); } }
static void ath9k_hw_setup_calibration(struct ath_hal *ah, struct hal_cal_list *currCal) { REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, currCal->calData->calCountMax); switch (currCal->calData->calType) { case IQ_MISMATCH_CAL: REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "starting IQ Mismatch Calibration\n"); break; case ADC_GAIN_CAL: REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "starting ADC Gain Calibration\n"); break; case ADC_DC_CAL: REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "starting ADC DC Calibration\n"); break; case ADC_DC_INIT_CAL: REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "starting Init ADC DC Calibration\n"); break; } REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), AR_PHY_TIMING_CTRL4_DO_CAL); }
static void ar9002_hw_setup_calibration(struct ath_hw *ah, struct ath9k_cal_list *currCal) { REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, currCal->calData->calCountMax); switch (currCal->calData->calType) { case IQ_MISMATCH_CAL: REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); DBG2("ath9k: " "starting IQ Mismatch Calibration\n"); break; case ADC_GAIN_CAL: REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); DBG2("ath9k: " "starting ADC Gain Calibration\n"); break; case ADC_DC_CAL: REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); DBG2("ath9k: " "starting ADC DC Calibration\n"); break; } REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), AR_PHY_TIMING_CTRL4_DO_CAL); }
/* * Helper for ASPM support. * * Disable PLL when in L0s as well as receiver clock when in L1. * This power saving option must be enabled through the SerDes. * * Programming the SerDes must go through the same 288 bit serial shift * register as the other analog registers. Hence the 9 writes. */ static void ar9003_hw_configpcipowersave(struct ath_hw *ah, bool power_off) { /* Nothing to do on restore for 11N */ if (!power_off /* !restore */) { /* set bit 19 to allow forcing of pcie core into L1 state */ REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); /* Several PCIe massages to ensure proper behaviour */ if (ah->config.pcie_waen) REG_WRITE(ah, AR_WA, ah->config.pcie_waen); else REG_WRITE(ah, AR_WA, ah->WARegVal); } /* * Configire PCIE after Ini init. SERDES values now come from ini file * This enables PCIe low power mode. */ if (ah->config.pcieSerDesWrite) { unsigned int i; struct ar5416IniArray *array; array = power_off ? &ah->iniPcieSerdes : &ah->iniPcieSerdesLowPower; for (i = 0; i < array->ia_rows; i++) { REG_WRITE(ah, INI_RA(array, i, 0), INI_RA(array, i, 1)); } } }
static void ar9003_mci_mute_bt(struct ath_hw *ah) { struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; /* disable all MCI messages */ REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, 0xffff0000); REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS0, 0xffffffff); REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS1, 0xffffffff); REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS2, 0xffffffff); REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS3, 0xffffffff); REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); /* wait pending HW messages to flush out */ udelay(10); /* * Send LNA_TAKE and SYS_SLEEPING when * 1. reset not after resuming from full sleep * 2. before reset MCI RX, to quiet BT and avoid MCI RX misalignment */ if (MCI_ANT_ARCH_PA_LNA_SHARED(mci)) { ar9003_mci_send_lna_take(ah, true); udelay(5); } ar9003_mci_send_sys_sleeping(ah, true); }
static void ar9003_hw_setup_calibration(struct ath_hw *ah, struct ath9k_cal_list *currCal) { /* Select calibration to run */ switch (currCal->calData->calType) { case IQ_MISMATCH_CAL: /* * Start calibration with * 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */ REG_RMW_FIELD(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX, currCal->calData->calCountMax); REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); DBG2("ath9k: " "starting IQ Mismatch Calibration\n"); /* Kick-off cal */ REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); break; case TEMP_COMP_CAL: REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM, AR_PHY_65NM_CH0_THERM_LOCAL, 1); REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM, AR_PHY_65NM_CH0_THERM_START, 1); DBG2("ath9k: " "starting Temperature Compensation Calibration\n"); break; } }
/* * This can stop or re-enables RX. * * If bool is set this will kill any frame which is currently being * transferred between the MAC and baseband and also prevent any new * frames from getting started. */ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set) { u32 reg; if (set) { REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0, AH_WAIT_TIMEOUT)) { REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); reg = REG_READ(ah, AR_OBS_BUS_1); ath_err(ath9k_hw_common(ah), "RX failed to go idle in 10 ms RXSM=0x%x\n", reg); return false; } } else { REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); } return true; }
void ath9k_hw_start_nfcal(struct ath_hw *ah, bool update) { if (ah->caldata) ah->caldata->nfcal_pending = true; REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); if (update) REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); else REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); }
void ath9k_hw_start_nfcal(struct ath_hw *ah, bool update) { if (ah->caldata) set_bit(NFCAL_PENDING, &ah->caldata->cal_flags); REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); if (update) REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); else REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); }
void emac_enable_clk(bool enable) { if (enable == true) { REG_SET_BIT(EMAC_CLK_EN_REG, EMAC_CLK_EN); } else { REG_CLR_BIT(EMAC_CLK_EN_REG, EMAC_CLK_EN); } }
void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan) { struct ath9k_nfcal_hist *h; int i, j; int32_t val; const u32 ar5416_cca_regs[6] = { AR_PHY_CCA, AR_PHY_CH1_CCA, AR_PHY_CH2_CCA, AR_PHY_EXT_CCA, AR_PHY_CH1_EXT_CCA, AR_PHY_CH2_EXT_CCA }; u8 chainmask; if (AR_SREV_9280(ah)) chainmask = 0x1B; else chainmask = 0x3F; #ifdef ATH_NF_PER_CHAN h = chan->nfCalHist; #else h = ah->nfCalHist; #endif for (i = 0; i < NUM_NF_READINGS; i++) { if (chainmask & (1 << i)) { val = REG_READ(ah, ar5416_cca_regs[i]); val &= 0xFFFFFE00; val |= (((u32) (h[i].privNF) << 1) & 0x1ff); REG_WRITE(ah, ar5416_cca_regs[i], val); } } REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); for (j = 0; j < 1000; j++) { if ((REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) break; udelay(10); } for (i = 0; i < NUM_NF_READINGS; i++) { if (chainmask & (1 << i)) { val = REG_READ(ah, ar5416_cca_regs[i]); val &= 0xFFFFFE00; val |= (((u32) (-50) << 1) & 0x1ff); REG_WRITE(ah, ar5416_cca_regs[i], val); } } }
void SystemClass::setCpuFrequency(CpuFrequency freq) { if (freq == eCF_160MHz) REG_SET_BIT(0x3ff00014, BIT(0)); else REG_CLR_BIT(0x3ff00014, BIT(0)); ets_update_cpu_frequency(freq); }
void IRAM_ATTR pm_off(void) { DEBUG ("%s\n", __func__); /* suspend UARTs */ for (int i = 0; i < 3; ++i) { REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF); uart_tx_wait_idle(i); } /* set all power down flags */ uint32_t pd_flags = RTC_SLEEP_PD_DIG | RTC_SLEEP_PD_RTC_PERIPH | RTC_SLEEP_PD_RTC_SLOW_MEM | RTC_SLEEP_PD_RTC_FAST_MEM | RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU | RTC_SLEEP_PD_VDDSDIO; rtc_sleep_config_t config = RTC_SLEEP_CONFIG_DEFAULT(pd_flags); config.wifi_pd_en = 1; config.rom_mem_pd_en = 1; config.lslp_meminf_pd = 1; /* Save current frequency and switch to XTAL */ rtc_cpu_freq_t cpu_freq = rtc_clk_cpu_freq_get(); rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL); /* set deep sleep duration to forever */ rtc_sleep_set_wakeup_time(rtc_time_get() + ~0x0UL); /* configure deep sleep */ rtc_sleep_init(config); rtc_sleep_start(RTC_TIMER_TRIG_EN, 0); /* Restore CPU frequency */ rtc_clk_cpu_freq_set(cpu_freq); /* resume UARTs */ for (int i = 0; i < 3; ++i) { REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF); REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON); REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON); } }
void emac_reset(void) { REG_SET_BIT(EMAC_DMABUSMODE_REG, EMAC_SW_RST); while (REG_GET_BIT(EMAC_DMABUSMODE_REG, EMAC_SW_RST) == 1) { //nothing to do ,if stop here,maybe emac have not clk input. ESP_LOGI(TAG, "emac resetting ...."); } ESP_LOGI(TAG, "emac reset done"); }
void pm_reboot(void) { DEBUG ("%s\n", __func__); /* suspend and flush UARTs */ for (int i = 0; i < 3; ++i) { REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF); uart_tx_wait_idle(i); } software_reset(); }
int ar9003_mci_end_reset(struct ath_hw *ah, struct ath9k_channel *chan, struct ath9k_hw_cal_data *caldata) { struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci; if (!mci_hw->ready) return 0; if (!IS_CHAN_2GHZ(chan) || (mci_hw->bt_state != MCI_BT_SLEEP)) goto exit; if (!ar9003_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET) && !ar9003_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)) goto exit; /* * BT is sleeping. Check if BT wakes up during * WLAN calibration. If BT wakes up during * WLAN calibration, need to go through all * message exchanges again and recal. */ REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, (AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET | AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE)); ar9003_mci_remote_reset(ah, true); ar9003_mci_send_sys_waking(ah, true); udelay(1); if (IS_CHAN_2GHZ(chan)) ar9003_mci_send_lna_transfer(ah, true); mci_hw->bt_state = MCI_BT_AWAKE; REG_CLR_BIT(ah, AR_PHY_TIMING4, 1 << AR_PHY_TIMING_CONTROL4_DO_GAIN_DC_IQ_CAL_SHIFT); if (caldata) { caldata->done_txiqcal_once = false; caldata->done_txclcal_once = false; caldata->rtt_done = false; } if (!ath9k_hw_init_cal(ah, chan)) return -EIO; REG_SET_BIT(ah, AR_PHY_TIMING4, 1 << AR_PHY_TIMING_CONTROL4_DO_GAIN_DC_IQ_CAL_SHIFT); exit: ar9003_mci_enable_interrupt(ah); return 0; }
void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx) { switch (rx) { case 0x5: REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); case 0x3: case 0x1: case 0x2: case 0x7: REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); break; default: break; } REG_WRITE(ah, AR_SELFGEN_MASK, tx); if (tx == 0x5) { REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); } }