void epit_start_timer(void)
{
REG_VAL(KZM_EPIT_STAT_ADDR) = 0x1;
/* Enable timer */
REG_VAL(KZM_EPIT_CTRL_ADDR) |= CTRL_EN;
}
static void led_light(unsigned int count)
{
unsigned int result = 0;
while (count-- > 0) {
REG_VAL(0xD8110024) |= 0x80;
REG_VAL(0xD8110054) |= 0x80;
REG_VAL(0xD8110084) &= ~0x80;
for (result = 3000000; result > 0; result--)
REG_VAL(0xD8110084) &= ~0x80;
for (result = 3000000; result > 0; result--)
REG_VAL(0xD8110084) |= 0x80;
}
}
void irq_handle(void)
{
/* Clear status bit. */
REG_VAL(KZM_EPIT_STAT_ADDR) = 0x1;
irq_acknowledge();
printf("EPIT time out...%d\n", count++);
}
void epit_init()
{
printf("EPIT init\n");
REG_VAL(KZM_EPIT_CTRL_ADDR) = 0;
/* Disable EPIT and reset. */
REG_VAL(KZM_EPIT_CTRL_ADDR) = CTRL_SWR;
/* Select Clock source */
REG_VAL(KZM_EPIT_CTRL_ADDR) = (CLKSRC_IPG << CTRL_CLKSRC_SHIFT);
/* Reload from load register */
REG_VAL(KZM_EPIT_CTRL_ADDR) |= (CTRL_RLD | CTRL_ENMOD);
/* Enable interrupt */
REG_VAL(KZM_EPIT_CTRL_ADDR) |= CTRL_OCIEN;
}
static int
jz4780_clk_pll_wait_lock(struct jz4780_clk_pll_sc *sc)
{
int i;
for (i = 0; i < PLL_TIMEOUT; i++) {
if (CLK_RD_4(sc, sc->clk_reg) & REG_VAL(CGU_PLL_LOCK, 1))
return (0);
DELAY(1000);
}
return (ETIMEDOUT);
}
int main(void)
{
qm_mpr_config_t cfg;
uint8_t lower_bound;
uint32_t heap_offset, mpr_base;
QM_PUTS("Starting: MPR");
/*
* The MPR is located in the heap in order to ensure it doesn't clash
* with anything so it is necessary to calculate the page number that
* corresponds to the start of the heap.
*/
heap_offset = (uint32_t)&__heap;
lower_bound = (uint8_t)((heap_offset - SRAM_BASE) / MPR_PAGE_SIZE) + 1;
/* Calculate the physical address of the start of the MPR. */
mpr_base = SRAM_BASE + (lower_bound * MPR_PAGE_SIZE);
/* Request the IRQ. */
qm_irq_request(QM_IRQ_SRAM_MPR_0_INT, qm_sram_mpr_0_isr);
/* Set the violation policy to trigger an interrupt. */
qm_mpr_set_violation_policy(MPR_VIOL_MODE_INTERRUPT,
mpr_example_callback, NULL);
/* Configure MPR to allow R/W from DMA agent only. */
cfg.en_lock_mask = QM_SRAM_MPR_EN_MASK_ENABLE;
cfg.agent_read_en_mask = QM_SRAM_MPR_AGENT_MASK_DMA;
cfg.agent_write_en_mask = QM_SRAM_MPR_AGENT_MASK_DMA;
cfg.up_bound = lower_bound;
cfg.low_bound = lower_bound;
qm_mpr_set_config(QM_MPR_0, &cfg);
/* Trigger a violation event by attempting a write inside the MPR. */
REG_VAL(mpr_base + 1) = 0xff;
/* Wait for the callback to be invoked. */
while (false == callback_invoked)
;
QM_PUTS("MPR Violation!");
QM_PUTS("Finished: MPR");
return 0;
}
/* QMSI MPR sample application: this example uses an MPR to pretect a 1kB page
of SRAM, and then triggers an MPR violation interrupt. */
int main(void)
{
qm_mpr_config_t cfg;
uint8_t lower_bound;
uint32_t heap_offset, sram_base, mpr_base;
QM_PUTS("\nMPR example app start");
/* we're going to put this MPR in the heap, to ensure it doesn't clash
* with anything else, so we need to figure out the page number that
* corresponds to the start of the heap */
heap_offset = (uint32_t)&__heap;
/* the IDT lives at the start of SRAM, so __idt_start gives us the SRAM
* base address in the Lakemont memory map */
sram_base = (uint32_t)&__idt_start;
lower_bound = (uint8_t)((heap_offset - sram_base) / MPR_PAGE_SIZE) + 1;
/* get the Lakemont physical address of the start of the MPR */
mpr_base = sram_base + (lower_bound * MPR_PAGE_SIZE);
/* Set the violation policy to trigger an interrupt */
qm_irq_request(QM_IRQ_SRAM, qm_mpr_isr);
qm_mpr_set_violation_policy(MPR_VIOL_MODE_INTERRUPT,
mpr_example_callback);
/* Configure MPR to allow R/W from DMA agent */
cfg.en_lock_mask = QM_SRAM_MPR_EN_MASK_ENABLE;
cfg.agent_read_en_mask = QM_SRAM_MPR_AGENT_MASK_DMA;
cfg.agent_write_en_mask = QM_SRAM_MPR_AGENT_MASK_DMA;
cfg.up_bound = lower_bound;
cfg.low_bound = lower_bound;
qm_mpr_set_config(QM_MPR_0, &cfg);
/* trigger a violation event by attempting a write inside the MPR */
REG_VAL(mpr_base + 1) = 0xff;
QM_PUTS("MPR example app complete");
return 0;
}
int main(void)
{
uint32_t flash_base;
uint32_t fpr_flash;
uint32_t value;
uint32_t app_end;
uint32_t address;
uint8_t low_bound;
qm_fpr_config_t cfg = {0};
#if (QUARK_D2000)
flash_base = QM_FLASH_REGION_SYS_0_BASE;
fpr_flash = QM_FLASH_0;
#elif(QUARK_SE)
flash_base = QM_FLASH_REGION_SYS_1_BASE;
fpr_flash = QM_FLASH_1;
#endif
QM_PRINTF("Starting: FPR\n");
/* Calculate how much space the application code occupies, so we can
* ensure our FPR does not overlap with it */
app_end = (uint32_t)__data_lma + (uint32_t)__data_size;
if ((app_end + FPR_SIZE + 1) > FLASH_END) {
QM_PRINTF("No free pages. Quitting.\n");
return 0;
}
/* Calculate 1k-aligned physical flash address for FPR start */
low_bound = ((app_end - flash_base) / FPR_SIZE) + 1;
/* Calculate MMIO address of a location inside the FPR */
address = (flash_base + (FPR_SIZE * low_bound)) + 4;
/* Set the violation policy to trigger an interrupt */
#if (QUARK_D2000)
qm_irq_request(QM_IRQ_FLASH_0, qm_fpr_isr_0);
#elif(QUARK_SE)
qm_irq_request(QM_IRQ_FLASH_1, qm_fpr_isr_1);
#endif
qm_fpr_set_violation_policy(FPR_VIOL_MODE_INTERRUPT, fpr_flash,
fpr_example_cb, NULL);
/* Configure MPR to allow R/W from DMA agent only */
cfg.en_mask = QM_FPR_ENABLE;
cfg.allow_agents = QM_FPR_DMA;
cfg.up_bound = low_bound + 1;
cfg.low_bound = low_bound;
qm_fpr_set_config(fpr_flash, QM_FPR_0, &cfg, QM_MAIN_FLASH_SYSTEM);
/* Trigger a violation event by attempting to read in the FLASH */
value = REG_VAL(address);
while (false == callback_invoked) {
}
QM_PRINTF("Finished: FPR\n");
value = value;
return 0;
}
/* Set interrupt interval, in milliseconds. */
void epit_set_interval(int interval)
{
REG_VAL(KZM_EPIT_LOAD_ADDR) = (IPG_CLK_KHZ * interval) ;
REG_VAL(KZM_EPIT_COMP_ADDR) = 0;
}
#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\
.ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
.ka_width = kaw }
#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
.hold_shift = hs, .bypass_shift = bs }
static const struct iproc_pll_ctrl genpll_scr = {
.flags = IPROC_CLK_AON | IPROC_CLK_PLL_SPLIT_STAT_CTRL,
.aon = AON_VAL(0x0, 1, 15, 12),
.reset = RESET_VAL(0x4, 2, 1),
.dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 2, 3),
.ndiv_int = REG_VAL(0x8, 4, 10),
.pdiv = REG_VAL(0x8, 0, 4),
.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
.status = REG_VAL(0x0, 27, 1),
};
static const struct iproc_clk_ctrl genpll_scr_clk[] = {
/* bypass_shift, the last value passed into ENABLE_VAL(), is not defined
* in NS2. However, it doesn't appear to be used anywhere, so setting
* it to 0.
*/
[BCM_NS2_GENPLL_SCR_SCR_CLK] = {
.channel = BCM_NS2_GENPLL_SCR_SCR_CLK,
.flags = IPROC_CLK_AON,
.enable = ENABLE_VAL(0x0, 18, 12, 0),
