BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc)
{
/* We only support interface 0, alternate interface 0. */
if (ifc != 0 || alt_ifc != 0)
return FALSE;
/* Perform procedure from TRM, section 2.3.7: */
/* (1) TODO. */
/* (2) Reset data toggles of the EPs in the interface. */
/* Note: RESETTOGGLE() gets the EP number WITH bit 7 set/cleared. */
RESETTOGGLE(0x82);
/* (3) Restore EPs to their default conditions. */
/* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */
RESETFIFO(0x02);
RESETTOGGLE(0x86);
RESETFIFO(0x06);
/* TODO */
/* (4) Clear the HSNAK bit. Not needed, fx2lib does this. */
return TRUE;
}
static void setup_endpoints(void)
{
/* Setup EP2 (IN). */
EP2CFG = (1 << 7) | /* EP is valid/activated */
(1 << 6) | /* EP direction: IN */
(1 << 5) | (0 << 4) | /* EP Type: bulk */
(1 << 3) | /* EP buffer size: 1024 */
(0 << 2) | /* Reserved. */
(0 << 1) | (0 << 0); /* EP buffering: quad buffering */
SYNCDELAY();
/* Disable all other EPs (EP1, EP4, EP6, and EP8). */
EP1INCFG &= ~bmVALID;
SYNCDELAY();
EP1OUTCFG &= ~bmVALID;
SYNCDELAY();
EP4CFG &= ~bmVALID;
SYNCDELAY();
EP6CFG &= (1 << 7) | /* EP is valid/activated */
(0 << 6) | /* EP direction: OUT */
(1 << 5) | (0 << 4) | /* EP Type: bulk */
(1 << 3) | /* EP buffer size: 1024 */
(0 << 2) | /* Reserved. */
(0 << 1) | (0 << 0); /* EP buffering: quad buffering */
SYNCDELAY();
EP8CFG &= ~bmVALID;
SYNCDELAY();
/* EP2: Reset the FIFOs. */
/* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */
RESETFIFO(0x02)
/* EP2: Enable AUTOIN mode. Set FIFO width to 8bits. */
EP2FIFOCFG = bmAUTOIN;
SYNCDELAY();
/* EP2: Auto-commit 512 (0x200) byte packets (due to AUTOIN = 1). */
EP2AUTOINLENH = 0x02;
SYNCDELAY();
EP2AUTOINLENL = 0x00;
SYNCDELAY();
/* EP2: Set the GPIF flag to 'full'. */
EP2GPIFFLGSEL = (1 << 1) | (0 << 1);
SYNCDELAY();
/* EP6: Reset the FIFOs. */
/* Note: RESETFIFO() gets the EP number WITHOUT bit 7 set/cleared. */
RESETFIFO(0x06)
/* EP6: Enable AUTOOUT mode. Set FIFO width to 8bits. */
EP6FIFOCFG = bmAUTOOUT;
SYNCDELAY();
OUTPKTEND = 0x82;
SYNCDELAY();
OUTPKTEND = 0x82;
}
BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc) {
printf ( "Set interface %d to alt: %d\n" , ifc, alt_ifc );
if (ifc==0&&alt_ifc==0) {
// SEE TRM 2.3.7
// reset toggles
RESETTOGGLE(0x02);
RESETTOGGLE(0x86);
// restore endpoints to default condition
RESETFIFO(0x02);
EP2BCL=0x80;
SYNCDELAY();
EP2BCL=0X80;
SYNCDELAY();
RESETFIFO(0x86);
return TRUE;
} else
return FALSE;
}
BOOL
handle_set_interface(BYTE interface, BYTE alt_interface)
{
if (interface != 0 || alt_interface != 0)
return FALSE;
RESETTOGGLE(0x01); /* ep1 out */
RESETTOGGLE(0x81); /* ep1 in */
RESETTOGGLE(0x82); /* ep2 in */
RESETTOGGLE(0x06); /* ep6 out */
RESETFIFO(2);
return TRUE;
}
