static bool check_cldap_reply_required_flags(uint32_t ret_flags,
uint32_t req_flags)
{
if (ret_flags == 0) {
return true;
}
if (req_flags & DS_PDC_REQUIRED)
RETURN_ON_FALSE(ret_flags & NBT_SERVER_PDC);
if (req_flags & DS_GC_SERVER_REQUIRED)
RETURN_ON_FALSE(ret_flags & NBT_SERVER_GC);
if (req_flags & DS_ONLY_LDAP_NEEDED)
RETURN_ON_FALSE(ret_flags & NBT_SERVER_LDAP);
if ((req_flags & DS_DIRECTORY_SERVICE_REQUIRED) ||
(req_flags & DS_DIRECTORY_SERVICE_PREFERRED))
RETURN_ON_FALSE(ret_flags & NBT_SERVER_DS);
if (req_flags & DS_KDC_REQUIRED)
RETURN_ON_FALSE(ret_flags & NBT_SERVER_KDC);
if (req_flags & DS_TIMESERV_REQUIRED)
RETURN_ON_FALSE(ret_flags & NBT_SERVER_TIMESERV);
if (req_flags & DS_WRITABLE_REQUIRED)
RETURN_ON_FALSE(ret_flags & NBT_SERVER_WRITABLE);
return true;
}
void CRTProgramPLL(PVRPSB_DEVINFO *psDevInfo, PLL_FREQ *psPllFreqInfo, PVRPSB_PIPE ePipe)
#endif
{
const IMG_UINT32 ui32DpioRefReg = (ePipe == PSB_PIPE_A) ? PVRPSB_DPIO_ADDR_REF_A : PVRPSB_DPIO_ADDR_REF_B;
const IMG_UINT32 ui32DpioMReg = (ePipe == PSB_PIPE_A) ? PVRPSB_DPIO_ADDR_M_A : PVRPSB_DPIO_ADDR_M_B;
const IMG_UINT32 ui32DpioNVcoReg = (ePipe == PSB_PIPE_A) ? PVRPSB_DPIO_ADDR_N_VCO_A : PVRPSB_DPIO_ADDR_N_VCO_B;
const IMG_UINT32 ui32DpioPReg = (ePipe == PSB_PIPE_A) ? PVRPSB_DPIO_ADDR_P_A : PVRPSB_DPIO_ADDR_P_B;
IMG_UINT32 ui32RegVal;
IMG_UINT32 ui32NVco;
IMG_UINT32 ui32M;
IMG_UINT32 ui32P;
IMG_UINT32 ui32Lane;
/* Reset the DPIO */
PVROSWriteMMIOReg(psDevInfo, PVRPSB_DPIO_CFG, 0);
PVROSReadMMIOReg(psDevInfo, PVRPSB_DPIO_CFG);
ui32RegVal = 0;
ui32RegVal = PVRPSB_DPIO_CFG_MODE_SET(ui32RegVal, PVRPSB_DPIO_CFG_MODE_SELECT0);
ui32RegVal = PVRPSB_DPIO_CFG_RESET_SET(ui32RegVal, 1);
PVROSWriteMMIOReg(psDevInfo, PVRPSB_DPIO_CFG, ui32RegVal);
/* Program the PLL registers */
RETURN_ON_FALSE(WriteDPIOReg(psDevInfo, ui32DpioRefReg, 0x0068A701)); /* Some magic */
RETURN_ON_FALSE(ReadDPIOReg(psDevInfo, ui32DpioMReg, &ui32M));
ui32M = PVRPSB_DPIO_DATA_M_M2_SET(ui32M, psPllFreqInfo->ui32M2);
RETURN_ON_FALSE(WriteDPIOReg(psDevInfo, ui32DpioMReg, ui32M));
RETURN_ON_FALSE(ReadDPIOReg(psDevInfo, ui32DpioNVcoReg, &ui32NVco));
ui32NVco = PVRPSB_DPIO_DATA_N_VCO_N_SET(ui32NVco, psPllFreqInfo->ui32N);
ui32NVco = PVRPSB_DPIO_DATA_N_VCO_MAGIC_SET(ui32NVco, 0x0107); /* Some more magic for good measure */
if (psPllFreqInfo->ui32Vco < 2250000)
{
ui32NVco = PVRPSB_DPIO_DATA_N_VCO_SEL_SET(ui32NVco, 0);
ui32NVco = PVRPSB_DPIO_DATA_N_VCO_CB_TUNE_SET(ui32NVco, 2);
}
else if (psPllFreqInfo->ui32Vco < 2750000)
{
ui32NVco = PVRPSB_DPIO_DATA_N_VCO_SEL_SET(ui32NVco, 1);
ui32NVco = PVRPSB_DPIO_DATA_N_VCO_CB_TUNE_SET(ui32NVco, 1);
}
else if (psPllFreqInfo->ui32Vco < 3300000)
{
ui32NVco = PVRPSB_DPIO_DATA_N_VCO_SEL_SET(ui32NVco, 2);
ui32NVco = PVRPSB_DPIO_DATA_N_VCO_CB_TUNE_SET(ui32NVco, 0);
}
else
{
ui32NVco = PVRPSB_DPIO_DATA_N_VCO_SEL_SET(ui32NVco, 3);
ui32NVco = PVRPSB_DPIO_DATA_N_VCO_CB_TUNE_SET(ui32NVco, 0);
}
RETURN_ON_FALSE(WriteDPIOReg(psDevInfo, ui32DpioNVcoReg, ui32NVco));
RETURN_ON_FALSE(ReadDPIOReg(psDevInfo, ui32DpioPReg, &ui32P));
ui32P = PVRPSB_DPIO_DATA_P_P1_SET(ui32P, psPllFreqInfo->ui32P1);
if (psPllFreqInfo->ui32P2 == 10)
{
ui32P = PVRPSB_DPIO_DATA_P_P2_DIVIDE_SET(ui32P, PVRPSB_DPIO_DATA_P_P2_DIVIDE_10);
}
else if (psPllFreqInfo->ui32P2 == 5)
{
ui32P = PVRPSB_DPIO_DATA_P_P2_DIVIDE_SET(ui32P, PVRPSB_DPIO_DATA_P_P2_DIVIDE_5);
}
else
{
printk(KERN_WARNING DRVNAME " - %s: Unrecognised P2 value\n", __FUNCTION__);
}
RETURN_ON_FALSE(WriteDPIOReg(psDevInfo, ui32DpioPReg, ui32P));
if (ePipe == PSB_PIPE_A)
{
RETURN_ON_FALSE(ReadDPIOReg(psDevInfo, PVRPSB_DPIO_ADDR_LANE0, &ui32Lane));
ui32Lane = PVRPSB_DPIO_DATA_LANE_ENABLE_SET(ui32Lane, 3);
RETURN_ON_FALSE(WriteDPIOReg(psDevInfo, PVRPSB_DPIO_ADDR_LANE0, ui32Lane));
RETURN_ON_FALSE(ReadDPIOReg(psDevInfo, PVRPSB_DPIO_ADDR_LANE1, &ui32Lane));
ui32Lane = PVRPSB_DPIO_DATA_LANE_ENABLE_SET(ui32Lane, 3);
RETURN_ON_FALSE(WriteDPIOReg(psDevInfo, PVRPSB_DPIO_ADDR_LANE1, ui32Lane));
RETURN_ON_FALSE(ReadDPIOReg(psDevInfo, PVRPSB_DPIO_ADDR_LANE2, &ui32Lane));
ui32Lane = PVRPSB_DPIO_DATA_LANE_ENABLE_SET(ui32Lane, 3);
RETURN_ON_FALSE(WriteDPIOReg(psDevInfo, PVRPSB_DPIO_ADDR_LANE2, ui32Lane));
RETURN_ON_FALSE(ReadDPIOReg(psDevInfo, PVRPSB_DPIO_ADDR_LANE3, &ui32Lane));
ui32Lane = PVRPSB_DPIO_DATA_LANE_ENABLE_SET(ui32Lane, 3);
RETURN_ON_FALSE(WriteDPIOReg(psDevInfo, PVRPSB_DPIO_ADDR_LANE3, ui32Lane));
}
}
