static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); CPUClass *cc = CPU_CLASS(c); DeviceClass *dc = DEVICE_CLASS(c); mcc->parent_realize = dc->realize; dc->realize = riscv_cpu_realizefn; mcc->parent_reset = cc->reset; cc->reset = riscv_cpu_reset; cc->has_work = riscv_cpu_has_work; cc->do_interrupt = riscv_cpu_do_interrupt; cc->dump_state = riscv_cpu_dump_state; cc->set_pc = riscv_cpu_set_pc; cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb; cc->gdb_read_register = riscv_cpu_gdb_read_register; cc->gdb_write_register = riscv_cpu_gdb_write_register; #ifdef CONFIG_USER_ONLY cc->handle_mmu_fault = riscv_cpu_handle_mmu_fault; #else cc->do_unassigned_access = riscv_cpu_unassigned_access; cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; #endif cc->gdb_num_core_regs = 73; }
static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); CPUClass *cc = CPU_CLASS(c); DeviceClass *dc = DEVICE_CLASS(c); device_class_set_parent_realize(dc, riscv_cpu_realize, &mcc->parent_realize); mcc->parent_reset = cc->reset; cc->reset = riscv_cpu_reset; cc->class_by_name = riscv_cpu_class_by_name; cc->has_work = riscv_cpu_has_work; cc->do_interrupt = riscv_cpu_do_interrupt; cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt; cc->dump_state = riscv_cpu_dump_state; cc->set_pc = riscv_cpu_set_pc; cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb; cc->gdb_read_register = riscv_cpu_gdb_read_register; cc->gdb_write_register = riscv_cpu_gdb_write_register; cc->gdb_num_core_regs = 33; #if defined(TARGET_RISCV32) cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; #elif defined(TARGET_RISCV64) cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; #endif cc->gdb_stop_before_watchpoint = true; cc->disas_set_info = riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY cc->do_unaligned_access = riscv_cpu_do_unaligned_access; cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; #endif #ifdef CONFIG_TCG cc->tcg_initialize = riscv_translate_init; cc->tlb_fill = riscv_cpu_tlb_fill; #endif /* For now, mark unmigratable: */ cc->vmsd = &vmstate_riscv_cpu; }