{ \ .reg = RK2928_CLKSEL_CON(1), \ .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \ RK3228_DIV_PERI_SHIFT) \ } #define RK3228_CPUCLK_RATE(_prate, _core_peri_div) \ { \ .prate = _prate, \ .divs = { \ RK3228_CLKSEL1(_core_peri_div), \ }, \ } static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = { RK3228_CPUCLK_RATE(816000000, 4), RK3228_CPUCLK_RATE(600000000, 4), RK3228_CPUCLK_RATE(312000000, 4), }; static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = { .core_reg = RK2928_CLKSEL_CON(0), .div_core_shift = 0, .div_core_mask = 0x1f, .mux_core_alt = 1, .mux_core_main = 0, .mux_core_shift = 6, .mux_core_mask = 0x1, }; PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
.val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \ RK3228_DIV_PERI_SHIFT) | \ HIWORD_UPDATE(_core_aclk_div, RK3228_DIV_ACLK_MASK, \ RK3228_DIV_ACLK_SHIFT), \ } #define RK3228_CPUCLK_RATE(_prate, _core_aclk_div, _core_peri_div) \ { \ .prate = _prate, \ .divs = { \ RK3228_CLKSEL1(_core_aclk_div, _core_peri_div), \ }, \ } static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = { RK3228_CPUCLK_RATE(1800000000, 1, 7), RK3228_CPUCLK_RATE(1704000000, 1, 7), RK3228_CPUCLK_RATE(1608000000, 1, 7), RK3228_CPUCLK_RATE(1512000000, 1, 7), RK3228_CPUCLK_RATE(1488000000, 1, 5), RK3228_CPUCLK_RATE(1416000000, 1, 5), RK3228_CPUCLK_RATE(1392000000, 1, 5), RK3228_CPUCLK_RATE(1296000000, 1, 5), RK3228_CPUCLK_RATE(1200000000, 1, 5), RK3228_CPUCLK_RATE(1104000000, 1, 5), RK3228_CPUCLK_RATE(1008000000, 1, 5), RK3228_CPUCLK_RATE(912000000, 1, 5), RK3228_CPUCLK_RATE(816000000, 1, 3), RK3228_CPUCLK_RATE(696000000, 1, 3), RK3228_CPUCLK_RATE(600000000, 1, 3), RK3228_CPUCLK_RATE(408000000, 1, 1),