void SSI3DMASlaveClass::configureSSI3() {
//
// Enable the SSI3 Peripheral.
//
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3);
ROM_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_SSI3);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);
// Configure GPIO Pins for SSI3 mode.
//
ROM_GPIOPinConfigure(GPIO_PQ0_SSI3CLK);
ROM_GPIOPinConfigure(GPIO_PQ1_SSI3FSS);
ROM_GPIOPinConfigure(GPIO_PQ2_SSI3XDAT0);
ROM_GPIOPinConfigure(GPIO_PQ3_SSI3XDAT1);
ROM_GPIOPinTypeSSI(GPIO_PORTQ_BASE, GPIO_PIN_3 | GPIO_PIN_2 | GPIO_PIN_1 | GPIO_PIN_0);
ROM_SSIConfigSetExpClk(SSI3_BASE, F_CPU, SSI_FRF_MOTO_MODE_0,
SSI_MODE_SLAVE, SPI_CLOCK / 12, 8);
ROM_SSIEnable(SSI3_BASE);
ROM_SSIDMAEnable(SSI3_BASE, SSI_DMA_RX | SSI_DMA_TX);
}
//*****************************************************************************
//
// Initializes the SSI1 peripheral and sets up the TX and RX uDMA channels.
// The SSI is configured for loopback mode so that any data sent on TX will be
// received on RX. The uDMA channels are configured so that the TX channel
// will copy data from a buffer to the SSI TX output. And the uDMA RX channel
// will receive any incoming data into a pair of buffers in ping-pong mode.
//
//*****************************************************************************
void
InitSSI2Transfer(void)
{
unsigned long SysClock=ROM_SysCtlClockGet();
//
// Enable the SSI peripheral, and configure it to operate even if the CPU
// is in sleep.
//
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
ROM_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_SSI2);
UARTprintf("%u\n",SysClock);
GPIOPinConfigure(GPIO_PB4_SSI2CLK);
GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_3, GPIO_PIN_3);
GPIOPinConfigure(GPIO_PB5_SSI2FSS);
GPIOPinConfigure(GPIO_PB6_SSI2RX);
GPIOPinConfigure(GPIO_PB7_SSI2TX);
GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7);
//
// Configure the SSI communication parameters.
//
//UARTprintf("%u\n",SysClock);
ROM_SSIConfigSetExpClk(SSI2_BASE, SysClock,
SSI_FRF_MOTO_MODE_1,
SSI_MODE_SLAVE,
1000000,
16);
//
// Set both the TX and RX trigger thresholds to 4. This will be used by
// the uDMA controller to signal when more data should be transferred. The
// uDMA TX and RX channels will be configured so that it can transfer 4
// bytes in a burst when the SSI is ready to transfer more data.
//
//ROM_SSIFIFOLevelSet(SSI2_BASE, SSI_FIFO_TX4_8, SSI_FIFO_RX4_8);
HWREG(SSI2_BASE + SSI_O_CR1) |= 0x00000020; // set Slave Bypass mode
//
// Enable the SSI for operation, and enable the uDMA interface for both TX
// and RX channels.
//
ROM_SSIEnable(SSI2_BASE);
ROM_SSIDMAEnable(SSI2_BASE, SSI_DMA_RX | SSI_DMA_TX);
//
// This register write will set the SSI to operate in loopback mode. Any
// data sent on the TX output will be received on the RX input.
//
//
// Enable the SSI peripheral interrupts. Note that no SSI interrupts
// were enabled, but the uDMA controller will cause an interrupt on the
// SSI interrupt signal when a uDMA transfer is complete.
//
ROM_IntEnable(INT_SSI2);
//
// Put the attributes in a known state for the uDMA SSI2RX channel. These
// should already be disabled by default.
//
ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_SSI2TX,
UDMA_ATTR_ALTSELECT | UDMA_ATTR_USEBURST |
UDMA_ATTR_HIGH_PRIORITY |
UDMA_ATTR_REQMASK);
ROM_uDMAChannelAssign(UDMA_CH13_SSI2TX);
//
// Configure the control parameters for the primary control structure for
// the SSI RX channel. The primary contol structure is used for the "A"
// part of the ping-pong receive. The transfer data size is 8 bits, the
// source address does not increment since it will be reading from a
// register. The destination address increment is byte 8-bit bytes. The
// arbitration size is set to 4 to match the RX FIFO trigger threshold.
// The uDMA controller will use a 4 byte burst transfer if possible. This
// will be somewhat more effecient that single byte transfers.
//
ROM_uDMAChannelControlSet(UDMA_CHANNEL_SSI2TX | UDMA_PRI_SELECT,
UDMA_SIZE_16 | UDMA_SRC_INC_16 | UDMA_DST_INC_NONE |
UDMA_ARB_4);
//
// Configure the control parameters for the alternate control structure for
// the SSI RX channel. The alternate contol structure is used for the "B"
// part of the ping-pong receive. The configuration is identical to the
// primary/A control structure.
//
ROM_uDMAChannelControlSet(UDMA_CHANNEL_SSI2TX | UDMA_ALT_SELECT,
UDMA_SIZE_16 | UDMA_SRC_INC_16 | UDMA_DST_INC_NONE |
UDMA_ARB_4);
//
// Set up the transfer parameters for the SSI RX primary control
// structure. The mode is set to ping-pong, the transfer source is the
// SSI data register, and the destination is the receive "A" buffer. The
// transfer size is set to match the size of the buffer.
//
ROM_uDMAChannelTransferSet(UDMA_CHANNEL_SSI2TX | UDMA_PRI_SELECT,
UDMA_MODE_PINGPONG,
(void *)g_uiSsiTxBufA,
(void *)(SSI2_BASE + SSI_O_DR),
SSI_TXBUF_SIZE);
//
// Set up the transfer parameters for the SSI RX alternate control
// structure. The mode is set to ping-pong, the transfer source is the
// SSI data register, and the destination is the receive "B" buffer. The
// transfer size is set to match the size of the buffer.
//
ROM_uDMAChannelTransferSet(UDMA_CHANNEL_SSI2TX | UDMA_ALT_SELECT,
UDMA_MODE_PINGPONG,
(void *)g_uiSsiTxBufB,
(void *)(SSI2_BASE + SSI_O_DR),
SSI_TXBUF_SIZE);
ROM_uDMAChannelAttributeEnable(UDMA_CHANNEL_SSI2TX, UDMA_ATTR_USEBURST);
UARTprintf("A_base: %X \n",(void *)g_uiSsiTxBufA);
UARTprintf("B_base: %X \n",(void *)(g_uiSsiTxBufB));
//
// Put the attributes in a known state for the uDMA SSI2TX channel. These
// should already be disabled by default.
//
ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_SSI2RX,
UDMA_ATTR_ALTSELECT |
UDMA_ATTR_HIGH_PRIORITY |
UDMA_ATTR_REQMASK);
ROM_uDMAChannelAssign(UDMA_CH12_SSI2RX);
//
// Set the USEBURST attribute for the uDMA SSI RX channel. This will
// force the controller to always use a burst when transferring data from
// the TX buffer to the SSI. This is somewhat more effecient bus usage
// than the default which allows single or burst transfers.
//
ROM_uDMAChannelAttributeEnable(UDMA_CHANNEL_SSI2RX, UDMA_ATTR_USEBURST);
//
// Configure the control parameters for the SSI TX. The uDMA SSI TX
// channel is used to transfer a block of data from a buffer to the SSI.
// The data size is 8 bits. The source address increment is 8-bit bytes
// since the data is coming from a buffer. The destination increment is
// none since the data is to be written to the SSI data register. The
// arbitration size is set to 4, which matches the SSI TX FIFO trigger
// threshold.
//
ROM_uDMAChannelControlSet(UDMA_CHANNEL_SSI2RX | UDMA_PRI_SELECT,
UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 |
UDMA_ARB_4);
//
// Set up the transfer parameters for the uDMA SSI TX channel. This will
// configure the transfer source and destination and the transfer size.
// Basic mode is used because the peripheral is making the uDMA transfer
// request. The source is the TX buffer and the destination is the SSI
// data register.
//
ROM_uDMAChannelTransferSet(UDMA_CHANNEL_SSI2RX | UDMA_PRI_SELECT,
UDMA_MODE_BASIC,
(void *)(SSI2_BASE + SSI_O_DR),
(void *)g_uiSsiRxBuf,
SSI_RXBUF_SIZE);
//
// Now both the uDMA SSI TX and RX channels are primed to start a
// transfer. As soon as the channels are enabled, the peripheral will
// issue a transfer request and the data transfers will begin.
//
ROM_uDMAChannelEnable(UDMA_CHANNEL_SSI2TX);
ROM_uDMAChannelEnable(UDMA_CHANNEL_SSI2RX);
GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_3, 0);
}
