unsigned* target_atag_mem(unsigned* ptr) { struct smem_ram_ptable ram_ptable; unsigned i = 0; if (smem_ram_ptable_init(&ram_ptable)) { for (i = 0; i < ram_ptable.len; i++) { if ((ram_ptable.parts[i].attr == READWRITE) && (ram_ptable.parts[i].domain == APPS_DOMAIN) && (ram_ptable.parts[i].start != 0x0) && (!(ROUND_TO_MB(ram_ptable.parts[i].size) <= SIZE_1M))) { /* ATAG_MEM */ *ptr++ = 4; *ptr++ = 0x54410002; /* RAM parition are reported correctly by NON-HLOS Use the size passed directly */ if (target_is_emmc_boot()) *ptr++ = ROUND_TO_MB(ram_ptable.parts[i].size); else *ptr++ = ram_ptable.parts[i].size; *ptr++ = ram_ptable.parts[i].start; } } } else { dprintf(CRITICAL, "ERROR: Unable to read RAM partition\n"); ASSERT(0); } return ptr; }
/* Setup memory for this platform */ void platform_init_mmu_mappings(void) { uint32_t i; uint32_t sections; struct smem_ram_ptable ram_ptable; uint32_t vaddress = 0; if (smem_ram_ptable_init(&ram_ptable)) { for (i = 0; i < ram_ptable.len; i++) { if ((ram_ptable.parts[i].attr == READWRITE) && (ram_ptable.parts[i].domain == APPS_DOMAIN) && (ram_ptable.parts[i].start != 0x0) && (!(ram_ptable.parts[i].size < MB))) { sections = ram_ptable.parts[i].size >> 20; if (vaddress == 0) { vaddress = ROUND_TO_MB(ram_ptable.parts[i].start); } while (sections--) { arm_mmu_map_section(ROUND_TO_MB(ram_ptable.parts[i].start) + sections*MB, vaddress + sections*MB, ALL_MEMORY); } vaddress += ROUND_TO_MB(ram_ptable.parts[i].size); available_scratch_mem += ROUND_TO_MB(ram_ptable.parts[i].size); } } } else {