/**
* @brief Main program.
* @param None
* @retval None
*/
uint32_t main(void)
{
RST_CLK_DeInit();
/* Select HSI/2 as CPU_CLK source*/
RST_CLK_CPU_PLLconfig (RST_CLK_CPU_PLLsrcHSIdiv2,0);
/* Periph clocks enable */
RST_CLK_PCLKcmd((RST_CLK_PCLK_RST_CLK | RST_CLK_PCLK_CAN1),ENABLE);
RST_CLK_PCLKcmd(RST_CLK_PCLK_PORTD,ENABLE);
/* Reset PORTD settings */
PORT_DeInit(MDR_PORTD);
/* Configure PORTD pins 10,11 for output to switch LED on/off */
PORT_InitStructure.PORT_FUNC = PORT_FUNC_PORT;
PORT_InitStructure.PORT_Pin = PORT_Pin_10 | PORT_Pin_11;
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_InitStructure.PORT_MODE = PORT_MODE_DIGITAL;
PORT_InitStructure.PORT_SPEED = PORT_SPEED_SLOW;
PORT_Init(MDR_PORTD, &PORT_InitStructure);
/* CAN transmit at 125Kb/s and receive by polling in loopback mode */
TestRx = CAN_Polling();
if (TestRx == FAILED)
{
/* Turn on led LED2 */
LEDOn(LED2);
}
else
{
/* Turn on led LED1 */
LEDOn(LED1);
}
while(1);
}
void BRD_Clock_Init_HSE_PLL(uint32_t PLL_Mul_sub1) // 128 MHz
{
// Сброс настроек системы тактирования
RST_CLK_DeInit();
// Инициализация генератора на внешнем кварцевом резонаторе (HSE)
RST_CLK_HSEconfig (RST_CLK_HSE_ON);
while (RST_CLK_HSEstatus() != SUCCESS);
// Инициализация блока PLL
// Включение использования PLL
RST_CLK_CPU_PLLcmd (ENABLE);
// Настройка источника и коэффициента умножения PLL
// (CPU_C1_SEL = HSE)
RST_CLK_CPU_PLLconfig (RST_CLK_CPU_PLLsrcHSEdiv1, PLL_Mul_sub1);
while (RST_CLK_CPU_PLLstatus() != SUCCESS);
// Подключение PLL к системе тактирования
// (CPU_C2_SEL = PLLCPUo)
RST_CLK_CPU_PLLuse (ENABLE);
// Настройка коэффициента деления блока CPU_C3_SEL
// (CPU_C3_SEL = CPU_C2)
RST_CLK_CPUclkPrescaler (RST_CLK_CPUclkDIV1);
// Использование процессором сигнала CPU_C3
// (HCLK = CPU_C3)
RST_CLK_CPUclkSelection (RST_CLK_CPUclkCPU_C3);
// Update System Clock
BRD_CPU_CLK = HSE_Value * (PLL_Mul_sub1 + 1);
}
/* Frequencies setup */
void Setup_CPU_Clock(void)
{
/* Enable HSE */
RST_CLK_HSEconfig(RST_CLK_HSE_ON);
if (RST_CLK_HSEstatus() != SUCCESS)
{
/* Trap */
while (1)
{
}
}
/* CPU_C1_SEL = HSE */
RST_CLK_CPU_PLLconfig(RST_CLK_CPU_PLLsrcHSEdiv1, RST_CLK_CPU_PLLmul10);
RST_CLK_CPU_PLLcmd(ENABLE);
if (RST_CLK_CPU_PLLstatus() != SUCCESS)
{
/* Trap */
while (1)
{
}
}
/* CPU_C3_SEL = CPU_C2_SEL */
RST_CLK_CPUclkPrescaler(RST_CLK_CPUclkDIV1);
/* CPU_C2_SEL = PLL */
RST_CLK_CPU_PLLuse(ENABLE);
/* HCLK_SEL = CPU_C3_SEL */
RST_CLK_CPUclkSelection(RST_CLK_CPUclkCPU_C3);
}
/**
* @brief Configure CPU clock.
* @param None
* @retval None
*/
void ClockConfigure ( void )
{
/* Enable HSE (High Speed External) clock */
RST_CLK_HSEconfig(RST_CLK_HSE_ON);
if (RST_CLK_HSEstatus() == ERROR) {
while (1);
}
/* Configures the CPU_PLL clock source */
RST_CLK_CPU_PLLconfig(RST_CLK_CPU_PLLsrcHSEdiv1, RST_CLK_CPU_PLLmul10);
/* Enables the CPU_PLL */
RST_CLK_CPU_PLLcmd(ENABLE);
if (RST_CLK_CPU_PLLstatus() == ERROR) {
while (1);
}
/* Enables the RST_CLK_PCLK_EEPROM */
RST_CLK_PCLKcmd(RST_CLK_PCLK_EEPROM, ENABLE);
/* Sets the code latency value */
EEPROM_SetLatency(EEPROM_Latency_3);
/* Select the CPU_PLL output as input for CPU_C3_SEL */
RST_CLK_CPU_PLLuse(ENABLE);
/* Set CPUClk Prescaler */
RST_CLK_CPUclkPrescaler(RST_CLK_CPUclkDIV1);
/* Select the CPU clock source */
RST_CLK_CPUclkSelection(RST_CLK_CPUclkCPU_C3);
}
/*******************************************************************************
* Function Name : ClockConfigure
* Description : Configures the CPU_PLL and RTCHSE clock.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ClockConfigure(void)
{
/* Configure CPU_PLL clock */
RST_CLK_CPU_PLLconfig (RST_CLK_CPU_PLLsrcHSIdiv1,0);
/* Enables the RTCHSE clock on all ports */
RST_CLK_PCLKcmd(ALL_PORTS_CLK, ENABLE);
}
void BRD_Clock_Init_HSE_PLL(uint32_t PLL_Mul_sub1)
{
uint32_t freqCPU;
RST_CLK_DeInit();
/* Enable HSE (High Speed External) clock */
RST_CLK_HSEconfig(RST_CLK_HSE_ON);
while (RST_CLK_HSEstatus() != SUCCESS);
// /* Configures the CPU_PLL clock source */
RST_CLK_CPU_PLLconfig(RST_CLK_CPU_PLLsrcHSEdiv1, PLL_Mul_sub1);
/* Enables the CPU_PLL */
RST_CLK_CPU_PLLcmd(ENABLE);
while (RST_CLK_CPU_PLLstatus() == ERROR);
/* Enables the RST_CLK_PCLK_EEPROM */
RST_CLK_PCLKcmd(RST_CLK_PCLK_EEPROM, ENABLE);
/* Sets the code latency value */
freqCPU = HSE_Value * (PLL_Mul_sub1 + 1);
if (freqCPU < 25E+6)
EEPROM_SetLatency(EEPROM_Latency_0);
else if (freqCPU < 50E+6)
EEPROM_SetLatency(EEPROM_Latency_1);
else if (freqCPU < 75E+6)
EEPROM_SetLatency(EEPROM_Latency_2);
else if (freqCPU < 100E+6)
EEPROM_SetLatency(EEPROM_Latency_3);
else if (freqCPU < 125E+6)
EEPROM_SetLatency(EEPROM_Latency_4);
else //if (PLL_Mul * HSE_Value <= 150E+6)
EEPROM_SetLatency(EEPROM_Latency_5);
// Additional Supply Power
if (freqCPU < 40E+6)
SetSelectRI(RI_till_40MHz);
else if (freqCPU < 80E+6)
SetSelectRI(RI_till_80MHz);
else
SetSelectRI(RI_over_80MHz);
/* Select the CPU_PLL output as input for CPU_C3_SEL */
RST_CLK_CPU_PLLuse(ENABLE);
/* Set CPUClk Prescaler */
RST_CLK_CPUclkPrescaler(RST_CLK_CPUclkDIV1);
/* Select the CPU clock source */
RST_CLK_CPUclkSelection(RST_CLK_CPUclkCPU_C3);
// Update System Clock
BRD_CPU_CLK = freqCPU;
}
//-----------------------------------------------------------------//
// Setup clocks
// CPU core clock (HCLK) = 32 MHz clock from 4 MHz HSE
// ADC clock = 4 MHz clock from 4 MHz HSE
//-----------------------------------------------------------------//
void Setup_CPU_Clock(void)
{
// Enable HSE
RST_CLK_HSEconfig(RST_CLK_HSE_ON);
if (RST_CLK_HSEstatus() != SUCCESS)
{
while (1) {} // Trap
}
//-------------------------------//
// Setup CPU PLL and CPU_C1_SEL
// CPU_C1 = HSE, PLL = x8
RST_CLK_CPU_PLLconfig(RST_CLK_CPU_PLLsrcHSEdiv1, RST_CLK_CPU_PLLmul8);
RST_CLK_CPU_PLLcmd(ENABLE);
if (RST_CLK_CPU_PLLstatus() != SUCCESS)
{
while (1) {} // Trap
}
// Setup CPU_C2 and CPU_C3
// CPU_C3 = CPU_C2
RST_CLK_CPUclkPrescaler(RST_CLK_CPUclkDIV1);
// CPU_C2 = CPU PLL output
RST_CLK_CPU_PLLuse(ENABLE);
// Switch to CPU_C3
// HCLK = CPU_C3
RST_CLK_CPUclkSelection(RST_CLK_CPUclkCPU_C3);
//-------------------------------//
// Setup ADC clock
// ADC_C2 = CPU_C1
RST_CLK_ADCclkSelection(RST_CLK_ADCclkCPU_C1);
// ADC_C3 = ADC_C2
RST_CLK_ADCclkPrescaler(RST_CLK_ADCclkDIV1);
// Enable ADC_CLK
RST_CLK_ADCclkEnable(ENABLE);
// Update system clock variable
SystemCoreClockUpdate();
// Enable clock on all ports (macro are defined in systemfunc.h)
RST_CLK_PCLKcmd(ALL_PORTS_CLK, ENABLE);
// Enable clock on peripheral blocks used in design
RST_CLK_PCLKcmd(PERIPHERALS_CLK ,ENABLE);
}
/**
* @brief Main program.
* @param None
* @retval None
*/
void main ( void )
{
uint8_t DataByte = 0x00;
static uint8_t ReciveByte = 0x00;
/* Enables the HSI clock on PORTD */
RST_CLK_PCLKcmd(RST_CLK_PCLK_PORTD, ENABLE);
/* Fill PortInit structure*/
PortInit.PORT_PULL_UP = PORT_PULL_UP_OFF;
PortInit.PORT_PULL_DOWN = PORT_PULL_DOWN_OFF;
PortInit.PORT_PD_SHM = PORT_PD_SHM_OFF;
PortInit.PORT_PD = PORT_PD_DRIVER;
PortInit.PORT_GFEN = PORT_GFEN_OFF;
PortInit.PORT_FUNC = PORT_FUNC_MAIN;
PortInit.PORT_SPEED = PORT_SPEED_MAXFAST;
PortInit.PORT_MODE = PORT_MODE_DIGITAL;
/* Configure PORTD pins 13 (UART2_TX) as output */
PortInit.PORT_OE = PORT_OE_OUT;
PortInit.PORT_Pin = PORT_Pin_13;
PORT_Init(MDR_PORTD, &PortInit);
/* Configure PORTD pins 14 (UART1_RX) as input */
PortInit.PORT_OE = PORT_OE_IN;
PortInit.PORT_Pin = PORT_Pin_14;
PORT_Init(MDR_PORTD, &PortInit);
/* Select HSI/2 as CPU_CLK source*/
RST_CLK_CPU_PLLconfig(RST_CLK_CPU_PLLsrcHSIdiv2, 0);
/* Enables the CPU_CLK clock on UART2 */
RST_CLK_PCLKcmd(RST_CLK_PCLK_UART2, ENABLE);
/* Set the HCLK division factor = 1 for UART2*/
UART_BRGInit(MDR_UART2, UART_HCLKdiv1 );
/* Initialize UART_InitStructure */
UART_InitStructure.UART_BaudRate = 9600;
UART_InitStructure.UART_WordLength = UART_WordLength8b;
UART_InitStructure.UART_StopBits = UART_StopBits2;
UART_InitStructure.UART_Parity = UART_Parity_Even;
UART_InitStructure.UART_FIFOMode = UART_FIFO_OFF;
UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_RXE
| UART_HardwareFlowControl_TXE;
/* Configure UART2 parameters*/
UART_Init(MDR_UART2, &UART_InitStructure);
/* Enables UART2 peripheral */
UART_Cmd(MDR_UART2, ENABLE);
while (1) {
/* Check TXFE flag */
while (UART_GetFlagStatus(MDR_UART2, UART_FLAG_TXFE) != SET);
/* Send Data from UART2 */
UART_SendData(MDR_UART2, DataByte);
/* Check RXFF flag */
while (UART_GetFlagStatus(MDR_UART2, UART_FLAG_RXFF) != SET);
/* Recive data*/
ReciveByte = UART_ReceiveData(MDR_UART2);
/* Increment Data */
DataByte++;
}
}
void main(void)
#endif
{
uint32_t i;
RST_CLK_DeInit();
RST_CLK_CPU_PLLconfig (RST_CLK_CPU_PLLsrcHSIdiv2,0);
/* Enable peripheral clocks --------------------------------------------------*/
RST_CLK_PCLKcmd((RST_CLK_PCLK_RST_CLK | RST_CLK_PCLK_TIMER1 | RST_CLK_PCLK_DMA),ENABLE);
RST_CLK_PCLKcmd((RST_CLK_PCLK_PORTA), ENABLE);
/* Init NVIC */
SCB->AIRCR = 0x05FA0000 | ((uint32_t)0x500);
SCB->VTOR = 0x08000000;
/* Disable all interrupt */
NVIC->ICPR[0] = 0xFFFFFFFF;
NVIC->ICER[0] = 0xFFFFFFFF;
/* Disable all DMA request */
MDR_DMA->CHNL_REQ_MASK_CLR = 0xFFFFFFFF;
MDR_DMA->CHNL_USEBURST_CLR = 0xFFFFFFFF;
/* Reset PORTB settings */
PORT_DeInit(MDR_PORTB);
/* Reset PORTF settings */
PORT_DeInit(MDR_PORTF);
/* Configure TIMER1 pins: CH1, CH2 */
/* Configure PORTA pins 1, 3 */
PORT_InitStructure.PORT_Pin = PORT_Pin_1;
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_InitStructure.PORT_FUNC = PORT_FUNC_ALTER;
PORT_InitStructure.PORT_MODE = PORT_MODE_DIGITAL;
PORT_InitStructure.PORT_SPEED = PORT_SPEED_FAST;
PORT_Init(MDR_PORTA, &PORT_InitStructure);
PORT_InitStructure.PORT_Pin = PORT_Pin_3;
PORT_InitStructure.PORT_OE = PORT_OE_IN;
PORT_Init(MDR_PORTA, &PORT_InitStructure);
/* Init RAM */
Init_RAM (DstBuf, BufferSize);
/* Reset all TIMER1 settings */
TIMER_DeInit(MDR_TIMER1);
TIMER_BRGInit(MDR_TIMER1,TIMER_HCLKdiv1);
/* TIM1 configuration ------------------------------------------------*/
/* Initializes the TIMERx Counter ------------------------------------*/
sTIM_CntInit.TIMER_Prescaler = 0x10;
sTIM_CntInit.TIMER_Period = 0x200;
sTIM_CntInit.TIMER_CounterMode = TIMER_CntMode_ClkFixedDir;
sTIM_CntInit.TIMER_CounterDirection = TIMER_CntDir_Up;
sTIM_CntInit.TIMER_EventSource = TIMER_EvSrc_None;
sTIM_CntInit.TIMER_FilterSampling = TIMER_FDTS_TIMER_CLK_div_1;
sTIM_CntInit.TIMER_ARR_UpdateMode = TIMER_ARR_Update_Immediately;
sTIM_CntInit.TIMER_ETR_FilterConf = TIMER_Filter_1FF_at_TIMER_CLK;
sTIM_CntInit.TIMER_ETR_Prescaler = TIMER_ETR_Prescaler_None;
sTIM_CntInit.TIMER_ETR_Polarity = TIMER_ETRPolarity_NonInverted;
sTIM_CntInit.TIMER_BRK_Polarity = TIMER_BRKPolarity_NonInverted;
TIMER_CntInit (MDR_TIMER1,&sTIM_CntInit);
/* Initializes the TIMER1 Channel1 -------------------------------------*/
TIMER_ChnStructInit(&sTIM_ChnInit);
sTIM_ChnInit.TIMER_CH_Number = TIMER_CHANNEL1;
sTIM_ChnInit.TIMER_CH_Mode = TIMER_CH_MODE_PWM;
sTIM_ChnInit.TIMER_CH_REF_Format = TIMER_CH_REF_Format3;
TIMER_ChnInit(MDR_TIMER1, &sTIM_ChnInit);
TIMER_SetChnCompare(MDR_TIMER1, TIMER_CHANNEL1, 0x100);
/* Initializes the TIMER1 Channel1 Output -------------------------------*/
TIMER_ChnOutStructInit(&sTIM_ChnOutInit);
sTIM_ChnOutInit.TIMER_CH_Number = TIMER_CHANNEL1;
sTIM_ChnOutInit.TIMER_CH_DirOut_Polarity = TIMER_CHOPolarity_NonInverted;
sTIM_ChnOutInit.TIMER_CH_DirOut_Source = TIMER_CH_OutSrc_REF;
sTIM_ChnOutInit.TIMER_CH_DirOut_Mode = TIMER_CH_OutMode_Output;
TIMER_ChnOutInit(MDR_TIMER1, &sTIM_ChnOutInit);
/* Initializes the TIMER1 Channel2 -------------------------------------*/
TIMER_ChnStructInit(&sTIM_ChnInit);
sTIM_ChnInit.TIMER_CH_Number = TIMER_CHANNEL2;
sTIM_ChnInit.TIMER_CH_Mode = TIMER_CH_MODE_CAPTURE;
TIMER_ChnInit(MDR_TIMER1, &sTIM_ChnInit);
/* Initializes the TIMER1 Channel2 Output -------------------------------*/
TIMER_ChnOutStructInit(&sTIM_ChnOutInit);
sTIM_ChnOutInit.TIMER_CH_Number = TIMER_CHANNEL2;
sTIM_ChnOutInit.TIMER_CH_DirOut_Polarity = TIMER_CHOPolarity_NonInverted;
sTIM_ChnOutInit.TIMER_CH_DirOut_Source = TIMER_CH_OutSrc_Only_0;
sTIM_ChnOutInit.TIMER_CH_DirOut_Mode = TIMER_CH_OutMode_Input;
TIMER_ChnOutInit(MDR_TIMER1, &sTIM_ChnOutInit);
/* Enable TIMER1 DMA request */
TIMER_DMACmd(MDR_TIMER1,(TIMER_STATUS_CCR_CAP_CH2), ENABLE);
/* Reset all DMA settings */
DMA_DeInit();
DMA_StructInit(&DMA_InitStr);
/* DMA_Channel_TIM1 configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)(&(MDR_TIMER1->CCR2));
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)DstBuf;
DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncNo;
DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncHalfword;
DMA_PriCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_PriCtrlStr.DMA_Mode = DMA_Mode_Basic;
DMA_PriCtrlStr.DMA_CycleSize = BufferSize;
DMA_PriCtrlStr.DMA_NumContinuous = DMA_Transfers_1;
DMA_PriCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged;
DMA_PriCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged;
/* Set Channel Structure */
DMA_InitStr.DMA_PriCtrlData = &DMA_PriCtrlStr;
DMA_InitStr.DMA_Priority = DMA_Priority_High;
DMA_InitStr.DMA_UseBurst = DMA_BurstClear;
DMA_InitStr.DMA_SelectDataStructure = DMA_CTRL_DATA_PRIMARY;
/* Init DMA channel */
DMA_Init(DMA_Channel_TIM1, &DMA_InitStr);
/* Enable TIMER1 */
TIMER_Cmd(MDR_TIMER1,ENABLE);
/* Transfer complete */
while((DMA_GetFlagStatus(DMA_Channel_TIM1, DMA_FLAG_CHNL_ENA)))
{
}
/* Check the corectness of written dada */
for(i = 0; i < BufferSize; i++)
{
if (DstBuf[i] != MDR_TIMER1->CCR1)
{
TransferStatus &= FAILED;
break;
}
else
{
TransferStatus = PASSED;
}
}
/* TransferStatus = PASSED, if the data transmitted are correct */
/* TransferStatus = FAILED, if the data transmitted are not correct */
while(1)
{
}
}
void main(void)
#endif
{
RST_CLK_DeInit();
RST_CLK_CPU_PLLconfig (RST_CLK_CPU_PLLsrcHSIdiv2,0);
/* Enable peripheral clocks --------------------------------------------------*/
RST_CLK_PCLKcmd((RST_CLK_PCLK_RST_CLK | RST_CLK_PCLK_SSP1 | RST_CLK_PCLK_SSP2 | RST_CLK_PCLK_DMA),ENABLE);
RST_CLK_PCLKcmd((RST_CLK_PCLK_PORTF | RST_CLK_PCLK_PORTD), ENABLE);
/* Init NVIC */
SCB->AIRCR = 0x05FA0000 | ((uint32_t)0x500);
SCB->VTOR = 0x08000000;
/* Disable all interrupt */
NVIC->ICPR[0] = 0xFFFFFFFF;
NVIC->ICER[0] = 0xFFFFFFFF;
/* Disable all DMA request */
MDR_DMA->CHNL_REQ_MASK_CLR = 0xFFFFFFFF;
MDR_DMA->CHNL_USEBURST_CLR = 0xFFFFFFFF;
/* Reset PORTD settings */
PORT_DeInit(MDR_PORTD);
/* Reset PORTF settings */
PORT_DeInit(MDR_PORTF);
/* Configure SSP2 pins: FSS, CLK, RXD, TXD */
/* Configure PORTD pins 2, 3, 5, 6 */
PORT_InitStructure.PORT_Pin = (PORT_Pin_2 | PORT_Pin_3 | PORT_Pin_5);
PORT_InitStructure.PORT_OE = PORT_OE_IN;
PORT_InitStructure.PORT_FUNC = PORT_FUNC_ALTER;
PORT_InitStructure.PORT_MODE = PORT_MODE_DIGITAL;
PORT_InitStructure.PORT_SPEED = PORT_SPEED_FAST;
PORT_Init(MDR_PORTD, &PORT_InitStructure);
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_InitStructure.PORT_Pin = (PORT_Pin_6);
PORT_Init(MDR_PORTD, &PORT_InitStructure);
/* Configure SSP1 pins: FSS, CLK, RXD, TXD */
/* Configure PORTF pins 0, 1, 2, 3 */
PORT_InitStructure.PORT_Pin = (PORT_Pin_3);
PORT_InitStructure.PORT_OE = PORT_OE_IN;
PORT_Init(MDR_PORTF, &PORT_InitStructure);
PORT_InitStructure.PORT_Pin = (PORT_Pin_0 | PORT_Pin_1 | PORT_Pin_2);
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_Init(MDR_PORTF, &PORT_InitStructure);
/* Init RAM */
Init_RAM (DstBuf1, BufferSize);
Init_RAM (SrcBuf1, BufferSize);
Init_RAM (DstBuf2, BufferSize);
Init_RAM (SrcBuf2, BufferSize);
/* Reset all SSP settings */
SSP_DeInit(MDR_SSP1);
SSP_DeInit(MDR_SSP2);
SSP_BRGInit(MDR_SSP1,SSP_HCLKdiv16);
SSP_BRGInit(MDR_SSP2,SSP_HCLKdiv16);
/* SSP1 MASTER configuration ------------------------------------------------*/
SSP_StructInit (&sSSP);
sSSP.SSP_SCR = 0x10;
sSSP.SSP_CPSDVSR = 2;
sSSP.SSP_Mode = SSP_ModeMaster;
sSSP.SSP_WordLength = SSP_WordLength16b;
sSSP.SSP_SPH = SSP_SPH_1Edge;
sSSP.SSP_SPO = SSP_SPO_Low;
sSSP.SSP_FRF = SSP_FRF_SPI_Motorola;
sSSP.SSP_HardwareFlowControl = SSP_HardwareFlowControl_SSE;
SSP_Init (MDR_SSP1,&sSSP);
/* SSP2 SLAVE configuration ------------------------------------------------*/
sSSP.SSP_SPH = SSP_SPH_1Edge;
sSSP.SSP_SPO = SSP_SPO_Low;
sSSP.SSP_CPSDVSR = 12;
sSSP.SSP_Mode = SSP_ModeSlave;
SSP_Init (MDR_SSP2,&sSSP);
/* Enable SSP1 DMA Rx and Tx request */
SSP_DMACmd(MDR_SSP1,(SSP_DMA_RXE | SSP_DMA_TXE), ENABLE);
/* Enable SSP2 DMA Rx and Tx request */
SSP_DMACmd(MDR_SSP2,(SSP_DMA_RXE | SSP_DMA_TXE), ENABLE);
/* Reset all DMA settings */
DMA_DeInit();
DMA_StructInit(&DMA_InitStr);
/* DMA_Channel_SSP1_RX configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)(&(MDR_SSP1->DR));
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)DstBuf1;
DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncNo;
DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncHalfword;
DMA_PriCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_PriCtrlStr.DMA_Mode = DMA_Mode_Basic;
DMA_PriCtrlStr.DMA_CycleSize = BufferSize;
DMA_PriCtrlStr.DMA_NumContinuous = DMA_Transfers_4;
DMA_PriCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged;
DMA_PriCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged;
/* Set Channel Structure */
DMA_InitStr.DMA_PriCtrlData = &DMA_PriCtrlStr;
DMA_InitStr.DMA_Priority = DMA_Priority_High;
DMA_InitStr.DMA_UseBurst = DMA_BurstClear;
DMA_InitStr.DMA_SelectDataStructure = DMA_CTRL_DATA_PRIMARY;
/* Init DMA channel */
DMA_Init(DMA_Channel_SSP1_RX, &DMA_InitStr);
/* DMA_Channel_SSP2_RX configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)(&(MDR_SSP2->DR));
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)DstBuf2;
/* Init DMA channel */
DMA_Init(DMA_Channel_SSP2_RX, &DMA_InitStr);
/* DMA_Channel_SSP1_TX configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)SrcBuf1;
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)(&(MDR_SSP1->DR));
DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncHalfword;
DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncNo;
DMA_InitStr.DMA_Priority = DMA_Priority_Default;
/* Init DMA channel */
DMA_Init(DMA_Channel_SSP1_TX, &DMA_InitStr);
/* DMA_Channel_SSP2_TX configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)SrcBuf2;
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)(&(MDR_SSP2->DR));
/* Init DMA channel */
DMA_Init(DMA_Channel_SSP2_TX, &DMA_InitStr);
/* Enable SSP1 */
SSP_Cmd(MDR_SSP1, ENABLE);
/* Enable SSP2 */
SSP_Cmd(MDR_SSP2, ENABLE);
/* Transfer complete */
while((SSP_GetFlagStatus(MDR_SSP1, SSP_FLAG_BSY)))
{
}
while((SSP_GetFlagStatus(MDR_SSP2, SSP_FLAG_BSY)))
{
}
/* Check the corectness of written dada */
TransferStatus1 = Verif_mem ((BufferSize), SrcBuf1, DstBuf2);
TransferStatus2 = Verif_mem ((BufferSize), SrcBuf2, DstBuf1);
/* TransferStatus1, TransferStatus2 = PASSED, if the data transmitted and received
are correct */
/* TransferStatus1, TransferStatus2 = FAILED, if the data transmitted and received
are different */
while(1)
{
}
}
void main(void)
#endif
{
RST_CLK_DeInit();
RST_CLK_CPU_PLLconfig(RST_CLK_CPU_PLLsrcHSIdiv2, 0);
/* Enable peripheral clocks --------------------------------------------------*/
RST_CLK_PCLKcmd(
(RST_CLK_PCLK_RST_CLK |
RST_CLK_PCLK_UART1 |
RST_CLK_PCLK_UART2 |
RST_CLK_PCLK_DMA),
ENABLE);
RST_CLK_PCLKcmd((RST_CLK_PCLK_PORTC | RST_CLK_PCLK_PORTD), ENABLE);
/* Disable all DMA request */
MDR_DMA ->CHNL_REQ_MASK_CLR = 0xFFFFFFFF;
MDR_DMA ->CHNL_USEBURST_CLR = 0xFFFFFFFF;
/* Reset PORTC settings */
PORT_DeInit(MDR_PORTC );
/* Reset PORTC settings */
PORT_DeInit(MDR_PORTD );
/* Configure UART1 pins: RXD, TXD */
/* Configure PORTB pins 3, 4 */
PORT_InitStructure.PORT_Pin = PORT_Pin_4;
PORT_InitStructure.PORT_OE = PORT_OE_IN;
PORT_InitStructure.PORT_FUNC = PORT_FUNC_MAIN;
PORT_InitStructure.PORT_MODE = PORT_MODE_DIGITAL;
PORT_InitStructure.PORT_SPEED = PORT_SPEED_FAST;
PORT_Init(MDR_PORTC, &PORT_InitStructure);
PORT_InitStructure.PORT_Pin = PORT_Pin_3;
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_Init(MDR_PORTC, &PORT_InitStructure);
/* Configure UART2 pins: RXD, TXD */
/* Configure PORTF pins 13, 14 */
PORT_InitStructure.PORT_Pin = PORT_Pin_14;
PORT_InitStructure.PORT_FUNC = PORT_FUNC_MAIN;
PORT_InitStructure.PORT_OE = PORT_OE_IN;
PORT_Init(MDR_PORTD, &PORT_InitStructure);
PORT_InitStructure.PORT_Pin = (PORT_Pin_13);
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_Init(MDR_PORTD, &PORT_InitStructure);
/* Init RAM */
Init_RAM(DstBuf1, BufferSize);
Init_RAM(SrcBuf1, BufferSize);
Init_RAM(DstBuf2, BufferSize);
Init_RAM(SrcBuf2, BufferSize);
/* Reset all UART settings */
UART_DeInit(MDR_UART1 );
UART_DeInit(MDR_UART2 );
UART_BRGInit(MDR_UART1, UART_HCLKdiv1 );
UART_BRGInit(MDR_UART2, UART_HCLKdiv1 );
/* UART1 configuration ------------------------------------------------*/
UART_StructInit(&sUART);
sUART.UART_BaudRate = 1200;
sUART.UART_WordLength = UART_WordLength8b;
sUART.UART_StopBits = UART_StopBits1;
sUART.UART_Parity = UART_Parity_No;
sUART.UART_FIFOMode = UART_FIFO_ON;
sUART.UART_HardwareFlowControl = (UART_HardwareFlowControl_RXE
| UART_HardwareFlowControl_TXE );
UART_Init(MDR_UART1, &sUART);
UART_DMAConfig( MDR_UART1,
UART_IT_FIFO_LVL_8words,
UART_IT_FIFO_LVL_8words );
/* UART2 configuration ------------------------------------------------*/
UART_Init(MDR_UART2, &sUART);
UART_DMAConfig(MDR_UART2,
UART_IT_FIFO_LVL_8words,
UART_IT_FIFO_LVL_8words );
/* Enable UART1 DMA Rx and Tx request */
UART_DMACmd(MDR_UART1, (UART_DMA_RXE | UART_DMA_TXE ), ENABLE);
/* Enable UART2 DMA Rx and Tx request */
UART_DMACmd(MDR_UART2, (UART_DMA_RXE | UART_DMA_TXE ), ENABLE);
/* Reset all DMA settings */
DMA_DeInit();
DMA_StructInit(&DMA_InitStr);
/* DMA_Channel_UART1_RX configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t) (&(MDR_UART1 ->DR));
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t) DstBuf1;
DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncNo;
DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncByte;
DMA_PriCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_PriCtrlStr.DMA_Mode = DMA_Mode_Basic;
DMA_PriCtrlStr.DMA_CycleSize = BufferSize;
DMA_PriCtrlStr.DMA_NumContinuous = DMA_Transfers_8;
DMA_PriCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged;
DMA_PriCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged;
/* Set Channel Structure */
DMA_InitStr.DMA_PriCtrlData = &DMA_PriCtrlStr;
DMA_InitStr.DMA_Priority = DMA_Priority_High;
DMA_InitStr.DMA_UseBurst = DMA_BurstClear;
DMA_InitStr.DMA_SelectDataStructure = DMA_CTRL_DATA_PRIMARY;
/* Init DMA channel */
DMA_Init(DMA_Channel_REQ_UART1_RX, &DMA_InitStr);
/* DMA_Channel_UART2_RX configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t) (&(MDR_UART2 ->DR));
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t) DstBuf2;
/* Init DMA channel */
DMA_Init(DMA_Channel_REQ_UART2_RX, &DMA_InitStr);
/* DMA_Channel_UART1_TX configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t) SrcBuf1;
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t) (&(MDR_UART1 ->DR));
DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncByte;
DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncNo;
DMA_InitStr.DMA_Priority = DMA_Priority_Default;
/* Init DMA channel */
DMA_Init(DMA_Channel_REQ_UART1_TX, &DMA_InitStr);
/* DMA_Channel_UART2_TX configuration ---------------------------------*/
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t) SrcBuf2;
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t) (&(MDR_UART2 ->DR));
/* Init DMA channel */
DMA_Init(DMA_Channel_REQ_UART2_TX, &DMA_InitStr);
/* Enable UART1 */
UART_Cmd(MDR_UART1, ENABLE);
/* Enable UART2 */
UART_Cmd(MDR_UART2, ENABLE);
/* Transfer complete */
while ((DMA_GetFlagStatus(DMA_Channel_REQ_UART1_TX, DMA_FLAG_CHNL_ENA )));
while ((DMA_GetFlagStatus(DMA_Channel_REQ_UART1_RX, DMA_FLAG_CHNL_ENA )));
while ((DMA_GetFlagStatus(DMA_Channel_REQ_UART2_TX, DMA_FLAG_CHNL_ENA )));
while ((DMA_GetFlagStatus(DMA_Channel_REQ_UART2_RX, DMA_FLAG_CHNL_ENA )));
/* Check the corectness of written dada */
TransferStatus1 = Verif_mem((BufferSize / 2), SrcBuf1, DstBuf2);
TransferStatus2 = Verif_mem((BufferSize / 2), SrcBuf2, DstBuf1);
/* TransferStatus1, TransferStatus2 = PASSED, if the data transmitted and received
are correct */
/* TransferStatus1, TransferStatus2 = FAILED, if the data transmitted and received
are different */
while (1);
}
void main(void)
#endif
{
RST_CLK_DeInit();
RST_CLK_CPU_PLLconfig (RST_CLK_CPU_PLLsrcHSIdiv2,0);
/* Enable peripheral clocks --------------------------------------------------*/
RST_CLK_PCLKcmd((RST_CLK_PCLK_RST_CLK | RST_CLK_PCLK_DMA | RST_CLK_PCLK_ADC),ENABLE);
RST_CLK_PCLKcmd((RST_CLK_PCLK_SSP1 | RST_CLK_PCLK_SSP2),ENABLE);
/* Disable all interrupt */
NVIC->ICPR[0] = 0xFFFFFFFF;
NVIC->ICER[0] = 0xFFFFFFFF;
/* DMA Configuration */
/* Reset all settings */
DMA_DeInit();
DMA_StructInit(&DMA_InitStr);
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)(&(MDR_ADC->ADC1_RESULT));
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)ADCConvertedValue;
DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncNo;
DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncHalfword;
DMA_PriCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_PriCtrlStr.DMA_Mode = DMA_Mode_PingPong;
DMA_PriCtrlStr.DMA_CycleSize = 10;
DMA_PriCtrlStr.DMA_NumContinuous = DMA_Transfers_1;
DMA_PriCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged;
DMA_PriCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged;
/* Set Alternate Control Data */
DMA_AltCtrlStr.DMA_SourceBaseAddr = (uint32_t)(&(MDR_ADC->ADC1_RESULT));
DMA_AltCtrlStr.DMA_DestBaseAddr = (uint32_t)ADCConvertedValue;
DMA_AltCtrlStr.DMA_SourceIncSize = DMA_SourceIncNo;
DMA_AltCtrlStr.DMA_DestIncSize = DMA_DestIncHalfword;
DMA_AltCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_AltCtrlStr.DMA_Mode = DMA_Mode_PingPong;
DMA_AltCtrlStr.DMA_CycleSize = 10;
DMA_AltCtrlStr.DMA_NumContinuous = DMA_Transfers_1;
DMA_AltCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged;
DMA_AltCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged;
/* Set Channel Structure */
DMA_InitStr.DMA_PriCtrlData = &DMA_PriCtrlStr;
DMA_InitStr.DMA_AltCtrlData = &DMA_AltCtrlStr;
DMA_InitStr.DMA_Priority = DMA_Priority_Default;
DMA_InitStr.DMA_UseBurst = DMA_BurstClear;
DMA_InitStr.DMA_SelectDataStructure = DMA_CTRL_DATA_PRIMARY;
/* Init DMA channel ADC1 */
DMA_Init(DMA_Channel_ADC1, &DMA_InitStr);
/* Enable dma_req or dma_sreq to generate DMA request */
MDR_DMA->CHNL_REQ_MASK_CLR = (1<<DMA_Channel_ADC1);
MDR_DMA->CHNL_USEBURST_CLR = (1<<DMA_Channel_ADC1);
/* Enable DMA channel ADC1 */
DMA_Cmd(DMA_Channel_ADC1, ENABLE);
/* ADC Configuration */
/* Reset all ADC settings */
ADC_DeInit();
ADC_StructInit(&sADC);
sADC.ADC_SynchronousMode = ADC_SyncMode_Independent;
sADC.ADC_StartDelay = 0;
sADC.ADC_TempSensor = ADC_TEMP_SENSOR_Enable;
sADC.ADC_TempSensorAmplifier = ADC_TEMP_SENSOR_AMPLIFIER_Enable;
sADC.ADC_TempSensorConversion = ADC_TEMP_SENSOR_CONVERSION_Enable;
sADC.ADC_IntVRefConversion = ADC_VREF_CONVERSION_Disable;
sADC.ADC_IntVRefTrimming = 1;
ADC_Init (&sADC);
/* ADC1 Configuration */
ADCx_StructInit (&sADCx);
sADCx.ADC_ClockSource = ADC_CLOCK_SOURCE_CPU;
sADCx.ADC_SamplingMode = ADC_SAMPLING_MODE_CICLIC_CONV;
sADCx.ADC_ChannelSwitching = ADC_CH_SWITCHING_Disable;
sADCx.ADC_ChannelNumber = ADC_CH_TEMP_SENSOR;
sADCx.ADC_Channels = 0;
sADCx.ADC_LevelControl = ADC_LEVEL_CONTROL_Disable;
sADCx.ADC_LowLevel = 0;
sADCx.ADC_HighLevel = 0;
sADCx.ADC_VRefSource = ADC_VREF_SOURCE_INTERNAL;
sADCx.ADC_IntVRefSource = ADC_INT_VREF_SOURCE_INEXACT;
sADCx.ADC_Prescaler = ADC_CLK_div_512;
sADCx.ADC_DelayGo = 7;
ADC1_Init (&sADCx);
/* Enable ADC1 EOCIF and AWOIFEN interupts */
ADC1_ITConfig((ADCx_IT_END_OF_CONVERSION | ADCx_IT_OUT_OF_RANGE), DISABLE);
/* ADC1 enable */
ADC1_Cmd (ENABLE);
/* Enable DMA IRQ */
NVIC_EnableIRQ(DMA_IRQn);
while(1);
}
void main(void)
#endif
{
RST_CLK_PCLKcmd(RST_CLK_PCLK_PORTD, ENABLE);
/* Configure all unused PORT pins to low power consumption */
PORT_StructInit(&PORT_InitStructure);
PORT_InitStructure.PORT_Pin = (PORT_Pin_All & ~(PORT_Pin_10 | PORT_Pin_11 |
PORT_Pin_12 | PORT_Pin_13 |
PORT_Pin_14));
PORT_Init(MDR_PORTD, &PORT_InitStructure);
/* Configure PORTD pins 10..14 for output to switch LEDs on/off */
PORT_InitStructure.PORT_Pin = (PORT_Pin_10 | PORT_Pin_11 | PORT_Pin_12 |
PORT_Pin_13 | PORT_Pin_14);
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_InitStructure.PORT_FUNC = PORT_FUNC_PORT;
PORT_InitStructure.PORT_MODE = PORT_MODE_DIGITAL;
PORT_InitStructure.PORT_SPEED = PORT_SPEED_SLOW;
PORT_Init(MDR_PORTD, &PORT_InitStructure);
/* Consequently turn all three used LEDs on and off */
LEDOn(LED1);
Delay(4*BLINK_DELAY);
LEDOff(LED1);
Delay(4*BLINK_DELAY);
LEDOn(LED2);
Delay(4*BLINK_DELAY);
LEDOff(LED2);
Delay(4*BLINK_DELAY);
LEDOn(LED3);
Delay(4*BLINK_DELAY);
LEDOff(LED3);
Delay(4*BLINK_DELAY);
/* Infinite loop that demonstrates different input clock sources using */
while (1)
{
/* Set RST_CLK to default */
RST_CLK_DeInit();
RST_CLK_PCLKcmd(RST_CLK_PCLK_PORTD, ENABLE);
/* 1. CPU_CLK = HSI clock */
/* Enable HSI clock source */
RST_CLK_HSIcmd(ENABLE);
/* Switch LED2 on and wait for HSI ready status */
LEDOn(LED2);
Delay(BLINK_DELAY);
if (RST_CLK_HSIstatus() == SUCCESS) /* Good HSI clock */
{
/* Switch LED2 off */
LEDOff(LED2);
/* Select HSI clock on the CPU clock MUX */
RST_CLK_CPUclkSelection(RST_CLK_CPUclkHSI);
/* LED1 blinking with HSI clock as input clock source */
BlinkLED1(BLINK_NUM, BLINK_DELAY);
}
else /* HSI timeout */
{
IndicateError();
}
/* 2. CPU_CLK = HSI/2 clock */
/* Enable HSI clock source */
RST_CLK_HSIcmd(ENABLE);
/* Disable CPU_PLL */
RST_CLK_CPU_PLLcmd(DISABLE);
/* Select HSI/2 clock as CPU_PLL input clock source */
RST_CLK_CPU_PLLconfig(RST_CLK_CPU_PLLsrcHSIdiv2, 1);
/* Switch LED2 on and wait for HSI ready status */
LEDOn(LED2);
Delay(BLINK_DELAY);
if (RST_CLK_HSIstatus() == SUCCESS) /* Good HSI clock */
{
/* Switch LED2 off */
LEDOff(LED2);
/* Set CPU_C3_prescaler to 1 */
RST_CLK_CPUclkPrescaler(RST_CLK_CPUclkDIV1);
/* Switch CPU_C2_SEL to CPU_C1 clock instead of CPU_PLL output */
RST_CLK_CPU_PLLuse(DISABLE);
/* LED1 blinking with HSI/2 clock as input clock source */
BlinkLED1(BLINK_NUM, BLINK_DELAY);
}
else /* HSI timeout */
{
IndicateError();
}
/* 3. CPU_CLK = 7*HSE/2 clock */
/* Enable HSE clock oscillator */
RST_CLK_HSEconfig(RST_CLK_HSE_ON);
/* Switch LED2 on and wait for HSE ready status */
LEDOn(LED2);
Delay(BLINK_DELAY);
if (RST_CLK_HSEstatus() == SUCCESS) /* Good HSE clock */
{
/* Select HSE clock as CPU_PLL input clock source */
/* Set PLL multiplier to 7 */
RST_CLK_CPU_PLLconfig(RST_CLK_CPU_PLLsrcHSEdiv1, 7);
/* Enable CPU_PLL */
RST_CLK_CPU_PLLcmd(ENABLE);
/* Switch LED2 on and wait for PLL ready status */
if (RST_CLK_HSEstatus() == SUCCESS) /* Good CPU PLL */
{
/* Switch LED2 off */
LEDOff(LED2);
/* Set CPU_C3_prescaler to 2 */
RST_CLK_CPUclkPrescaler(RST_CLK_CPUclkDIV2);
/* Set CPU_C2_SEL to CPU_PLL output instead of CPU_C1 clock */
RST_CLK_CPU_PLLuse(ENABLE);
/* Select CPU_C3 clock on the CPU clock MUX */
RST_CLK_CPUclkSelection(RST_CLK_CPUclkCPU_C3);
/* LED1 blinking with 7*HSE/2 clock as input clock source */
BlinkLED1(BLINK_NUM, BLINK_DELAY);
}
else /* CPU_PLL timeout */
{
IndicateError();
}
}
else /* HSE timeout */
{
IndicateError();
}
/* 4. CPU_CLK = LSI clock */
/* Enable LSI clock source */
RST_CLK_LSIcmd(ENABLE);
/* Switch LED2 on and wait for LSI ready status */
LEDOn(LED2);
Delay(BLINK_DELAY);
if (RST_CLK_LSIstatus() == SUCCESS) /* Good LSI clock */
{
/* Switch LED2 off */
LEDOff(LED2);
/* Select LSI clock on the CPU clock MUX */
RST_CLK_CPUclkSelection(RST_CLK_CPUclkLSI);
/* LED1 blinking with LSI clock as input clock source */
BlinkLED1(BLINK_NUM, BLINK_DELAY);
}
else /* LSI timeout */
{
IndicateError();
}
}
}
/**
* @brief Main program.
* @param None
* @retval None
*/
int main (void)
{
uint8_t DataByte=0x01;
static uint8_t ReciveByte[16];
uint32_t i;
/* Enables the HSI clock on PORTB,PORTD */
RST_CLK_PCLKcmd(RST_CLK_PCLK_PORTB,ENABLE);
RST_CLK_PCLKcmd(RST_CLK_PCLK_PORTD,ENABLE);
/* Fill PortInit structure*/
PortInit.PORT_PULL_UP = PORT_PULL_UP_OFF;
PortInit.PORT_PULL_DOWN = PORT_PULL_DOWN_OFF;
PortInit.PORT_PD_SHM = PORT_PD_SHM_OFF;
PortInit.PORT_PD = PORT_PD_DRIVER;
PortInit.PORT_GFEN = PORT_GFEN_OFF;
PortInit.PORT_FUNC = PORT_FUNC_ALTER;
PortInit.PORT_SPEED = PORT_SPEED_MAXFAST;
PortInit.PORT_MODE = PORT_MODE_DIGITAL;
/* Configure PORTB pins 5 (UART1_TX) as output */
PortInit.PORT_OE = PORT_OE_OUT;
PortInit.PORT_Pin = PORT_Pin_5;
PORT_Init(MDR_PORTB, &PortInit);
/* Configure PORTB pins 6 (UART1_RX) as input */
PortInit.PORT_OE = PORT_OE_IN;
PortInit.PORT_Pin = PORT_Pin_6;
PORT_Init(MDR_PORTB, &PortInit);
/* Configure PORTD pins 1 (UART2_TX) as output */
PortInit.PORT_OE = PORT_OE_OUT;
PortInit.PORT_Pin = PORT_Pin_1;
PORT_Init(MDR_PORTD, &PortInit);
/* Configure PORTD pins 0 (UART1_RX) as input */
PortInit.PORT_OE = PORT_OE_IN;
PortInit.PORT_Pin = PORT_Pin_0;
PORT_Init(MDR_PORTD, &PortInit);
/* Select HSI/2 as CPU_CLK source*/
RST_CLK_CPU_PLLconfig (RST_CLK_CPU_PLLsrcHSIdiv2,0);
/* Enables the CPU_CLK clock on UART1,UART2 */
RST_CLK_PCLKcmd(RST_CLK_PCLK_UART1, ENABLE);
RST_CLK_PCLKcmd(RST_CLK_PCLK_UART2, ENABLE);
/* Set the HCLK division factor = 1 for UART1,UART2*/
UART_BRGInit(MDR_UART1, UART_HCLKdiv1);
UART_BRGInit(MDR_UART2, UART_HCLKdiv1);
/* Initialize UART_InitStructure */
UART_InitStructure.UART_BaudRate = 115000;
UART_InitStructure.UART_WordLength = UART_WordLength8b;
UART_InitStructure.UART_StopBits = UART_StopBits1;
UART_InitStructure.UART_Parity = UART_Parity_No;
UART_InitStructure.UART_FIFOMode = UART_FIFO_ON;
UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_RXE | UART_HardwareFlowControl_TXE;
/* Configure UART1 parameters*/
UART_Init (MDR_UART1,&UART_InitStructure);
/* Configure DMA for UART1*/
UART_DMAConfig (MDR_UART1, UART_IT_FIFO_LVL_12words, UART_IT_FIFO_LVL_12words);
UART_DMACmd(MDR_UART1, UART_DMA_TXE | UART_DMA_RXE | UART_DMA_ONERR, ENABLE);
/* Enables UART1 peripheral */
UART_Cmd(MDR_UART1,ENABLE);
/* Configure UART2 parameters*/
UART_Init (MDR_UART2,&UART_InitStructure);
/* Configure DMA for UART2*/
UART_DMAConfig (MDR_UART2, UART_IT_FIFO_LVL_12words, UART_IT_FIFO_LVL_12words);
UART_DMACmd(MDR_UART2, UART_DMA_TXE | UART_DMA_RXE | UART_DMA_ONERR, ENABLE);
/* Enables UART2 peripheral */
UART_Cmd(MDR_UART2,ENABLE);
while (1)
{
/* Check TXFE flag */
while (UART_GetFlagStatus (MDR_UART1, UART_FLAG_TXFE)!= SET)
{
}
/* Send Data from UART1 */
for (i=0;i<16;i++)
{
UART_SendData (MDR_UART1, (uint16_t)(i+16*DataByte));
}
/* Check RXFF flag */
while (UART_GetFlagStatus (MDR_UART2, UART_FLAG_RXFF)!= SET)
{
}
/* Recive data */
for (i=0;i<16;i++)
{
ReciveByte[i] = UART_ReceiveData (MDR_UART2);
}
/* Increment Data */
DataByte++;
}
}
void main(void)
#endif
{
RST_CLK_DeInit();
RST_CLK_CPU_PLLconfig (RST_CLK_CPU_PLLsrcHSIdiv2,0);
/* Enable peripheral clocks --------------------------------------------------*/
RST_CLK_PCLKcmd((RST_CLK_PCLK_RST_CLK | RST_CLK_PCLK_DMA | RST_CLK_PCLK_PORTE),ENABLE);
RST_CLK_PCLKcmd((RST_CLK_PCLK_TIMER1 | RST_CLK_PCLK_DAC),ENABLE);
RST_CLK_PCLKcmd((RST_CLK_PCLK_SSP1 | RST_CLK_PCLK_SSP2),ENABLE);
/* Disable all interrupt */
NVIC->ICPR[0] = 0xFFFFFFFF;
NVIC->ICER[0] = 0xFFFFFFFF;
/* Reset PORTE settings */
PORT_DeInit(MDR_PORTE);
/* Configure DAC pin: DAC1_OUT */
/* Configure PORTE pin 9 */
PORT_InitStructure.PORT_Pin = PORT_Pin_2;
PORT_InitStructure.PORT_OE = PORT_OE_OUT;
PORT_InitStructure.PORT_MODE = PORT_MODE_ANALOG;
PORT_Init(MDR_PORTE, &PORT_InitStructure);
/* DMA Configuration */
/* Reset all DMA settings */
DMA_DeInit();
DMA_StructInit(&DMA_InitStr);
/* Set Primary Control Data */
DMA_PriCtrlStr.DMA_SourceBaseAddr = (uint32_t)Sine12bit;
DMA_PriCtrlStr.DMA_DestBaseAddr = (uint32_t)(&(MDR_DAC->DAC1_DATA));
DMA_PriCtrlStr.DMA_SourceIncSize = DMA_SourceIncHalfword;
DMA_PriCtrlStr.DMA_DestIncSize = DMA_DestIncNo;
DMA_PriCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_PriCtrlStr.DMA_Mode = DMA_Mode_PingPong;
DMA_PriCtrlStr.DMA_CycleSize = 32;
DMA_PriCtrlStr.DMA_NumContinuous = DMA_Transfers_1;
DMA_PriCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged;
DMA_PriCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged;
/* Set Alternate Control Data */
DMA_AltCtrlStr.DMA_SourceBaseAddr = (uint32_t)Sine12bit;
DMA_AltCtrlStr.DMA_DestBaseAddr = (uint32_t)(&(MDR_DAC->DAC1_DATA));
DMA_AltCtrlStr.DMA_SourceIncSize = DMA_SourceIncHalfword;
DMA_AltCtrlStr.DMA_DestIncSize = DMA_DestIncNo;
DMA_AltCtrlStr.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_AltCtrlStr.DMA_Mode = DMA_Mode_PingPong;
DMA_AltCtrlStr.DMA_CycleSize = 32;
DMA_AltCtrlStr.DMA_NumContinuous = DMA_Transfers_1;
DMA_AltCtrlStr.DMA_SourceProtCtrl = DMA_SourcePrivileged;
DMA_AltCtrlStr.DMA_DestProtCtrl = DMA_DestPrivileged;
/* Set Channel Structure */
DMA_InitStr.DMA_PriCtrlData = &DMA_PriCtrlStr;
DMA_InitStr.DMA_AltCtrlData = &DMA_AltCtrlStr;
DMA_InitStr.DMA_Priority = DMA_Priority_Default;
DMA_InitStr.DMA_UseBurst = DMA_BurstClear;
DMA_InitStr.DMA_SelectDataStructure = DMA_CTRL_DATA_PRIMARY;
/* Init DMA channel TIM1*/
DMA_Init(DMA_Channel_REQ_TIM1, &DMA_InitStr);
/* Enable dma_req or dma_sreq to generate DMA request */
MDR_DMA->CHNL_REQ_MASK_CLR = DMA_SELECT(DMA_Channel_REQ_TIM1);
MDR_DMA->CHNL_USEBURST_CLR = DMA_SELECT(DMA_Channel_REQ_TIM1);
/* Enable DMA_Channel_TIM1 */
DMA_Cmd(DMA_Channel_REQ_TIM1, ENABLE);
/* ADC Configuration */
/* Reset all ADC settings */
DAC_DeInit();
/* DAC channel1 Configuration */
DAC1_Init(DAC1_AVCC);
/* DAC channel1 enable */
DAC1_Cmd(ENABLE);
/* TIMER1 Configuration */
/* Time base configuration */
TIMER_DeInit(MDR_TIMER1);
TIMER_BRGInit(MDR_TIMER1,TIMER_HCLKdiv1);
sTIM_CntInit.TIMER_Prescaler = 0;
sTIM_CntInit.TIMER_Period = 0xFF;
sTIM_CntInit.TIMER_CounterMode = TIMER_CntMode_ClkFixedDir;
sTIM_CntInit.TIMER_CounterDirection = TIMER_CntDir_Up;
sTIM_CntInit.TIMER_EventSource = TIMER_EvSrc_None;
sTIM_CntInit.TIMER_FilterSampling = TIMER_FDTS_TIMER_CLK_div_1;
sTIM_CntInit.TIMER_ARR_UpdateMode = TIMER_ARR_Update_Immediately;
sTIM_CntInit.TIMER_ETR_FilterConf = TIMER_Filter_1FF_at_TIMER_CLK;
sTIM_CntInit.TIMER_ETR_Prescaler = TIMER_ETR_Prescaler_None;
sTIM_CntInit.TIMER_ETR_Polarity = TIMER_ETRPolarity_NonInverted;
sTIM_CntInit.TIMER_BRK_Polarity = TIMER_BRKPolarity_NonInverted;
TIMER_CntInit (MDR_TIMER1,&sTIM_CntInit);
/* Enable DMA for TIMER1 */
TIMER_DMACmd(MDR_TIMER1, TIMER_STATUS_CNT_ARR, TIMER_DMA_Channel0, ENABLE);
/* TIMER1 enable counter */
TIMER_Cmd(MDR_TIMER1,ENABLE);
/* Enable DMA IRQ */
NVIC_EnableIRQ(DMA_IRQn);
/* Infinite loop */
while(1)
{
}
}
