RTDECL(void) RTThreadPreemptRestore(PRTTHREADPREEMPTSTATE pState) { AssertPtr(pState); Assert(pState->u32Reserved == 42); pState->u32Reserved = 0; RT_ASSERT_PREEMPT_CPUID_RESTORE(pState); RTCPUID idCpu = RTMpCpuId(); if (RT_UNLIKELY(idCpu < RT_ELEMENTS(g_aPreemptHacks))) { Assert(g_aPreemptHacks[idCpu].cRecursion > 0); if (--g_aPreemptHacks[idCpu].cRecursion == 0) { lck_spin_t *pSpinLock = g_aPreemptHacks[idCpu].pSpinLock; if (pSpinLock) { IPRT_DARWIN_SAVE_EFL_AC(); lck_spin_unlock(pSpinLock); IPRT_DARWIN_RESTORE_EFL_AC(); } else AssertFailed(); } } }
RTDECL(void) RTThreadPreemptRestore(PRTTHREADPREEMPTSTATE pState) { AssertPtr(pState); RT_ASSERT_PREEMPT_CPUID_RESTORE(pState); KeLowerIrql(pState->uchOldIrql); pState->uchOldIrql = 255; }
RTDECL(void) RTThreadPreemptRestore(PRTTHREADPREEMPTSTATE pState) { AssertPtr(pState); RT_ASSERT_PREEMPT_CPUID_RESTORE(pState); restore_interrupts((cpu_status)pState->uOldCpuState); pState->uOldCpuState = 0; }
RTDECL(void) RTThreadPreemptRestore(PRTTHREADPREEMPTSTATE pState) { AssertPtr(pState); Assert(pState->u32Reserved == 42); pState->u32Reserved = 0; RT_ASSERT_PREEMPT_CPUID_RESTORE(pState); critical_exit(); }
RTDECL(void) RTThreadPreemptRestore(PRTTHREADPREEMPTSTATE pState) { AssertPtr(pState); //dprintf("%s(%p)\n", __FUNCTION__, pState); RT_ASSERT_PREEMPT_CPUID_RESTORE(pState); //RELEASE_THREAD_LOCK(); restore_interrupts((cpu_status)pState->uOldCpuState); pState->uOldCpuState = 0; }
RTDECL(void) RTThreadPreemptRestore(PRTTHREADPREEMPTSTATE pState) { AssertPtr(pState); AssertMsg(pState->u32Reserved > 0 && pState->u32Reserved < 32, ("%d\n", pState->u32Reserved)); RT_ASSERT_PREEMPT_CPUID_RESTORE(pState); /* No preemption on OS/2, so do our own accounting. */ int32_t volatile *pc = &g_acPreemptDisabled[ASMGetApicId()]; AssertMsg(pState->u32Reserved == (uint32_t)*pc, ("uchDummy=%d *pc=%d \n", pState->u32Reserved, *pc)); ASMAtomicUoWriteS32(pc, pState->u32Reserved - 1); pState->u32Reserved = 0; }
RTDECL(void) RTThreadPreemptRestore(PRTTHREADPREEMPTSTATE pState) { #ifdef CONFIG_PREEMPT AssertPtr(pState); Assert(pState->u32Reserved == 42); RT_ASSERT_PREEMPT_CPUID_RESTORE(pState); preempt_enable(); #else int32_t volatile *pc; AssertPtr(pState); AssertMsg(pState->u32Reserved > 0 && pState->u32Reserved < 32, ("%d\n", pState->u32Reserved)); RT_ASSERT_PREEMPT_CPUID_RESTORE(pState); /* Do our own accounting. */ pc = &g_acPreemptDisabled[smp_processor_id()]; AssertMsg(pState->u32Reserved == (uint32_t)*pc, ("u32Reserved=%d *pc=%d \n", pState->u32Reserved, *pc)); ASMAtomicUoWriteS32(pc, pState->u32Reserved - 1); #endif pState->u32Reserved = 0; }