/*******************************************************************************
* Function Name: usb0_host_CtrlReadStart
* Description : Executes USB control transfer/data stage(read).
* Arguments : uint32_t Bsize ; Data Size
* : uint8_t *Table ; Data Table Address
* Return Value : none
*******************************************************************************/
void usb0_host_CtrlReadStart (uint32_t Bsize, uint8_t * Table)
{
uint16_t mbw;
g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
usb0_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */
g_usb0_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */
g_usb0_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */
USB200.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */
#if(1) /* ohci_wrapp */
Userdef_USB_usb0_host_delay_10us(3);
#endif
RZA_IO_RegWrite_16(&USB200.DCPCFG,
0,
USB_DCPCFG_DIR_SHIFT,
USB_DCPCFG_DIR);
mbw = usb0_host_get_mbw(g_usb0_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb0_host_data_pointer[USB_HOST_PIPE0]);
usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, mbw);
USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
usb0_host_enable_brdy_int(USB_HOST_PIPE0); /* Ok */
usb0_host_clear_pid_stall(USB_HOST_PIPE0);
usb0_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */
}
/*******************************************************************************
* Function Name: usb1_function_USB_FUNCTION_Detach
* Description : Disconnects from the USB host controller.
* : This function opens D+/D-.
* Arguments : none
* Return Value : none
*******************************************************************************/
void usb1_function_USB_FUNCTION_Detach (void)
{
uint16_t pipe;
Userdef_USB_usb1_function_detach();
for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe)
{
if (g_usb1_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_IDLE)
{
usb1_function_stop_transfer(pipe);
}
}
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
0,
USB_SYSCFG_DPRPU_SHIFT,
USB_SYSCFG_DPRPU); /* open D+ and D- */
/* Detach Recovery */
Userdef_USB_usb1_function_delay_500ns(); /* need 1us=500ns * 2 wait */
Userdef_USB_usb1_function_delay_500ns();
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
1,
USB_SYSCFG_DCFM_SHIFT,
USB_SYSCFG_DCFM);
Userdef_USB_usb1_function_delay_500ns(); /* need 100ns wait but 500ns S/W wait */
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
0,
USB_SYSCFG_DCFM_SHIFT,
USB_SYSCFG_DCFM);
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
0,
USB_SYSCFG_USBE_SHIFT,
USB_SYSCFG_USBE); /* soft reset module */
Userdef_USB_usb1_function_delay_500ns();
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
1,
USB_SYSCFG_USBE_SHIFT,
USB_SYSCFG_USBE);
usb1_function_EnableINTModule(); /* Interrupt Enable */
}
/*******************************************************************************
* Function Name: usb1_function_USB_FUNCTION_Attach
* Description : Connects to the USB host controller.
* : This function pulls up D+.
* Arguments : none
* Return Value : none
*******************************************************************************/
void usb1_function_USB_FUNCTION_Attach (void)
{
Userdef_USB_usb1_function_attach();
Userdef_USB_usb1_function_delay_xms(10);
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
1,
USB_SYSCFG_DPRPU_SHIFT,
USB_SYSCFG_DPRPU); /* Pull-up D+ and open D- */
}
/*******************************************************************************
* Function Name: usb1_function_InitModule
* Description : Initializes the USB module in the USB function mode.
* Arguments : uint16_t mode ; USB_FUNCTION_HIGH_SPEED ; Hi-Speed Mode
* : ; other ; Full-speed Mode
* Return Value : none
*******************************************************************************/
void usb1_function_InitModule (uint16_t mode)
{
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
0,
USB_SYSCFG_DCFM_SHIFT,
USB_SYSCFG_DCFM); /* USB function */
/* USB module operation enabled */
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
1,
USB_SYSCFG_USBE_SHIFT,
USB_SYSCFG_USBE);
if (mode == USB_FUNCTION_HIGH_SPEED)
{
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
1,
USB_SYSCFG_HSE_SHIFT,
USB_SYSCFG_HSE); /* Hi-Speed Mode */
}
else
{
RZA_IO_RegWrite_16(&USB201.SYSCFG0,
0,
USB_SYSCFG_HSE_SHIFT,
USB_SYSCFG_HSE);
}
/* for power-on */
if (usb1_function_CheckVBUStaus() == DEVDRV_USBF_ON)
{
usb1_function_EnableINTModule(); /* Interrupt Enable */
usb1_function_USB_FUNCTION_Attach(); /* pull-up D+ and open D- */
}
else
{
usb1_function_USB_FUNCTION_Detach(); /* USB Detach */
/* with Interrupt Enable */
}
}
/*******************************************************************************
* Function Name: usb0_host_CtrlWriteStart
* Description : Executes USB control transfer/data stage(write).
* Arguments : uint32_t Bsize ; Data Size
* : uint8_t *Table ; Data Table Address
* Return Value : USB_HOST_WRITESHRT ; End of data write
* : USB_HOST_WRITEEND ; End of data write (not null)
* : USB_HOST_WRITING ; Continue of data write
* : USB_HOST_FIFOERROR ; FIFO access error
*******************************************************************************/
uint16_t usb0_host_CtrlWriteStart (uint32_t Bsize, uint8_t * Table)
{
uint16_t EndFlag_K;
uint16_t mbw;
g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
usb0_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */
g_usb0_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */
g_usb0_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */
USB200.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */
#if(1) /* ohci_wrapp */
Userdef_USB_usb0_host_delay_10us(3);
#endif
RZA_IO_RegWrite_16(&USB200.DCPCFG,
1,
USB_DCPCFG_DIR_SHIFT,
USB_DCPCFG_DIR);
mbw = usb0_host_get_mbw(g_usb0_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb0_host_data_pointer[USB_HOST_PIPE0]);
usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_BITISEL, mbw);
USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
usb0_host_clear_pid_stall(USB_HOST_PIPE0);
EndFlag_K = usb0_host_write_buffer_c(USB_HOST_PIPE0);
/* Host Control sequence */
switch (EndFlag_K)
{
case USB_HOST_WRITESHRT: /* End of data write */
g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
usb0_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */
break;
case USB_HOST_WRITEEND: /* End of data write (not null) */
case USB_HOST_WRITING: /* Continue of data write */
usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
usb0_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */
break;
case USB_HOST_FIFOERROR: /* FIFO access error */
break;
default:
break;
}
usb0_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */
return (EndFlag_K); /* End or Err or Continue */
}
/*******************************************************************************
* Function Name: usb0_function_dma_stop_d0
* Description : D0FIFO DMA stop
* Arguments : uint16_t pipe : pipe number
* : uint32_t remain : transfer byte
* Return Value : none
*******************************************************************************/
void usb0_function_dma_stop_d0 (uint16_t pipe, uint32_t remain)
{
uint16_t dtln;
uint16_t dfacc;
uint16_t buffer;
uint16_t sds_b = 1;
dfacc = RZA_IO_RegRead_16(&USB200.D0FBCFG, USB_DnFBCFG_DFACC_SHIFT, USB_DnFBCFG_DFACC);
if (dfacc == 2)
{
sds_b = 32;
}
else if (dfacc == 1)
{
sds_b = 16;
}
else
{
if (g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size == 2)
{
sds_b = 4;
}
else if (g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size == 1)
{
sds_b = 2;
}
else
{
sds_b = 1;
}
}
if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
{
if (g_usb0_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE)
{
buffer = USB200.D0FIFOCTR;
dtln = (buffer & USB_FUNCTION_BITDTLN);
if ((dtln % sds_b) != 0)
{
remain += (sds_b - (dtln % sds_b));
}
g_usb0_function_PipeDataSize[pipe] = (g_usb0_function_data_count[pipe] - remain);
g_usb0_function_data_count[pipe] = remain;
}
}
RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, 0, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE);
}
/*******************************************************************************
* Function Name: usb0_function_dmaint_buf2fifo
* Description : Executes write completion in FIFO by DMAC.
* Arguments : uint16_t pipe : pipe number
* Return Value : none
*******************************************************************************/
static void usb0_function_dmaint_buf2fifo (uint16_t pipe)
{
uint32_t remain;
uint16_t useport;
useport = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
if (useport == USB_FUNCTION_D0FIFO_DMA)
{
remain = Userdef_USB_usb0_function_stop_dma0();
usb0_function_dma_stop_d0(pipe, remain);
if (g_usb0_function_DmaBval[USB_FUNCTION_D0FIFO] != 0)
{
RZA_IO_RegWrite_16(&USB200.D0FIFOCTR,
1,
USB_DnFIFOCTR_BVAL_SHIFT,
USB_DnFIFOCTR_BVAL);
}
}
else
{
remain = Userdef_USB_usb0_function_stop_dma1();
usb0_function_dma_stop_d1(pipe, remain);
if (g_usb0_function_DmaBval[USB_FUNCTION_D1FIFO] != 0)
{
RZA_IO_RegWrite_16(&USB200.D1FIFOCTR,
1,
USB_DnFIFOCTR_BVAL_SHIFT,
USB_DnFIFOCTR_BVAL);
}
}
usb0_function_enable_bemp_int(pipe);
}
/*******************************************************************************
* Function Name: usb0_host_CtrlTransStart
* Description : Executes USB control transfer.
* Arguments : uint16_t devadr ; device address
* : uint16_t Req ; bmRequestType & bRequest
* : uint16_t Val ; wValue
* : uint16_t Indx ; wIndex
* : uint16_t Len ; wLength
* : uint8_t *Buf ; Data buffer
* Return Value : DEVDRV_SUCCESS ; SUCCESS
* : DEVDRV_ERROR ; ERROR
*******************************************************************************/
int32_t usb0_host_CtrlTransStart (uint16_t devadr, uint16_t Req, uint16_t Val,
uint16_t Indx, uint16_t Len, uint8_t * Buf)
{
if (g_usb0_host_UsbDeviceSpeed == USB_HOST_LOW_SPEED)
{
RZA_IO_RegWrite_16(&USB200.SOFCFG,
1,
USB_SOFCFG_TRNENSEL_SHIFT,
USB_SOFCFG_TRNENSEL);
}
else
{
RZA_IO_RegWrite_16(&USB200.SOFCFG,
0,
USB_SOFCFG_TRNENSEL_SHIFT,
USB_SOFCFG_TRNENSEL);
}
USB200.DCPMAXP = (uint16_t)((uint16_t)(devadr << 12) + g_usb0_host_default_max_packet[devadr]);
if (g_usb0_host_pipe_status[USB_HOST_PIPE0] == USB_HOST_PIPE_IDLE)
{
g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT;
g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
g_usb0_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE);
if (Len == 0)
{
g_usb0_host_CmdStage |= USB_HOST_MODE_NO_DATA; /* No-data Control */
}
else
{
if ((Req & 0x0080) != 0)
{
g_usb0_host_CmdStage |= USB_HOST_MODE_READ; /* Control Read */
}
else
{
g_usb0_host_CmdStage |= USB_HOST_MODE_WRITE; /* Control Write */
}
}
g_usb0_host_SavReq = Req; /* save request */
g_usb0_host_SavVal = Val;
g_usb0_host_SavIndx = Indx;
g_usb0_host_SavLen = Len;
}
else
{
if ((g_usb0_host_SavReq != Req) || (g_usb0_host_SavVal != Val)
|| (g_usb0_host_SavIndx != Indx) || (g_usb0_host_SavLen != Len))
{
return DEVDRV_ERROR;
}
}
switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
{
/* --------------- SETUP STAGE --------------- */
case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE):
usb0_host_SetupStage(Req, Val, Indx, Len);
break;
case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DOING):
/* do nothing */
break;
case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DONE): /* goto next stage */
g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD)))
{
case USB_HOST_MODE_WRITE:
g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
g_usb0_host_CmdStage |= USB_HOST_STAGE_DATA;
break;
case USB_HOST_MODE_READ:
g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
g_usb0_host_CmdStage |= USB_HOST_STAGE_DATA;
break;
case USB_HOST_MODE_NO_DATA:
g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
break;
default:
break;
}
g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
break;
case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_NORES):
if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3)
{
g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
}
else
{
g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
}
break;
/* --------------- DATA STAGE --------------- */
case (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE):
switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD)))
{
case USB_HOST_MODE_WRITE:
usb0_host_CtrlWriteStart((uint32_t)Len, Buf);
break;
case USB_HOST_MODE_READ:
usb0_host_CtrlReadStart((uint32_t)Len, Buf);
break;
default:
break;
}
break;
case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
/* do nothing */
break;
case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DONE): /* goto next stage */
g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
break;
case (USB_HOST_STAGE_DATA | USB_HOST_CMD_NORES):
if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3)
{
g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
}
else
{
g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
usb0_host_clear_pid_stall(USB_HOST_PIPE0);
usb0_host_set_pid_buf(USB_HOST_PIPE0);
}
break;
case (USB_HOST_STAGE_DATA | USB_HOST_CMD_STALL):
g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */
break;
/* --------------- STATUS STAGE --------------- */
case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE):
usb0_host_StatusStage();
break;
case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
/* do nothing */
break;
case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DONE): /* end of Control transfer */
usb0_host_set_pid_nak(USB_HOST_PIPE0);
g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_DONE; /* exit DONE */
break;
case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_NORES):
if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3)
{
g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
}
else
{
g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
usb0_host_clear_pid_stall(USB_HOST_PIPE0);
usb0_host_set_pid_buf(USB_HOST_PIPE0);
}
break;
case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_STALL):
g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */
break;
default:
break;
}
if (g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT)
{
RZA_IO_RegWrite_16(&USB200.SOFCFG,
0,
USB_SOFCFG_TRNENSEL_SHIFT,
USB_SOFCFG_TRNENSEL);
}
return DEVDRV_SUCCESS;
}
/*******************************************************************************
* Function Name: usb1_host_interrupt1
* Description : Execue the USB interrupt.
* Arguments : none
* Return Value : none
*******************************************************************************/
void usb1_host_interrupt1 (void)
{
uint16_t intsts0;
uint16_t intsts1;
uint16_t intenb0;
uint16_t intenb1;
uint16_t brdysts;
uint16_t nrdysts;
uint16_t bempsts;
uint16_t brdyenb;
uint16_t nrdyenb;
uint16_t bempenb;
volatile uint16_t dumy_sts;
intsts0 = USB201.INTSTS0;
intsts1 = USB201.INTSTS1;
intenb0 = USB201.INTENB0;
intenb1 = USB201.INTENB1;
if ((intsts1 & USB_HOST_BITBCHG) && (intenb1 & USB_HOST_BITBCHGE))
{
USB201.INTSTS1 = (uint16_t)~USB_HOST_BITBCHG;
RZA_IO_RegWrite_16(&USB201.INTENB1,
0,
USB_INTENB1_BCHGE_SHIFT,
USB_INTENB1_BCHGE);
g_usb1_host_bchg_flag = USB_HOST_YES;
}
else if ((intsts1 & USB_HOST_BITSACK) && (intenb1 & USB_HOST_BITSACKE))
{
USB201.INTSTS1 = (uint16_t)~USB_HOST_BITSACK;
#if(1) /* ohci_wrapp */
ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
#else
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
#endif
}
else if ((intsts1 & USB_HOST_BITSIGN) && (intenb1 & USB_HOST_BITSIGNE))
{
USB201.INTSTS1 = (uint16_t)~USB_HOST_BITSIGN;
#if(1) /* ohci_wrapp */
g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
#else
g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
g_usb1_host_CmdStage |= USB_HOST_CMD_NORES;
#endif
}
else if (((intsts1 & USB_HOST_BITDTCH) == USB_HOST_BITDTCH)
&& ((intenb1 & USB_HOST_BITDTCHE) == USB_HOST_BITDTCHE))
{
USB201.INTSTS1 = (uint16_t)~USB_HOST_BITDTCH;
RZA_IO_RegWrite_16(&USB201.INTENB1,
0,
USB_INTENB1_DTCHE_SHIFT,
USB_INTENB1_DTCHE);
g_usb1_host_detach_flag = USB_HOST_YES;
Userdef_USB_usb1_host_detach();
usb1_host_UsbDetach2();
}
else if (((intsts1 & USB_HOST_BITATTCH) == USB_HOST_BITATTCH)
&& ((intenb1 & USB_HOST_BITATTCHE) == USB_HOST_BITATTCHE))
{
USB201.INTSTS1 = (uint16_t)~USB_HOST_BITATTCH;
RZA_IO_RegWrite_16(&USB201.INTENB1,
0,
USB_INTENB1_ATTCHE_SHIFT,
USB_INTENB1_ATTCHE);
g_usb1_host_attach_flag = USB_HOST_YES;
Userdef_USB_usb1_host_attach();
usb1_host_UsbAttach();
}
else if ((intsts0 & intenb0 & (USB_HOST_BITBEMP | USB_HOST_BITNRDY | USB_HOST_BITBRDY)))
{
brdysts = USB201.BRDYSTS;
nrdysts = USB201.NRDYSTS;
bempsts = USB201.BEMPSTS;
brdyenb = USB201.BRDYENB;
nrdyenb = USB201.NRDYENB;
bempenb = USB201.BEMPENB;
if ((intsts0 & USB_HOST_BITBRDY) && (intenb0 & USB_HOST_BITBRDYE) && (brdysts & brdyenb))
{
usb1_host_BRDYInterrupt(brdysts, brdyenb);
}
else if ((intsts0 & USB_HOST_BITBEMP) && (intenb0 & USB_HOST_BITBEMPE) && (bempsts & bempenb))
{
usb1_host_BEMPInterrupt(bempsts, bempenb);
}
else if ((intsts0 & USB_HOST_BITNRDY) && (intenb0 & USB_HOST_BITNRDYE) && (nrdysts & nrdyenb))
{
usb1_host_NRDYInterrupt(nrdysts, nrdyenb);
}
else
{
/* Do Nothing */
}
}
else
{
/* Do Nothing */
}
/* Three dummy read for clearing interrupt requests */
dumy_sts = USB201.INTSTS0;
dumy_sts = USB201.INTSTS1;
}
EXEC_RAM void qspiReconfigure(void)
{
fPtr applicationEntry = (fPtr) DEF_USER_PROGRAM_SRC;
qspiExternalAddressForceIdleAndWait();
/*
* The default SPI pins are configured by the ROM bootloader when
* booting from QSPI
*
* On RZ/A1-H these are configured by the bootloader :
* P9.2 SPBCLK0
* P9.3 SPBSSL0
* P9.4 SPBIO00 / SPBM00
* P9.5 SPBIO10 / SPBMI0
*
* To support QUAD mode the following are required:
* P9.6 SPBIO20
* P9.7 SPBIO30
*/
/*
* Configure additional pins for quad mode
* Port 0 is needed in all configurations since it must be attached for
* QSPI boot
*/
/* P9_6: SPBIO20_0 */
RZA_IO_RegWrite_16(&GPIO.PFCAE9, 0, GPIO_PFCAE9_PFCAE96_SHIFT, GPIO_PFCAE9_PFCAE96);
RZA_IO_RegWrite_16(&GPIO.PFCE9, 0, GPIO_PFCE9_PFCE96_SHIFT, GPIO_PFCE9_PFCE96);
RZA_IO_RegWrite_16(&GPIO.PFC9, 1, GPIO_PFC9_PFC96_SHIFT, GPIO_PFC9_PFC96);
RZA_IO_RegWrite_16(&GPIO.PMC9, 1, GPIO_PMC9_PMC96_SHIFT, GPIO_PMC9_PMC96);
RZA_IO_RegWrite_16(&GPIO.PIPC9, 1, GPIO_PIPC9_PIPC96_SHIFT, GPIO_PIPC9_PIPC96);
/* P9_7: SPBIO30_0 */
RZA_IO_RegWrite_16(&GPIO.PFCAE9, 0, GPIO_PFCAE9_PFCAE97_SHIFT, GPIO_PFCAE9_PFCAE97);
RZA_IO_RegWrite_16(&GPIO.PFCE9, 0, GPIO_PFCE9_PFCE97_SHIFT, GPIO_PFCE9_PFCE97);
RZA_IO_RegWrite_16(&GPIO.PFC9, 1, GPIO_PFC9_PFC97_SHIFT, GPIO_PFC9_PFC97);
RZA_IO_RegWrite_16(&GPIO.PMC9, 1, GPIO_PMC9_PMC97_SHIFT, GPIO_PMC9_PMC97);
RZA_IO_RegWrite_16(&GPIO.PIPC9, 1, GPIO_PIPC9_PIPC97_SHIFT, GPIO_PIPC9_PIPC97);
/*
* When dual mode is used, we need 4 additional lines for channel 1
*
* On RZ/A1-H these need to be added for channel 2:
* P2.12 SPBIO01_0
* P2.13 SPBIO11_0
* P2.14 SPBIO21_0
* P2.15 SPBIO31_0
*/
if (QSPI_HARDWARE == DUAL_MEMORY) {
/*
* Clock and slave select must be connected to the same ports used in channel 0
* for the first QSPI Flash chip (P9.2 and P9.3)
*
* Now we add the additional data lanes for the second chip
*
*/
/* P2_12: SPBIO01_0 */
RZA_IO_RegWrite_16(&GPIO.PFCAE2, 0, GPIO_PFCAE2_PFCAE212_SHIFT, GPIO_PFCAE2_PFCAE212);
RZA_IO_RegWrite_16(&GPIO.PFCE2, 1, GPIO_PFCE2_PFCE212_SHIFT, GPIO_PFCE2_PFCE212);
RZA_IO_RegWrite_16(&GPIO.PFC2, 1, GPIO_PFC2_PFC212_SHIFT, GPIO_PFC2_PFC212);
RZA_IO_RegWrite_16(&GPIO.PMC2, 1, GPIO_PMC2_PMC212_SHIFT, GPIO_PMC2_PMC212);
RZA_IO_RegWrite_16(&GPIO.PIPC2, 1, GPIO_PIPC2_PIPC212_SHIFT, GPIO_PIPC2_PIPC212);
/* P2_13: SPBIO11_0 */
RZA_IO_RegWrite_16(&GPIO.PFCAE2, 0, GPIO_PFCAE2_PFCAE213_SHIFT, GPIO_PFCAE2_PFCAE213);
RZA_IO_RegWrite_16(&GPIO.PFCE2, 1, GPIO_PFCE2_PFCE213_SHIFT, GPIO_PFCE2_PFCE213);
RZA_IO_RegWrite_16(&GPIO.PFC2, 1, GPIO_PFC2_PFC213_SHIFT, GPIO_PFC2_PFC213);
RZA_IO_RegWrite_16(&GPIO.PMC2, 1, GPIO_PMC2_PMC213_SHIFT, GPIO_PMC2_PMC213);
RZA_IO_RegWrite_16(&GPIO.PIPC2, 1, GPIO_PIPC2_PIPC213_SHIFT, GPIO_PIPC2_PIPC213);
/* P2_14: SPBIO21_0 */
RZA_IO_RegWrite_16(&GPIO.PFCAE2, 0, GPIO_PFCAE2_PFCAE214_SHIFT, GPIO_PFCAE2_PFCAE214);
RZA_IO_RegWrite_16(&GPIO.PFCE2, 1, GPIO_PFCE2_PFCE214_SHIFT, GPIO_PFCE2_PFCE214);
RZA_IO_RegWrite_16(&GPIO.PFC2, 1, GPIO_PFC2_PFC214_SHIFT, GPIO_PFC2_PFC214);
RZA_IO_RegWrite_16(&GPIO.PMC2, 1, GPIO_PMC2_PMC214_SHIFT, GPIO_PMC2_PMC214);
RZA_IO_RegWrite_16(&GPIO.PIPC2, 1, GPIO_PIPC2_PIPC214_SHIFT, GPIO_PIPC2_PIPC214);
/* P2_15: SPBIO31_0 */
RZA_IO_RegWrite_16(&GPIO.PFCAE2, 0, GPIO_PFCAE2_PFCAE215_SHIFT, GPIO_PFCAE2_PFCAE215);
RZA_IO_RegWrite_16(&GPIO.PFCE2, 1, GPIO_PFCE2_PFCE215_SHIFT, GPIO_PFCE2_PFCE215);
RZA_IO_RegWrite_16(&GPIO.PFCE2, 1, GPIO_PFCE2_PFCE215_SHIFT, GPIO_PFCE2_PFCE215);
RZA_IO_RegWrite_16(&GPIO.PFC2, 1, GPIO_PFC2_PFC215_SHIFT, GPIO_PFC2_PFC215);
RZA_IO_RegWrite_16(&GPIO.PMC2, 1, GPIO_PMC2_PMC215_SHIFT, GPIO_PMC2_PMC215);
RZA_IO_RegWrite_16(&GPIO.PIPC2, 1, GPIO_PIPC2_PIPC215_SHIFT, GPIO_PIPC2_PIPC215);
}
/* After boot the controller is in external address mode
* To change the configuration we need to put the controller back in SPI mode
* Note:
* Some commands might not use the fastest frequencies.
* Choose 33 MHz
*/
spiConfiguration = &spiMode_33Mhz;
qspiControllerConfigure(spiConfiguration);
/* Send a software reset to the Flash devices */
qspiSoftwareReset(spiConfiguration->dataBusSize);
statusReg1_device0.stReg1 = statusReg1_device1.stReg1 = 0;
statusReg2_device0.stReg2 = statusReg2_device1.stReg2 = 0;
/* Read out the manufacturer signature */
/* TODO: may change to use "new" CFI information instead of the legacy READ_EMS command */
qspiReadElectronicManufacturerSignature(&signature0, &signature1, spiConfiguration->dataBusSize);
/* check the EMS read was successful */
/* Stop booting if the flash is not recognized */
if((signature0.deviceId != S25FL512S) || (signature0.manufacturerId != SPANSION_ID))
{
while(1);
};
if(QSPI_HARDWARE == DUAL_MEMORY) {
if( (signature1.deviceId != S25FL512S) || (signature1.manufacturerId != SPANSION_ID))
{
while(1);
};
};
/* Read out the configuration and status registers */
qspiReadConfigRegister(&configReg1_device0, &configReg1_device1, spiConfiguration->dataBusSize);
qspiReadStatusRegister1(&statusReg1_device0, &statusReg1_device1, spiConfiguration->dataBusSize);
qspiReadStatusRegister2(&statusReg2_device0, &statusReg2_device1, spiConfiguration->dataBusSize);
/* Now configure for quad mode */
configReg1_device0.QUAD = QUAD_MODE;
/* always clear latency code to b'00 */
/* on RSK Spansion Flash device it means supporting up to 80 MHz clock frequency */
/* Slower frequencies can use the same latency code for faster frequency */
configReg1_device0.LC0 = 0;
configReg1_device0.LC1 = 0;
if (QSPI_HARDWARE == DUAL_MEMORY) {
configReg1_device1.QUAD = QUAD_MODE;
configReg1_device1.LC0 = 0;
configReg1_device1.LC1 = 0;
}
/* enable writing to the status register */
qspiWriteEnable(spiConfiguration->dataBusSize);
/* verify the read enable latch in the register is set */
qspiReadStatusRegister1(&statusReg1_device0, &statusReg1_device1, spiConfiguration->dataBusSize);
/* write back and configure the memory for quad mode */
qspiWriteStatusConfigRegister(statusReg1_device0, configReg1_device0, statusReg1_device1, configReg1_device1, spiConfiguration->dataBusSize);
/* now disable writes to the status register */
qspiWriteDisable(spiConfiguration->dataBusSize);
#if BYTEREAD_TEST
test_readBytes(spiConfiguration->dataBusSize);
#endif
/* now prepare scenario for external address mode */
/*
* Switch to external address mode
* Note: if the application space is configured in dual mode, the
* "single spi" mode loader flash address space cannot be accessed anymore
* after this point without reconfiguring again the controller
*/
extAddressTransfer = &quadIoRead4b;
extAddressTransfer->optionalData.UINT8[3] = 0x00;
qspiConfigureExternalAddressTransfer(extAddressTransfer);
spiConfiguration = &spiMode_66Mhz;
spiConfiguration->operatingMode = EXTERNAL_ADDRESS_SPACE;
qspiControllerConfigure(spiConfiguration);
/* flush the read cache */
qspiExternalAddressFlushReadCache();
/* now jump to the program application entry point */
(*applicationEntry)();
while(1);
}
