/*
* The application must provide a function that configures a peripheral to
* create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()
* in FreeRTOSConfig.h to call the function. This file contains a function
* that is suitable for use on the Renesas RZ MPU.
*/
void vConfigureTickInterrupt( void )
{
/* Stop the counter. */
OSTM0.OSTMnTT.BIT.OSTMnTT = 1;
/* Work in interval mode. */
OSTM0.OSTMnCTL.BIT.OSTMnMD1 = OSTM_MODE_INTERVAL;
/* Use interrupts after counting starts. */
OSTM0.OSTMnCTL.BIT.OSTMnMD0 = 1;
/* Start value for down counter. */
OSTM0.OSTMnCMP = configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ;
/* Configure the interrupt controller. */
R_INTC_RegistIntFunc( INTC_ID_OSTMI0, ( ISR_FUNCTION ) FreeRTOS_Tick_Handler );
/* Tick must be assigned the lowest interrupt priority. */
R_INTC_SetPriority( INTC_ID_OSTMI0, portLOWEST_USABLE_INTERRUPT_PRIORITY );
INTC.ICCBPR.BIT.Binarypoint = 0;
R_INTC_Enable( INTC_ID_OSTMI0 );
R_OSTM_Open( DEVDRV_CH_0 );
}
/*
* See the serial2.h header file.
*/
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
/* Baud is set in IoInitScif2(), called in prvSetupHardware() in main.c. */
( void ) ulWantedBaud;
/* Create the queues used to hold Rx/Tx characters. Note the comments at
the top of this file regarding the use of queues in this manner. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( char ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( char ) );
/* If the queues were created correctly then setup the serial port
hardware. */
if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )
{
/* Register RXI and TXI handlers. */
R_INTC_RegistIntFunc( INTC_ID_RXI2, prvRXI_Handler );
R_INTC_RegistIntFunc( INTC_ID_TXI2, prvTXI_Handler );
/* Set both interrupts such that they can interrupt the tick. Also
set the Rx interrupt above the Tx interrupt in the hope that (for test
purposes) the Tx interrupt will interrupt the Rx interrupt. */
R_INTC_SetPriority( INTC_ID_RXI2, configMAX_API_CALL_INTERRUPT_PRIORITY );
R_INTC_SetPriority( INTC_ID_TXI2, ( configMAX_API_CALL_INTERRUPT_PRIORITY + 1 ) );
/* This driver is intended to test interrupt interactions, and not
intended to be efficient. Therefore set the RX trigger level to 1. */
SCIF2.SCFCR.BIT.RTRG = 0;
SCIF2.SCFCR.BIT.TTRG = 3;
/* Enable Rx interrupt. Tx interrupt will be enabled when a Tx is
performed. */
SCIF2.SCSCR.BIT.RIE = 1;
R_INTC_Enable( INTC_ID_RXI2 );
R_INTC_Enable( INTC_ID_TXI2 );
}
/* This demo file only supports a single port but we have to return
something to comply with the standard demo header file. */
return ( xComPortHandle ) 0;
}
void dmac0Init(void)
{
//Debug message
TRACE_INFO("Initializing DMAC0 controller...\r\n");
//Select DMA mode (register mode)
DMAC0.CHCFG.BIT.DMS = 0;
//DMA transfers are continued using the next register set
DMAC0.CHCFG.BIT.REN = 1;
//Invert RSEL automatically after a DMA transaction
DMAC0.CHCFG.BIT.RSW = 1;
//Execute the next 0 register set
DMAC0.CHCFG.BIT.RSEL = 0;
//Stop the DMA transfer without sweeping the buffer
DMAC0.CHCFG.BIT.SBE = 0;
//Mask the DMA transfer end interrupt
DMAC0.CHCFG.BIT.DEM = 1;
//Set DMA transfer mode (single transfer mode)
DMAC0.CHCFG.BIT.TM = 0;
//Destination address counting direction (fixed)
DMAC0.CHCFG.BIT.DAD = 1;
//Source address counting direction (increment)
DMAC0.CHCFG.BIT.SAD = 0;
//Destination data size (32 bits)
DMAC0.CHCFG.BIT.DDS = 2;
//Source data size (32 bits)
DMAC0.CHCFG.BIT.SDS = 2;
//Set DMAACK output mode (level mode)
DMAC0.CHCFG.BIT.AM = 1;
//Detect a DMA request based on the level of the signal
DMAC0.CHCFG.BIT.LVL = 1;
//Detect a request when the signal is at the high level
DMAC0.CHCFG.BIT.HIEN = 1;
//Do not detect a request even when the signal is at the low level
DMAC0.CHCFG.BIT.LOEN = 0;
//Request direction (DMAACK is to become active when written)
DMAC0.CHCFG.BIT.REQD = 1;
//Set DMAC channel (CH0/CH8)
DMAC0.CHCFG.BIT.SEL = 0;
//Transfer interval for the DMA channel
DMAC0.CHITVL.LONG = 0;
//Clear channel extension register
DMAC0.CHEXT.LONG = 0;
//Clear channel control register
DMAC0.CHCTRL.LONG = 0;
//DMA resource selectors (SSIF0 peripheral)
DMAC01.DMARS.BIT.CH0_MID = 0x38;
DMAC01.DMARS.BIT.CH0_RID = 0x01;
//Use level output for the DMA transfer end interrupt
DMAC07.DCTRL.BIT.LVINT = 1;
//Set transfer priority control mode (fixed priority)
DMAC07.DCTRL.BIT.PR = 0;
//Register DMAINT0 interrupt handler
R_INTC_RegistIntFunc(INTC_ID_DMAINT0, dmac0IrqHandler);
//Configure DMAINT0 interrupt priority
R_INTC_SetPriority(INTC_ID_DMAINT0, DMAC0_IRQ_PRIORITY);
}
