void CPersTst::PersTst()
{
if (PR_htValid) {
switch (PR_htInst) {
case TST_READ:
{
if (ReadMemBusy()) {
HtRetry();
break;
}
P_err = 0;
P_gvarAddr = 0;
ReadMem_gvar(P_memAddr, P_gvarAddr, P_gvarAddr, 0);
ReadMemPause(TST_CHK);
}
break;
case TST_CHK:
{
if (SendCallBusy_tst2()) {
HtRetry();
break;
}
if (GR_gvar[0].data != 0xdeadbeef00001234ULL) {
HtAssert(0, 0);
P_err += 1;
}
SendCall_tst2(TST_CALL, P_memAddr, P_err);
}
break;
case TST_CALL:
{
if (SendCallBusy_tst3()) {
HtRetry();
break;
}
SendCall_tst3(TST_RTN, P_memAddr);
}
break;
case TST_RTN:
{
if (SendReturnBusy_htmain()) {
HtRetry();
break;
}
SendReturn_htmain(P_err);
}
break;
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR);
break;
}
case TEST00_WR: {
PW_test00_0_src_u0_data[0].write_addr(1, 1);
PW_test00_0_src_u0_data[0].test00_0_src_u3_data.test00_0_src_v5_data[0] = ((int16_t)0x00030d46d8f2d5e0LL);
PW_test00_0_src_u0_data[0].test00_0_src_u3_data.test00_0_src_v5_data[1] = ((int16_t)0x00030d46d8f2d5e0LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_src_u3_data(PR_memAddr + 0, 1, 1, 0, 1);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_src_u3_data(PR_memAddr + 0, 1, 1, 0, 1);
P_test00_0_src_u0_data_RdAddr1 = (ht_uint4)1;
P_test00_0_src_u0_data_RdAddr2 = (ht_uint2)1;
ReadMemPause(TEST00_CHK);
break;
}
case TEST00_CHK: {
if ((int16_t)PR_test00_0_src_u0_data[0].test00_0_src_u3_data.test00_0_src_v5_data[0] != ((int16_t)0x00030d46d8f2d5e0LL)) {
HtAssert(0, 0);
}
if ((int16_t)PR_test00_0_src_u0_data[0].test00_0_src_u3_data.test00_0_src_v5_data[1] != ((int16_t)0x00030d46d8f2d5e0LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void
CPersRead::PersRead()
{
if (PR_htValid) {
switch (PR_htInst) {
case READ_ENTRY: {
if (ReadMemBusy()) {
HtRetry();
break;
}
if (P_flush) {
// don't start new reads, check that reads are complete before txfr control to pipe
ReadMemPoll(READ_TFR);
} else {
// Memory read request
ReadMem_opAMem(P_vaAddr, PR_idx, false);
HtContinue(READ_LDB);
}
}
break;
case READ_LDB: {
if (ReadMemBusy()) {
HtRetry();
break;
}
// Memory read request
ReadMem_opBMem(P_vbAddr, PR_idx);
ReadMemPause(READ_TFR);
}
break;
case READ_TFR: {
if (SendTransferBusy_pipe()) {
HtRetry();
break;
}
SendTransfer_pipe(P_idx, P_vtAddr, P_scalar, P_operation, P_flush);
}
break;
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR0);
break;
}
case TEST00_WR0: {
S_test00_0_dst_u0_data[4].write_addr(3);
S_test00_0_dst_u0_data[4].write_mem().test00_0_dst_v0_data[0][0] = ((uint8_t)0x001791e73186ba40LL);
S_test00_0_dst_u0_data[4].write_mem().test00_0_dst_v0_data[0][1] = ((uint8_t)0x001791e73186ba40LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_dst_u0_data(PR_memAddr + 0, 4);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_dst_u0_data(PR_memAddr + 0, 4);
ReadMemPause(TEST00_CHK0);
break;
}
case TEST00_CHK0: {
SR_test00_0_dst_u0_data[4].read_addr(3);
if (SR_test00_0_dst_u0_data[4].read_mem().test00_0_dst_v0_data[0][0] != ((uint8_t)0x001791e73186ba40LL)) {
HtAssert(0, 0);
}
if (S_test00_0_dst_u0_data[4].read_mem().test00_0_dst_v0_data[0][1] != ((uint8_t)0x001791e73186ba40LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR0);
break;
}
case TEST00_WR0: {
S_test00_0_src_s0_data[1].test00_0_src_v0_data = ((uint8_t)0x0019dd5784fd41e0LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_uint8_t(PR_memAddr + 0, S_test00_0_src_s0_data[1].test00_0_src_v0_data);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_dst_v1_data(PR_memAddr + 0, 1, 0, 3);
P_test00_0_dst_s0_data_RdAddr1 = (ht_uint5)29;
P_test00_0_dst_s0_data_RdAddr2 = (ht_uint4)10;
ReadMemPause(TEST00_CHK0);
break;
}
case TEST00_CHK0: {
if (GR_test00_0_dst_s0_data[1][0].test00_0_dst_s1_data.test00_0_dst_s2_data[3].test00_0_dst_v1_data != ((uint8_t)0x0019dd5784fd41e0LL)) {
printf("\n");
printf("EXP: 0x%02x\n", (uint8_t)0x0019dd5784fd41e0LL);
printf("ACT: 0x%02x\n", GR_test00_0_dst_s0_data[1][0].test00_0_dst_s1_data.test00_0_dst_s2_data[3].test00_0_dst_v1_data);
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void CPersTest02::PersTest02() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST02_ENTRY: {
HtContinue(TEST02_WR);
break;
}
case TEST02_WR: {
GW_test02_0_0_data.write_addr(1);
GW_test02_0_0_data = (uint16_t)0x000f42d48c6b5fe0LL;
P_test02_0_0_data_RdAddr1 = (ht_uint1)1;
HtContinue(TEST02_ST0);
break;
}
case TEST02_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_uint16_t(PR_memAddr + 0, GR_test02_0_0_data);
WriteMemPause(TEST02_LD0);
break;
}
case TEST02_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test02_0_1_data(PR_memAddr + 0, 3, 1, 0, 1);
P_test02_0_1_data_RdAddr1 = (ht_uint2)3;
P_test02_0_1_data_RdAddr2 = (ht_uint1)1;
ReadMemPause(TEST02_CHK);
break;
}
case TEST02_CHK: {
if ((uint16_t)GR_test02_0_1_data[0] != (uint16_t)0x000f42d48c6b5fe0LL) {
HtAssert(0, (uint32_t)0x00020000);
}
HtContinue(TEST02_RTN);
break;
}
case TEST02_RTN: {
if (SendReturnBusy_test02()) {
HtRetry();
break;
}
SendReturn_test02();
break;
}
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR);
break;
}
case TEST00_WR: {
S_test00_0_v0_data = (uint32_t)0x001e30bb590b7c20LL;
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_v0_data(PR_memAddr + 0);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_v1_data(PR_memAddr + 0, 1, 1);
P_test00_0_v1_data_RdAddr1 = (ht_uint1)1;
ReadMemPause(TEST00_CHK);
break;
}
case TEST00_CHK: {
printf("EXP (Test00): 0x%08x\n", (uint32_t)0x001e30bb590b7c20LL);
printf("ACT (Test00): 0x%08x\n", (uint32_t)PR_test00_0_v1_data);
if ((uint32_t)PR_test00_0_v1_data != (uint32_t)0x001e30bb590b7c20LL) {
HtAssert(0, (uint32_t)0x00010000);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void CPersTest04::PersTest04() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST04_ENTRY: {
HtContinue(TEST04_WR);
break;
}
case TEST04_WR: {
PW_test04_0_0_data[0].write_addr(1);
PW_test04_0_0_data[0] = (uint32_t)0x001f0506fc2d5be0LL;
P_test04_0_0_data_RdAddr1 = (ht_uint1)1;
HtContinue(TEST04_ST0);
break;
}
case TEST04_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_uint32_t(PR_memAddr + 0, PR_test04_0_0_data[0]);
WriteMemPause(TEST04_LD0);
break;
}
case TEST04_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test04_0_1_data(PR_memAddr + 0, 0, 1);
P_test04_0_1_data_RdAddr1 = (ht_uint1)0;
ReadMemPause(TEST04_CHK);
break;
}
case TEST04_CHK: {
if ((uint32_t)PR_test04_0_1_data != (uint32_t)0x001f0506fc2d5be0LL) {
HtAssert(0, (uint32_t)0x00040000);
}
HtContinue(TEST04_RTN);
break;
}
case TEST04_RTN: {
if (SendReturnBusy_test04()) {
HtRetry();
break;
}
SendReturn_test04();
break;
}
default:
assert(0);
}
}
}
void CPersTest01::PersTest01() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST01_ENTRY: {
HtContinue(TEST01_WR);
break;
}
case TEST01_WR: {
PW_test01_0_0_data[0].write_addr(1, 1);
PW_test01_0_0_data[0] = (uint32_t)0x0008fc35477e21e0LL;
P_test01_0_0_data_RdAddr1 = (ht_uint1)1;
P_test01_0_0_data_RdAddr2 = (ht_uint2)1;
HtContinue(TEST01_ST0);
break;
}
case TEST01_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_uint32_t(PR_memAddr + 0, PR_test01_0_0_data[0]);
WriteMemPause(TEST01_LD0);
break;
}
case TEST01_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test01_0_1_data(PR_memAddr + 0);
ReadMemPause(TEST01_CHK);
break;
}
case TEST01_CHK: {
if ((uint32_t)GR_test01_0_1_data != (uint32_t)0x0008fc35477e21e0LL) {
HtAssert(0, (uint32_t)0x00010000);
}
HtContinue(TEST01_RTN);
break;
}
case TEST01_RTN: {
if (SendReturnBusy_test01()) {
HtRetry();
break;
}
SendReturn_test01();
break;
}
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR);
break;
}
case TEST00_WR: {
PW_test00_0_s0_data[0][0].write_addr(0);
PW_test00_0_s0_data[0][0].test00_0_v0_data = (uint32_t)0x000f282d40dc1a20LL;
P_test00_0_s0_data_RdAddr1 = (ht_uint1)0;
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_uint32_t(PR_memAddr + 0, PR_test00_0_s0_data[0][0].test00_0_v0_data);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_v2_data(PR_memAddr + 0, 0, 0, 1);
ReadMemPause(TEST00_CHK);
break;
}
case TEST00_CHK: {
S_test00_0_v2_data[0][0].read_addr(0);
if ((uint32_t)S_test00_0_v2_data[0][0].read_mem() != (uint32_t)0x000f282d40dc1a20LL) {
HtAssert(0, (uint32_t)0x00000000);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR3_htValid) {
switch (PR3_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR0);
break;
}
case TEST00_WR0: {
S_test00_0_src_v0_data[1] = ((uint8_t)0x0005fe8e04926bc0LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_src_v0_data(PR3_memAddr + 0, 0, 3);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_dst_v0_data(PR3_memAddr + 0, 1, 0, 2, 2, 0, 2);
P3_test00_0_dst_s0_data_RdAddr1 = (ht_uint3)1;
P3_test00_0_dst_s0_data_RdAddr2 = (ht_uint5)0;
ReadMemPause(TEST00_CHK0);
break;
}
case TEST00_CHK0: {
if ((uint8_t)GR3_test00_0_dst_s0_data[2][2].test00_0_dst_v0_data[1] != ((uint8_t)0x0005fe8e04926bc0LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void CPersTest07::PersTest07() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST07_ENTRY: {
HtContinue(TEST07_WR);
break;
}
case TEST07_WR: {
S_test07_0_src_v0_data[0][0].write_addr(2, 2);
S_test07_0_src_v0_data[0][0].write_mem((int64_t)0x000b446373a6a660LL);
HtContinue(TEST07_ST0);
break;
}
case TEST07_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
S_test07_0_src_v0_data[0][0].read_addr(2, 2);
WriteMem_int64_t(PR_memAddr + 0, S_test07_0_src_v0_data[0][0].read_mem());
WriteMemPause(TEST07_LD0);
break;
}
case TEST07_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test07_0_dst_v0_data(PR_memAddr + 0);
ReadMemPause(TEST07_CHK);
break;
}
case TEST07_CHK: {
if ((int64_t)GR_test07_0_dst_v0_data != ((int64_t)0x000b446373a6a660LL)) {
HtAssert(0, 0);
}
HtContinue(TEST07_RTN);
break;
}
case TEST07_RTN: {
if (SendReturnBusy_test07()) {
HtRetry();
break;
}
SendReturn_test07();
break;
}
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR);
break;
}
case TEST00_WR: {
GW_test00_0_src_s0_data[1][4].write_addr(31, 21);
GW_test00_0_src_s0_data[1][4].test00_0_src_u0_data.test00_0_src_v5_data[3] = ((int64_t)0x0014aa913ee74960LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_src_v5_data(PR_memAddr + 0, 31, 21, 1, 4, 3, 1);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_dst_v0_data(PR_memAddr + 0, 2, 0, 1);
ReadMemPause(TEST00_CHK);
break;
}
case TEST00_CHK: {
if ((int64_t)GR_test00_0_dst_v0_data[2][0] != ((int64_t)0x0014aa913ee74960LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR);
break;
}
case TEST00_WR: {
PW_test00_0_src_u0_data.write_addr(7, 0);
PW_test00_0_src_u0_data.test00_0_src_u1_data[1][0].test00_0_src_v4_data[0][0] = ((uint16_t)0x000d29b349215400LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_src_v4_data(PR_memAddr + 0, 7, 0, 1, 0, 0, 1);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_dst_v0_data(PR_memAddr + 0);
ReadMemPause(TEST00_CHK);
break;
}
case TEST00_CHK: {
if ((uint16_t)PR_test00_0_dst_v0_data != ((uint16_t)0x000d29b349215400LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR2_htValid) {
switch (PR2_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR0);
break;
}
case TEST00_WR0: {
P2_test00_0_src_v0_data[1] = ((uint8_t)0x000c594186129be0LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_uint8_t(PR2_memAddr + 0, P2_test00_0_src_v0_data[1]);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_dst_v0_data(PR2_memAddr + 0, 2);
P2_test00_0_dst_u0_data_RdAddr1 = (ht_uint2)2;
ReadMemPause(TEST00_CHK0);
break;
}
case TEST00_CHK0: {
if (PR2_test00_0_dst_u0_data[2].test00_0_dst_v0_data[3] != ((uint8_t)0x000c594186129be0LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR);
break;
}
case TEST00_WR: {
P_test00_0_src_v0_data[0][0] = ((int32_t)0x001fe79ea30a33c0LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_src_v0_data(PR_memAddr + 0, 0, 0, 3);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_dst_v0_data(PR_memAddr + 0, 0, 0, 3);
ReadMemPause(TEST00_CHK);
break;
}
case TEST00_CHK: {
// I never wrote the src var at [0][1]...this shouldn't be equal!
if ((int32_t)PR_test00_0_dst_v0_data[0][1] == ((int32_t)0x001fe79ea30a33c0LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void CPersTest01::PersTest01() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST01_ENTRY: {
HtContinue(TEST01_WR);
break;
}
case TEST01_WR: {
GW_test01_0_0_data.test01_0_0_data[0] = (uint32_t)0x000a6fb2efa357a0LL;
HtContinue(TEST01_ST0);
break;
}
case TEST01_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test01_0_0_data(PR_memAddr + 0);
WriteMemPause(TEST01_LD0);
break;
}
case TEST01_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test01_0_3_data(PR_memAddr + 0);
ReadMemPause(TEST01_CHK);
break;
}
case TEST01_CHK: {
if ((uint32_t)P_test01_0_2_data.test01_0_3_data[0] != (uint32_t)0x000a6fb2efa357a0LL) {
HtAssert(0, (uint32_t)0x00010000);
}
HtContinue(TEST01_RTN);
break;
}
case TEST01_RTN: {
if (SendReturnBusy_test01()) {
HtRetry();
break;
}
SendReturn_test01();
break;
}
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR);
break;
}
case TEST00_WR: {
P_test00_0_src_s0_data[0].test00_0_src_v0_data = ((uint32_t)0x0015a3c65555c9a0LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_src_s0_data(PR_memAddr + 0, 0, 1);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_src_s0_data(PR_memAddr + 0, 0, 1);
ReadMemPause(TEST00_CHK);
break;
}
case TEST00_CHK: {
if ((uint32_t)P_test00_0_src_s0_data[0].test00_0_src_v0_data != ((uint32_t)0x0015a3c65555c9a0LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR0);
break;
}
case TEST00_WR0: {
P_test00_0_src_v0_data = ((ht_uint21)0x000bee4da53c6fe0LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_ht_uint21(PR_memAddr + 0, P_test00_0_src_v0_data);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_src_v0_data(PR_memAddr + 0);
ReadMemPause(TEST00_CHK0);
break;
}
case TEST00_CHK0: {
if ((ht_uint21)PR_test00_0_src_v0_data != ((ht_uint21)0x000bee4da53c6fe0LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR4_htValid) {
switch (PR4_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR);
break;
}
case TEST00_WR: {
P4_test00_0_src_v0_data = ((ht_int48)0x0005e9b4c8fece20LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_src_v0_data(PR4_memAddr + 0);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_src_v0_data(PR4_memAddr + 0);
ReadMemPause(TEST00_CHK);
break;
}
case TEST00_CHK: {
if (PR4_test00_0_src_v0_data != (int64_t)0xffffe9b4c8fece20LL) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR);
break;
}
case TEST00_WR: {
GW_test00_0_v0_data[1] = (uint32_t)0x001a50be16eb3880LL;
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_v0_data(PR_memAddr + 0);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_v1_data(PR_memAddr + 0);
ReadMemPause(TEST00_CHK);
break;
}
case TEST00_CHK: {
if ((uint32_t)SR_test00_0_v1_data != (uint32_t)0x001a50be16eb3880LL) {
HtAssert(0, (uint32_t)0x00000000);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void CPersPriv1::PersPriv1()
{
if (PR_htValid) {
switch (PR_htInstr) {
case PRIV1_ENTRY:
{
P_data = 0x3434343456565656LL;
HtContinue(PRIV1_WRITE);
break;
}
case PRIV1_WRITE:
{
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_data(PR_memAddr);
WriteMemPause(PRIV1_READ);
break;
}
case PRIV1_READ:
{
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_data(PR_memAddr);
ReadMemPause(PRIV1_RETURN);
break;
}
case PRIV1_RETURN:
{
if (SendReturnBusy_priv1()) {
HtRetry();
break;
}
if (PR_data != 0x3434343456565656LL) P_err = true;
SendReturn_priv1(P_err);
break;
}
default:
assert(0);
}
}
}
void
CPersRelu::PersRelu()
{
if (PR_htValid) {
switch (PR_htInst) {
case RELU_LD1: {
BUSY_RETRY(ReadMemBusy());
// Memory read request
//printf("calculate address idx: %u", P_vecIdx);
fflush(stdout);
MemAddr_t memRdAddr = SR_op1Addr + (P_vecIdx << 3);
//printf("About to read ");
ReadMem_op1(memRdAddr);
ReadMemPause(RELU_ST);
}
break;
case RELU_ST: {
BUSY_RETRY(WriteMemBusy());
uint64_t basemask = 0x000000000000FFFF;
P_result = 0;
for(int i = 0; i < 64; i+=16){
if((int16_t)(PR_op1 >> i) > 0){
P_result = P_result | (PR_op1 & (basemask << i));
}else{
//Rectify the i'th element to 0
//P_result = 0;
}
}
//printf("ST op1: %ld => %ld\n",PR_op1, P_result);
// Memory write request
MemAddr_t memWrAddr = SR_resAddr + (P_vecIdx << 3);
WriteMem(memWrAddr, P_result);
WriteMemPause(RELU_RTN);
}
break;
case RELU_RTN: {
BUSY_RETRY(SendReturnBusy_relu());
SendReturn_relu();
}
break;
default:
assert(0);
}
}
void CPersTst3::PersTst3()
{
if (PR_htValid) {
switch (PR_htInst) {
case TST3_ENTRY:
{
if (ReadMemBusy()) {
HtRetry();
break;
}
GW_gvar3.data = 0x35;
ReadMem_gvar31(P_memAddr, PR_htId);
ReadMemPause(TST3_RTN);
}
break;
case TST3_RTN:
{
if (SendReturnBusy_tst3()) {
HtRetry();
break;
}
ht_uint8 rdData = GR_gvar3.data;
if (rdData != 0x35)
HtAssert(0, 0);
rdData = GR_gvar31.data;
if (rdData != 0x34)
HtAssert(0, 0);
SendReturn_tst3();
}
break;
default:
assert(0);
}
}
}
void
CPersOver::PersOver()
{
if (PR_htValid) {
switch (PR_htInstr) {
case OVER_RD: {
BUSY_RETRY(ReadMemBusy());
ReadMem_data(P_addr);
ReadMemPause(OVER_WR);
}
break;
case OVER_WR: {
BUSY_RETRY(WriteMemBusy());
WriteMem(P_addr, ~PR_data);
WriteMemPause(OVER_RSM);
}
break;
case OVER_RSM: {
S_bResume = true;
HtPause(OVER_RTN);
}
break;
case OVER_RTN: {
BUSY_RETRY(SendReturnBusy_htmain());
SendReturn_htmain();
}
break;
default:
assert(0);
}
}
if (SR_bResume) {
S_bResume = false;
HtResume(0);
}
}
void
CPersGupsCore::PersGupsCore()
{
MemAddr_t rndIdx = SR_base + ((PR_ran & (SR_tblSize - 1)) << 3); // QW index
if (PR_htValid) {
switch (PR_htInst) {
case PGC_ENTRY: {
P_ran = (uint64_t)(PR_ran << 1) ^ ((int64_t) PR_ran < 0 ? POLY : 0);
HtContinue(PGC_READ);
break;
}
case PGC_READ: {
BUSY_RETRY(ReadMemBusy());
ReadMem_intData(rndIdx);
ReadMemPause(PGC_WRITE);
break;
}
case PGC_WRITE: {
BUSY_RETRY(WriteMemBusy());
WriteMem(rndIdx, PR_intData^PR_ran, /*orderChk=*/ false);
P_ran = (uint64_t)(PR_ran << 1) ^ ((int64_t) PR_ran < 0 ? POLY : 0);
P_vecIdx += 1;
if (P_vecIdx < SR_vecLen) {
HtContinue(PGC_READ);
} else
HtContinue(PGC_RTN);
break;
}
case PGC_RTN: {
BUSY_RETRY(SendReturnBusy_GupsCore());
SendReturn_GupsCore();
break;
}
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR);
break;
}
case TEST00_WR: {
PW_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_v1_data[0] = ((int8_t)0x000e618a5ec1b240LL);
PW_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_v2_data[0][0] = ((int64_t)0x000c7954e20d9e20LL);
PW_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_v2_data[1][0] = ((int64_t)0x000c7954e20d9e20LL);
PW_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_v2_data[2][0] = ((int64_t)0x000c7954e20d9e20LL);
PW_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_v2_data[3][0] = ((int64_t)0x000c7954e20d9e20LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_dst_s1_data_struct(PR_memAddr + 0, PR_test00_0_dst_s0_data.test00_0_dst_s1_data);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_dst_s1_data(PR_memAddr + 0);
ReadMemPause(TEST00_CHK);
break;
}
case TEST00_CHK: {
if ((int8_t)PR_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_v1_data[0] != ((int8_t)0x000e618a5ec1b240LL)) {
HtAssert(0, 0);
}
if ((int64_t)PR_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_v2_data[0][0] != ((int64_t)0x000c7954e20d9e20LL)) {
HtAssert(0, 0);
}
if ((int64_t)PR_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_v2_data[1][0] != ((int64_t)0x000c7954e20d9e20LL)) {
HtAssert(0, 0);
}
if ((int64_t)PR_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_v2_data[2][0] != ((int64_t)0x000c7954e20d9e20LL)) {
HtAssert(0, 0);
}
if ((int64_t)PR_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_v2_data[3][0] != ((int64_t)0x000c7954e20d9e20LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void
CPersStencil::PersStencil()
{
if (PR_htValid) {
//fprintf(stderr,"stencil was called and r_ts_htValid is %d and state is %d and thread id is %d\n",
// r_ts_htValid, (int)r_ts_htInst, PR_htId.to_int());
switch (PR_htInst) {
case START: // 1
{
P_change = 0;
P_i = 0;
P_ram_rdVal = PR_htId; // indexed only by thread id
HtContinue(FIRST_TWO_ROWS_LOOP_TOP);
}
break;
// fill in first two rows of temp array
// for (i = 0; i < m; i++) {
// tempa[0][i] = a[0][i]; // main memory read
// tempa[1][i] = a[1][i]; // main memory read
// }
case FIRST_TWO_ROWS_LOOP_TOP: // 3
{
if (!(P_i < P_p_m)) {
HtContinue(FIRST_TWO_ROWS_LOOP_EXIT);
break;
}
if (ReadMemBusy()) {
HtRetry();
break;
}
// First read request
memAddrT memAddr = addr(P_p_a, 0 + P_p_js, P_i + P_p_is);
sc_uint<STENCIL_HTID_W> ramWrAddr = PR_htId;
// Mif0RdReq(rsmInst, memAddr, rdDstId, ramIdx, bFirst, bLast)
// Mif0RdReq(CHAINED_READ, /* rsmInst */
ReadMem_j0(memAddr, /* memAddr */
ramWrAddr); /* ramIdx */
HtContinue(FIRST_TWO_ROWS_READ2);
}
break;
case FIRST_TWO_ROWS_READ2: // 4
{
// Second read request
if (ReadMemBusy()) {
HtRetry();
break;
}
// Set up for write to tempa[P_i] on next clock
P_ram_i = tempaIndex(P_i);
memAddrT memAddr = addr(P_p_a, 1 + P_p_js, P_i + P_p_is);
sc_uint<STENCIL_HTID_W> ramWrAddr = PR_htId;
// Mif0RdReq(rsmInst, memAddr, rdDstId, ramIdx, bFirst, bLast)
ReadMem_j1(memAddr, /* memAddr */
ramWrAddr); /* ramIdx */
ReadMemPause(FIRST_TWO_ROWS_ASSIGN);
}
break;
case FIRST_TWO_ROWS_ASSIGN: // 5
{
// tempa[0][P_i] = MifRdVal(1);
// tempa[1][P_i] = MifRdVal(2);
GW_tempa.write_addr(P_ram_i);
GW_tempa.j0 = GR_mifRdVal.j0;
GW_tempa.j1 = GR_mifRdVal.j1;
// increment i and loop back
P_i = P_i + 1;
HtContinue(FIRST_TWO_ROWS_LOOP_TOP);
}
break;
case FIRST_TWO_ROWS_LOOP_EXIT: // 6
{
// for (j = 2; j < n; j++) {
P_j = 2;
// Set up for read from tempa[0] on next clock
P_ram_i = tempaIndex(0);
HtContinue(J_LOOP_TOP);
}
break;
case J_LOOP_TOP: // 7
{
if (!(P_j < P_p_n)) {
HtContinue(J_LOOP_EXIT);
break;
}
if (ReadMemBusy()) {
HtRetry();
break;
}
P_t00 = GR_tempa.j0;
P_t10 = GR_tempa.j1;
// Set up to read from tempa[1] on next clock
P_ram_i = tempaIndex(1);
#if 0
// These have to be delayeduntil next slot
// copy initial values for first two columns into "registers"
// j i j i
P_t01 = tempa[0][1];
P_t11 = tempa[1][1];
#endif
// P_t20 = a[j][0]; P_t21 = a[j][1]; // main memory reads
// First read request
memAddrT memAddr = addr(P_p_a, P_j + P_p_js, 0 + P_p_is);
sc_uint<STENCIL_HTID_W> ramWrAddr = PR_htId; // P_t20
// Mif0RdReq(rsmInst, memAddr, rdDstId, ramIdx, bFirst, bLast)
ReadMem_j0(memAddr, /* memAddr */
ramWrAddr); /* ramIdx */
HtContinue(J_LOOP_READ2);
}
break;
case J_LOOP_READ2: // 8
{
// Second read request
if (ReadMemBusy()) {
HtRetry();
break;
}
P_t01 = GR_tempa.j0;
P_t11 = GR_tempa.j1;
memAddrT memAddr = addr(P_p_a, P_j + P_p_js, 1 + P_p_is);
sc_uint<STENCIL_HTID_W> ramWrAddr = PR_htId; // P_t21
// Mif0RdReq(rsmInst, memAddr, rdDstId, ramIdx, bFirst, bLast)
ReadMem_j1(memAddr, /* memAddr */
ramWrAddr); /* ramIdx */
// Set up to write to tempa[0] on next clock
P_ram_i = tempaIndex(0);
ReadMemPause(J_LOOP_ASSIGN);
}
break;
case J_LOOP_ASSIGN: // 9
{
P_t20 = GR_mifRdVal.j0;
P_t21 = GR_mifRdVal.j1;
// Save these first two values (shift columns up) for next j
// tempa[0][0] = P_t10;
// tempa[1][0] = P_t20;
GW_tempa.write_addr(P_ram_i);
GW_tempa.j0 = P_t10;
GW_tempa.j1 = P_t20;
#if 0
// block ram writes to slot 1 delayed until next clock
tempa[0][1] = P_t11;
tempa[1][1] = P_t21;
#endif
// Set up to write to tempa[1] on next clock
P_ram_i = tempaIndex(1);
// for (i = 2; i < m; i++) {
P_i = 2;
HtContinue(J_LOOP_ASSIGN2);
}
break;
case J_LOOP_ASSIGN2: // 15
{
// tempa[0][1] = P_t11;
// tempa[1][1] = P_t21;
GW_tempa.write_addr(P_ram_i);
GW_tempa.j0 = P_t11;
GW_tempa.j1 = P_t21;
// Set up to read from tempa[P_i] on next clock
P_ram_i = tempaIndex(P_i);
HtContinue(I_LOOP_TOP);
}
break;
case I_LOOP_TOP: // 11
{
if (!(P_i < P_p_m)) {
HtContinue(I_LOOP_EXIT);
break;
}
if (ReadMemBusy()) {
HtRetry();
break;
}
// Get third column
// P_t02 = tempa[0][P_i]; // AE memory
// P_t12 = tempa[1][P_i]; // AE memory
P_t02 = GR_tempa.j0;
P_t12 = GR_tempa.j1;
// P_t22 = a[j][i]; // main memory read
memAddrT memAddr = addr(P_p_a, P_j + P_p_js, P_i + P_p_is);
sc_uint<STENCIL_HTID_W> ramWrAddr = PR_htId; // P_t22
// Mif0RdReq(rsmInst, memAddr, rdDstId, ramIdx, bFirst, bLast)
ReadMem_j0(memAddr, /* memAddr */
ramWrAddr); /* ramIdx */
// Set up to write to tempa[P_i] on next clock
assert(P_ram_i == tempaIndex(P_i)); // should already be set
P_ram_i = tempaIndex(P_i);
ReadMemPause(I_LOOP_ASSIGN);
}
break;
case I_LOOP_ASSIGN: // 12
{
if (WriteMemBusy()) {
HtRetry();
break;
}
// Get third column
P_t22 = GR_mifRdVal.j0;
// Save these values (shift column up) for next j
// tempa[0][P_i] = P_t12;
// tempa[1][P_i] = P_t22;
GW_tempa.write_addr(P_ram_i);
GW_tempa.j0 = P_t12;
GW_tempa.j1 = P_t22;
P_res =
mulX(P_p_w0, P_t11) +
mulX(P_p_w1, (P_t10 + P_t01 + P_t12 + P_t21)) +
mulX(P_p_w2, (P_t00 + P_t20 + P_t02 + P_t22));
// newa[j-1][i-1] = res; // main memory store
memAddrT memAddr = addr(P_p_newa, P_p_js + P_j - 1, P_p_is + P_i - 1);
WriteMem(memAddr, (sc_uint<MEM_DATA_W>)P_res);
WriteMemPause(I_LOOP_CHANGE);
}
break;
case I_LOOP_CHANGE: // 13
{
P_diff = fabs(P_res - P_t11);
P_change = fmax(P_change, P_diff);
// prepare for next iteration; shift columns left
P_t00 = P_t01; P_t01 = P_t02;
P_t10 = P_t11; P_t11 = P_t12;
P_t20 = P_t21; P_t21 = P_t22;
P_i = P_i + 1;
// Set up to read from tempa[P_i] on next clock
P_ram_i = tempaIndex(P_i);
HtContinue(I_LOOP_TOP);
}
break;
case I_LOOP_EXIT: // 14
{
// increment j and loop back
P_j = P_j + 1;
// Set up for read from tempa[0] on next clock
P_ram_i = tempaIndex(0);
HtContinue(J_LOOP_TOP);
}
break;
case J_LOOP_EXIT: // 10
{
HtContinue(DONE);
}
break;
case DONE: // 2
{
if (SendReturnBusy_stencil()) {
HtRetry();
break;
}
#if 0
fprintf(stderr, "not busy -- doing return from thread %d change is %g\n",
(int)(P_htId),
((double)P_change) / ((double)(ONE)));
#endif
SendReturn_stencil(P_change);
// HtPause();
}
break;
default:
#if 0
fprintf(stderr, "Stencil did not handle state %d\n", (int)r_ts_htInst);
#endif
break;
}
} // r_ts_htValid
}
void CPersBcm::PersBcm()
{
if (PR1_htValid) {
switch (PR1_htInst) {
// Initial Entry Point from Host Code -> BCM_ENTRY
//
// Read in Task information
// GR_task -> midState[8]/data[3]/initNonce/lastNonce/target[3]
case BCM_ENTRY: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_task(PR1_pBcmTask);
ReadMemPause(BCM_TASK_VALID);
}
break;
// Force initial task to be valid
// Setup initial Nonce
case BCM_TASK_VALID: {
S_bTaskValid = true;
S_nonce = S_task.m_initNonce;
S_hashCount = 0;
HtContinue(BCM_CHK_RTN);
}
break;
// Main hash loop, sit and check the result queue
case BCM_CHK_RTN: {
if (SendReturnBusy_bcm() || SendHostMsgBusy()) {
HtRetry();
break;
}
if (S_hashCount > 1000000) {
SendHostMsg(BCM_HASHES_COMPLETED, (ht_uint56)S_hashCount);
S_hashCount = 0;
}
if (S_nonceHitQue.empty()) {
// No results waiting
if (S_bTaskValid) {
HtContinue(BCM_CHK_RTN);
} else {
if (S_hashCount > 0) {
SendHostMsg(BCM_HASHES_COMPLETED, (ht_uint56)S_hashCount);
S_hashCount = 0;
}
SendReturn_bcm(P1_pBcmTask);
}
} else {
// Results are waiting to be processed
if (S_bcmRsltQue.empty())
HtContinue(BCM_CHK_RTN);
else
HtContinue(BCM_WR_RSLT1);
}
// Reset index for results to zero (for writing to memory)
S_rsltQwIdx = 0;
}
break;
// BCM_WR_RSLT1->3, steps to write a result to memory
case BCM_WR_RSLT1: {
if (WriteMemBusy()) {
HtRetry();
break;
}
ht_uint48 memAddr = S_bcmRsltQue.front() | (S_rsltQwIdx << 3);
WriteMem(memAddr, S_task.m_qw[S_rsltQwIdx]);
S_rsltQwIdx += 1;
if (S_rsltQwIdx < 5)
HtContinue(BCM_WR_RSLT1);
else
HtContinue(BCM_WR_RSLT2);
}
break;
case BCM_WR_RSLT2: {
if (WriteMemBusy()) {
HtRetry();
break;
}
ht_uint48 memAddr = S_bcmRsltQue.front() | (5 << 3);
ht_uint64 memData;
memData(31, 0) = S_task.m_qw[5] & 0xffffffff;
memData(63, 32) = BcmByteSwap32(S_nonceHitQue.front());
S_nonceHitQue.pop();
WriteMem(memAddr, memData);
WriteMemPause(BCM_WR_RSLT3);
}
break;
case BCM_WR_RSLT3: {
if (SendHostMsgBusy()) {
HtRetry();
break;
}
SendHostMsg(BCM_RSLT_BUF_RDY, (ht_uint56)S_bcmRsltQue.front());
S_bcmRsltQue.pop();
HtContinue(BCM_CHK_RTN);
}
break;
default:
assert(0);
}
}
// temps used within macros
uint32_t temp1, temp2, tmp;
// Input Valid Signal reflects Task Valid Signal
T1_vld = S_bTaskValid;
// *** State Setup ***
// Setup T1_data
T1_data.m_dw[0] = S_task.m_data[0];
T1_data.m_dw[1] = S_task.m_data[1];
T1_data.m_dw[2] = S_task.m_data[2];
T1_data.m_dw[3] = S_nonce;
T1_data.m_dw[4] = 0x80000000;
T1_data.m_dw[5] = 0x00000000;
T1_data.m_dw[6] = 0x00000000;
T1_data.m_dw[7] = 0x00000000;
T1_data.m_dw[8] = 0x00000000;
T1_data.m_dw[9] = 0x00000000;
T1_data.m_dw[10] = 0x00000000;
T1_data.m_dw[11] = 0x00000000;
T1_data.m_dw[12] = 0x00000000;
T1_data.m_dw[13] = 0x00000000;
T1_data.m_dw[14] = 0x00000000;
T1_data.m_dw[15] = 0x00000280;
// Setup T1_state
T1_state.m_state[0] = S_task.m_midState.m_state[0];
T1_state.m_state[1] = S_task.m_midState.m_state[1];
T1_state.m_state[2] = S_task.m_midState.m_state[2];
T1_state.m_state[3] = S_task.m_midState.m_state[3];
T1_state.m_state[4] = S_task.m_midState.m_state[4];
T1_state.m_state[5] = S_task.m_midState.m_state[5];
T1_state.m_state[6] = S_task.m_midState.m_state[6];
T1_state.m_state[7] = S_task.m_midState.m_state[7];
// Nonce
T1_nonce = S_nonce;
// *** Do Work ***
// 64-deep Hash Cycle 1
Q(T2_state, 0, T2_data, 0x428A2F98);
Q(T3_state, 7, T3_data, 0x71374491);
Q(T4_state, 6, T4_data, 0xB5C0FBCF);
Q(T5_state, 5, T5_data, 0xE9B5DBA5);
Q(T6_state, 4, T6_data, 0x3956C25B);
Q(T7_state, 3, T7_data, 0x59F111F1);
Q(T8_state, 2, T8_data, 0x923F82A4);
Q(T9_state, 1, T9_data, 0xAB1C5ED5);
Q(T10_state, 0, T10_data, 0xD807AA98);
Q(T11_state, 7, T11_data, 0x12835B01);
Q(T12_state, 6, T12_data, 0x243185BE);
Q(T13_state, 5, T13_data, 0x550C7DC3);
Q(T14_state, 4, T14_data, 0x72BE5D74);
Q(T15_state, 3, T15_data, 0x80DEB1FE);
Q(T16_state, 2, T16_data, 0x9BDC06A7);
Q(T17_state, 1, T17_data, 0xC19BF174);
R(T18_state, 0, T18_data, 0xE49B69C1);
R(T19_state, 7, T19_data, 0xEFBE4786);
R(T20_state, 6, T20_data, 0x0FC19DC6);
R(T21_state, 5, T21_data, 0x240CA1CC);
R(T22_state, 4, T22_data, 0x2DE92C6F);
R(T23_state, 3, T23_data, 0x4A7484AA);
R(T24_state, 2, T24_data, 0x5CB0A9DC);
R(T25_state, 1, T25_data, 0x76F988DA);
R(T26_state, 0, T26_data, 0x983E5152);
R(T27_state, 7, T27_data, 0xA831C66D);
R(T28_state, 6, T28_data, 0xB00327C8);
R(T29_state, 5, T29_data, 0xBF597FC7);
R(T30_state, 4, T30_data, 0xC6E00BF3);
R(T31_state, 3, T31_data, 0xD5A79147);
R(T32_state, 2, T32_data, 0x06CA6351);
R(T33_state, 1, T33_data, 0x14292967);
R(T34_state, 0, T34_data, 0x27B70A85);
R(T35_state, 7, T35_data, 0x2E1B2138);
R(T36_state, 6, T36_data, 0x4D2C6DFC);
R(T37_state, 5, T37_data, 0x53380D13);
R(T38_state, 4, T38_data, 0x650A7354);
R(T39_state, 3, T39_data, 0x766A0ABB);
R(T40_state, 2, T40_data, 0x81C2C92E);
R(T41_state, 1, T41_data, 0x92722C85);
R(T42_state, 0, T42_data, 0xA2BFE8A1);
R(T43_state, 7, T43_data, 0xA81A664B);
R(T44_state, 6, T44_data, 0xC24B8B70);
R(T45_state, 5, T45_data, 0xC76C51A3);
R(T46_state, 4, T46_data, 0xD192E819);
R(T47_state, 3, T47_data, 0xD6990624);
R(T48_state, 2, T48_data, 0xF40E3585);
R(T49_state, 1, T49_data, 0x106AA070);
R(T50_state, 0, T50_data, 0x19A4C116);
R(T51_state, 7, T51_data, 0x1E376C08);
R(T52_state, 6, T52_data, 0x2748774C);
R(T53_state, 5, T53_data, 0x34B0BCB5);
R(T54_state, 4, T54_data, 0x391C0CB3);
R(T55_state, 3, T55_data, 0x4ED8AA4A);
R(T56_state, 2, T56_data, 0x5B9CCA4F);
R(T57_state, 1, T57_data, 0x682E6FF3);
R(T58_state, 0, T58_data, 0x748F82EE);
R(T59_state, 7, T59_data, 0x78A5636F);
R(T60_state, 6, T60_data, 0x84C87814);
R(T61_state, 5, T61_data, 0x8CC70208);
R(T62_state, 4, T62_data, 0x90BEFFFA);
R(T63_state, 3, T63_data, 0xA4506CEB);
R(T64_state, 2, T64_data, 0xBEF9A3F7);
R(T65_state, 1, T65_data, 0xC67178F2);
// Add following hash cycle 1
T66_state.m_state[0] = T66_state.m_state[0] + S_task.m_midState.m_state[0];
T66_state.m_state[1] = T66_state.m_state[1] + S_task.m_midState.m_state[1];
T66_state.m_state[2] = T66_state.m_state[2] + S_task.m_midState.m_state[2];
T66_state.m_state[3] = T66_state.m_state[3] + S_task.m_midState.m_state[3];
T66_state.m_state[4] = T66_state.m_state[4] + S_task.m_midState.m_state[4];
T66_state.m_state[5] = T66_state.m_state[5] + S_task.m_midState.m_state[5];
T66_state.m_state[6] = T66_state.m_state[6] + S_task.m_midState.m_state[6];
T66_state.m_state[7] = T66_state.m_state[7] + S_task.m_midState.m_state[7];
// State Setup
// Setup T67_data
T67_data.m_dw[0] = T67_state.m_state[0];
T67_data.m_dw[1] = T67_state.m_state[1];
T67_data.m_dw[2] = T67_state.m_state[2];
T67_data.m_dw[3] = T67_state.m_state[3];
T67_data.m_dw[4] = T67_state.m_state[4];
T67_data.m_dw[5] = T67_state.m_state[5];
T67_data.m_dw[6] = T67_state.m_state[6];
T67_data.m_dw[7] = T67_state.m_state[7];
T67_data.m_dw[8] = 0x00000000;
T67_data.m_dw[9] = 0x00000000;
T67_data.m_dw[10] = 0x00000000;
T67_data.m_dw[11] = 0x00000000;
T67_data.m_dw[12] = 0x00000000;
T67_data.m_dw[13] = 0x00000000;
T67_data.m_dw[14] = 0x00000000;
T67_data.m_dw[15] = 0x00000000;
T67_data.m_uc[35] = 0x80;
T67_data.m_uc[61] = 0x01;
// Setup T67_state
T67_state.m_state[0] = 0x6A09E667;
T67_state.m_state[1] = 0xBB67AE85;
T67_state.m_state[2] = 0x3C6EF372;
T67_state.m_state[3] = 0xA54FF53A;
T67_state.m_state[4] = 0x510E527F;
T67_state.m_state[5] = 0x9B05688C;
T67_state.m_state[6] = 0x1F83D9AB;
T67_state.m_state[7] = 0x5BE0CD19;
// 64-deep Hash Cycle 2
Q(T68_state, 0, T68_data, 0x428A2F98);
Q(T69_state, 7, T69_data, 0x71374491);
Q(T70_state, 6, T70_data, 0xB5C0FBCF);
Q(T71_state, 5, T71_data, 0xE9B5DBA5);
Q(T72_state, 4, T72_data, 0x3956C25B);
Q(T73_state, 3, T73_data, 0x59F111F1);
Q(T74_state, 2, T74_data, 0x923F82A4);
Q(T75_state, 1, T75_data, 0xAB1C5ED5);
Q(T76_state, 0, T76_data, 0xD807AA98);
Q(T77_state, 7, T77_data, 0x12835B01);
Q(T78_state, 6, T78_data, 0x243185BE);
Q(T79_state, 5, T79_data, 0x550C7DC3);
Q(T80_state, 4, T80_data, 0x72BE5D74);
Q(T81_state, 3, T81_data, 0x80DEB1FE);
Q(T82_state, 2, T82_data, 0x9BDC06A7);
Q(T83_state, 1, T83_data, 0xC19BF174);
R(T84_state, 0, T84_data, 0xE49B69C1);
R(T85_state, 7, T85_data, 0xEFBE4786);
R(T86_state, 6, T86_data, 0x0FC19DC6);
R(T87_state, 5, T87_data, 0x240CA1CC);
R(T88_state, 4, T88_data, 0x2DE92C6F);
R(T89_state, 3, T89_data, 0x4A7484AA);
R(T90_state, 2, T90_data, 0x5CB0A9DC);
R(T91_state, 1, T91_data, 0x76F988DA);
R(T92_state, 0, T92_data, 0x983E5152);
R(T93_state, 7, T93_data, 0xA831C66D);
R(T94_state, 6, T94_data, 0xB00327C8);
R(T95_state, 5, T95_data, 0xBF597FC7);
R(T96_state, 4, T96_data, 0xC6E00BF3);
R(T97_state, 3, T97_data, 0xD5A79147);
R(T98_state, 2, T98_data, 0x06CA6351);
R(T99_state, 1, T99_data, 0x14292967);
R(T100_state, 0, T100_data, 0x27B70A85);
R(T101_state, 7, T101_data, 0x2E1B2138);
R(T102_state, 6, T102_data, 0x4D2C6DFC);
R(T103_state, 5, T103_data, 0x53380D13);
R(T104_state, 4, T104_data, 0x650A7354);
R(T105_state, 3, T105_data, 0x766A0ABB);
R(T106_state, 2, T106_data, 0x81C2C92E);
R(T107_state, 1, T107_data, 0x92722C85);
R(T108_state, 0, T108_data, 0xA2BFE8A1);
R(T109_state, 7, T109_data, 0xA81A664B);
R(T110_state, 6, T110_data, 0xC24B8B70);
R(T111_state, 5, T111_data, 0xC76C51A3);
R(T112_state, 4, T112_data, 0xD192E819);
R(T113_state, 3, T113_data, 0xD6990624);
R(T114_state, 2, T114_data, 0xF40E3585);
R(T115_state, 1, T115_data, 0x106AA070);
R(T116_state, 0, T116_data, 0x19A4C116);
R(T117_state, 7, T117_data, 0x1E376C08);
R(T118_state, 6, T118_data, 0x2748774C);
R(T119_state, 5, T119_data, 0x34B0BCB5);
R(T120_state, 4, T120_data, 0x391C0CB3);
R(T121_state, 3, T121_data, 0x4ED8AA4A);
R(T122_state, 2, T122_data, 0x5B9CCA4F);
R(T123_state, 1, T123_data, 0x682E6FF3);
R(T124_state, 0, T124_data, 0x748F82EE);
R(T125_state, 7, T125_data, 0x78A5636F);
R(T126_state, 6, T126_data, 0x84C87814);
R(T127_state, 5, T127_data, 0x8CC70208);
R(T128_state, 4, T128_data, 0x90BEFFFA);
R(T129_state, 3, T129_data, 0xA4506CEB);
R(T130_state, 2, T130_data, 0xBEF9A3F7);
R(T131_state, 1, T131_data, 0xC67178F2);
// Add following hash cycle 2
T132_state.m_state[0] = BcmByteSwap32(T132_state.m_state[0] + 0x6A09E667);
T132_state.m_state[1] = BcmByteSwap32(T132_state.m_state[1] + 0xBB67AE85);
T132_state.m_state[2] = BcmByteSwap32(T132_state.m_state[2] + 0x3C6EF372);
T132_state.m_state[3] = BcmByteSwap32(T132_state.m_state[3] + 0xA54FF53A);
T132_state.m_state[4] = BcmByteSwap32(T132_state.m_state[4] + 0x510E527F);
T132_state.m_state[5] = BcmByteSwap32(T132_state.m_state[5] + 0x9B05688C);
T132_state.m_state[6] = BcmByteSwap32(T132_state.m_state[6] + 0x1F83D9AB);
T132_state.m_state[7] = BcmByteSwap32(T132_state.m_state[7] + 0x5BE0CD19);
// *** End Checks ***
// Increment Nonce
if (T1_vld)
S_nonce++;
// Send MSG back if we need to!
// Check for Result Found
if (T133_vld && !S_nonceHitQue.full()) {
bool bW7Eq = T133_state.m_state[7] == S_task.m_target[2];
bool bW7Lt = T133_state.m_state[7] < S_task.m_target[2];
bool bW6Eq = T133_state.m_state[6] == S_task.m_target[1];
bool bW6Lt = T133_state.m_state[6] < S_task.m_target[1];
bool bW5Eq = T133_state.m_state[5] == S_task.m_target[0];
bool bW5Lt = T133_state.m_state[5] < S_task.m_target[0];
bool bMatch = bW7Lt || bW7Eq && (bW6Lt || bW6Eq && (bW5Lt || bW5Eq));
if (bMatch)
S_nonceHitQue.push(BcmByteSwap32(T133_nonce));
// Check for Last Nonce / Increment count
if (S_task.m_lastNonce == T133_nonce)
S_bTaskValid = false;
else
S_hashCount++;
}
// Check force return / reset
if (S_forceReturn) {
S_bTaskValid = false;
S_forceReturn = false;
}
if (GR_htReset) {
S_zeroInput = true;
S_bTaskValid = false;
S_forceReturn = false;
}
}
void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR0);
break;
}
case TEST00_WR0: {
S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v1_data = ((int32_t)0x0002daa2633de3e0LL);
S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v2_data[0][0] = ((int32_t)0x0000ba052338b540LL);
S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v2_data[0][1] = ((int32_t)0x0000ba052338b540LL);
S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v2_data[0][2] = ((int32_t)0x0000ba052338b540LL);
S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v2_data[0][3] = ((int32_t)0x0000ba052338b540LL);
S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v3_data = ((uint32_t)0x00194f52bcc93520LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_dst_s2_data_struct(PR_memAddr + 0, SR_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_dst_s2_data(PR_memAddr + 0);
ReadMemPause(TEST00_CHK0);
break;
}
case TEST00_CHK0: {
if ((int32_t)S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v1_data != ((int32_t)0x0002daa2633de3e0LL)) {
printf("EXP: 0x%08x\n", (int32_t)0x0002daa2633de3e0LL);
printf("ACT: 0x%08x\n\n", (int32_t)S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v1_data);
HtAssert(0, 0);
}
if ((int32_t)SR_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v2_data[0][0] != ((int32_t)0x0000ba052338b540LL)) {
HtAssert(0, 0);
}
if ((int32_t)S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v2_data[0][1] != ((int32_t)0x0000ba052338b540LL)) {
HtAssert(0, 0);
}
if ((int32_t)SR_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v2_data[0][2] != ((int32_t)0x0000ba052338b540LL)) {
HtAssert(0, 0);
}
if ((int32_t)S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v2_data[0][3] != ((int32_t)0x0000ba052338b540LL)) {
HtAssert(0, 0);
}
if ((uint32_t)S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v3_data != ((uint32_t)0x00194f52bcc93520LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}