static void InitForceUsbIdSwitchOpen (void)
{
I2C_WriteByte(0x72, 0x90, 0x26); // Disable CBUS discovery
ReadModifyWriteTPI(0x95, SI_BIT_6, SI_BIT_6); // Force USB ID switch to open
ReadModifyWriteTPI(0x95, SI_BIT_6, SI_BIT_6); // Force USB ID switch to open
WriteByteTPI(0x92, 0x46); // Force MHD mode
}
void HotPlugService (void) {
DisableInterrupts(0xFF);
Active9232();
if ((HDCP_TxSupports == true)) {
if (HDCP_AksvValid == true) {
// AV MUTE
TPI_DEBUG_PRINT (("TMDS -> Enabled (Video Muted)\n"));
ReadModifyWriteTPI(0x1A, BIT_6 | BIT_4 | BIT_3,
0x40 | 0x00 | 0x08);
tmdsPoweredUp = true;
EnableInterrupts(BIT_0 | 0x02 | 0x10 | 0x20 | 0x40 | 0x80);
}
} else {
TPI_DEBUG_PRINT (("TMDS -> Enabled\n"));
ReadModifyWriteTPI(0x1A,
BIT_6 | BIT_4 | BIT_3,
0x40 | 0x00 | 0x08);
tmdsPoweredUp = TRUE;
EnableInterrupts(0x01 | 0x02 | 0x10 | 0x40);
}
TxPowerStateD0();
I2C_WriteByte(TPI_SLAVE_ADDR, 0xcd, 0x0);
I2C_WriteByte(TPI_SLAVE_ADDR, 0x19, 0x0);
}
void SiiDrvHdmiTxLiteHdcpInitialize (void)
{
#ifdef KSVFORWARD //(
// Enable the KSV Forwarding feature and the KSV FIFO Intererrupt
ReadModifyWriteTPI(TPI_HDCP_CONTROL_DATA_REG, KSV_FORWARD_MASK, KSV_FORWARD_ENABLE);
ReadModifyWriteTPI(TPI_KSV_FIFO_READY_INT_EN, KSV_FIFO_READY_EN_MASK, KSV_FIFO_READY_ENABLE);
#endif //)
}
void Active9232 (void) {
uint8_t i;
uint8_t *video_parm = &video_param[hd_720p][0];
/* choose video mode */
if (mhl_tpi_info->check_hdmi_sink()) {
I2C_WriteByte(TPI_SLAVE_ADDR, 0x08, 0x70);
I2C_WriteBlock(TPI_SLAVE_ADDR, 0x0, video_parm, 8);
I2C_WriteByte(TPI_SLAVE_ADDR, 0x0, 0x60);
}
if (!mhl_tpi_info->check_hdmi_sink()) {
ReadModifyWriteTPI(0x1A, BIT_0, 0x01);
}
I2C_WriteByte(TPI_SLAVE_ADDR, 0x09, 0x00);
I2C_WriteByte(TPI_SLAVE_ADDR, 0x19, 0x00);
if (!mhl_tpi_info->check_hdmi_sink()) {
ReadModifyWriteTPI(0x1A, BIT_0, 0x00);
}
I2C_WriteByte(TPI_SLAVE_ADDR, 0x60, 0x00);
I2C_WriteByte(TPI_SLAVE_ADDR, 0xbf, 0x00);
for (i = 0; i < 14 ;i++)
I2C_WriteByte(TPI_SLAVE_ADDR, 0x0C + i, avi_info_frame[hd_720p][i]);
I2C_WriteByte(TPI_SLAVE_ADDR, 0xbf, 0xc6);
if (mhl_tpi_info->check_hdmi_sink()) {
I2C_WriteByte(TPI_SLAVE_ADDR, 0x26, 0x91);
I2C_WriteByte(TPI_SLAVE_ADDR, 0x25, 0x03);
I2C_WriteByte(TPI_SLAVE_ADDR, 0x27, 0x59);
I2C_WriteByte(TPI_SLAVE_ADDR, 0x28, 0x00);
I2C_WriteByte(TPI_SLAVE_ADDR, 0x1f, 0x80);
I2C_WriteByte(TPI_SLAVE_ADDR, 0x20, 0x90);
I2C_WriteByte(TPI_SLAVE_ADDR, 0x21, 0x00);
I2C_WriteByte(TPI_SLAVE_ADDR, 0x24, 0x02);
I2C_WriteByte(TPI_SLAVE_ADDR, 0x25, 0x00);
I2C_WriteByte(TPI_SLAVE_ADDR, 0xbc, 0x02);
I2C_WriteByte(TPI_SLAVE_ADDR, 0xbd, 0x24);
I2C_WriteByte(TPI_SLAVE_ADDR, 0xbe, 0x92);
I2C_WriteByte(TPI_SLAVE_ADDR, 0xbc, 0x02);
I2C_WriteByte(TPI_SLAVE_ADDR, 0xbd, 0x2f);
I2C_WriteByte(TPI_SLAVE_ADDR, 0xbe, 0x0);
I2C_WriteByte(TPI_SLAVE_ADDR, 0x26, 0x81);
I2C_WriteBlock(TPI_SLAVE_ADDR, 0xbf, audio_info_frame, 15);
I2C_WriteByte(TPI_SLAVE_ADDR, 0x0a, 0x0);
}
}
void EnableTMDS (void)
{
printk("[SIMG] TMDS -> Enabled\n");
ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG, TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE);
tmdsPoweredUp = TRUE;
}
static void TxPowerStateD0 (void)
{
ReadModifyWriteTPI(TPI_DEVICE_POWER_STATE_CTRL_REG, TX_POWER_STATE_MASK, 0x00);
TPI_DEBUG_PRINT(("[SIMG] TX Power State D0\n"));
txPowerState = TX_POWER_STATE_D0;
}
void DisableTMDS(void)
{
TPI_DEBUG_PRINT(("TMDS -> Disabled\n"));
ReadModifyWriteTPI(0x1A, BIT_4 | BIT_3,
0x10 | 0x08);
tmdsPoweredUp = false;
}
void EnableTMDS(void)
{
TPI_DEBUG_PRINT(("TMDS -> Enabled\n"));
ReadModifyWriteTPI(0x1A, BIT_4,
0x00);
tmdsPoweredUp = true;
}
void DisableTMDS (void)
{
TPI_DEBUG_PRINT(("[SIMG] TMDS -> Disabled\n"));
ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG, TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_POWER_DOWN);
tmdsPoweredUp = FALSE;
}
byte MHD_Bridge_detect(void)
{
byte temp = 0;
byte BridgeOn = 0;
/* disable interrupts */
ReadModifyWriteTPI(TPI_INTERRUPT_ENABLE_REG,
RECEIVER_SENSE_EVENT_MASK, 0x00);
msleep(180);
if(!gpio_get_value(TEGRA_GPIO_PI5)&& MHD_HW_IsOn()) //TEGRA_GPIO_PI5: GPIO_ACCESSORY_INT
{
temp = ReadIndexedRegister(INDEXED_PAGE_0, 0x09);
if ((temp & RSEN) == 0x00) {
BridgeOn = FALSE;
//ReadModifyWriteTPI(0x79, SI_BIT_5 | SI_BIT_4, SI_BIT_4); //force HPD to 0
ReadModifyWriteIndexedRegister(INDEXED_PAGE_0, 0x79, SI_BIT_5 | SI_BIT_4, SI_BIT_4);
} else {
BridgeOn = TRUE;
//ReadModifyWriteTPI(0x79, BIT_5 | BIT_4, 0); //back to current state
}
printk("[HDMI] Bridge detect %x :: HPD %d\n",BridgeOn,gpio_get_value(TEGRA_GPIO_PN7)); //TEGRA_GPIO_PN7: GPIO_HDMI_HPD
//ReadModifyWriteTPI(0x79, SI_BIT_5 | SI_BIT_4, 0); //back to current state
ReadModifyWriteIndexedRegister(INDEXED_PAGE_0, 0x79, SI_BIT_5 | SI_BIT_4, 0);
}
MHD_INT_clear();
/* enable interrupts */
WriteIndexedRegister(INDEXED_PAGE_0, 0x78, 0x01);
printk("[HDMI]MHD_Bridge_detect -- \n");
return BridgeOn;
}
static void TxPowerStateD0(void)
{
ReadModifyWriteTPI(0x1E, BIT_1 | BIT_0, 0x00);
TPI_DEBUG_PRINT(("TX Power State D0\n"));
ReadModifyWriteIndexedRegister(0x01, 0x94, BIT_0 | BIT_1, 0x01);
ReadModifyWriteIndexedRegister(0x01, 0x93, 0xF0, 0x80);
}
void mhl_output_enable(void)
{
mdelay(100);
//ReadModifyWriteIndexedRegister(INDEXED_PAGE_0, 0x95, BIT_5, BIT_5);
//WriteIndexedRegister(INDEXED_PAGE_0, 0x74, 0x40);
WriteIndexedRegister(INDEXED_PAGE_0, 0xA0, 0x10);
mdelay(100);
ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG, TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE);
}
static void HotPlugService(void)
{
/* disable interrupts */
ReadModifyWriteTPI(TPI_INTERRUPT_ENABLE_REG,
RECEIVER_SENSE_EVENT_MASK, 0x00);
/* enable TMDS */
pr_info("[SIMG] TMDS -> Enabled\n");
ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG,
TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE);
tmdsPoweredUp = TRUE;
TxPowerStateD0();
/* enable interrupts */
WriteIndexedRegister(INDEXED_PAGE_0, 0x78, 0x01);
CheckTxFifoStable();
}
void sii9234_tpi_init(void)
{
MHD_HW_Reset();
//sii9234_initial_registers_set(); //previous setting
printk("[HDMI]9234 init ++ \n");
#if 0
/* disable interrupts */
ReadModifyWriteTPI(TPI_INTERRUPT_ENABLE_REG,
RECEIVER_SENSE_EVENT_MASK, 0x00);
//MHD_INT_clear();
#endif
sii9234_register_init();
/* start tpi */
WriteByteTPI(TPI_ENABLE, 0x00); /* Write "0" to 72:C7 to
start HW TPI mode */
/* enable interrupts */
WriteIndexedRegister(INDEXED_PAGE_0, 0x78, 0x01);
/* mhd rx connected */
WriteIndexedRegister(INDEXED_PAGE_0,
0xA0, 0x10); /* TX termination enable */
WriteByteCBUS(0x07, DDC_XLTN_TIMEOUT_MAX_VAL |
0x0E); /* Increase DDC translation layer timer (burst mode) */
WriteByteCBUS(0x47, 0x03);
WriteByteCBUS(0x21, 0x01); /* Heartbeat Disable */
/* enable mhd tx */
ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG,
TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE);
/* set mhd power active mode */
ReadModifyWriteTPI(TPI_DEVICE_POWER_STATE_CTRL_REG,
TX_POWER_STATE_MASK, 0x00);
mhd_tx_fifo_stable(); //fifo clear
printk("[HDMI]9234 init -- \n");
}
void OnDownstreamRxPoweredDown(void)
{
TPI_DEBUG_PRINT(("[SIMG] DSRX -> Powered Down\n"));
dsRxPoweredUp = FALSE;
/* disable TMDS */
TPI_DEBUG_PRINT(("[SIMG] TMDS -> Disabled\n"));
ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG,
TMDS_OUTPUT_CONTROL_MASK,
TMDS_OUTPUT_CONTROL_POWER_DOWN);
tmdsPoweredUp = FALSE;
}
void sii9234_tpi_init(void)
{
MHD_HW_Reset();
pr_info("[HDMI]9234 init ++\n");
sii9234_register_init();
/* start tpi */
WriteByteTPI(TPI_ENABLE, 0x00); /* Write "0" to 72:C7 to
start HW TPI mode */
/* enable interrupts */
WriteIndexedRegister(INDEXED_PAGE_0, 0x78, 0x01);
/* mhd rx connected */
WriteIndexedRegister(INDEXED_PAGE_0,
0xA0, 0x10); /* TX termination enable */
WriteByteCBUS(0x07, DDC_XLTN_TIMEOUT_MAX_VAL |
0x0E); /* Increase DDC translation layer timer (burst mode) */
WriteByteCBUS(0x47, 0x03);
WriteByteCBUS(0x21, 0x01); /* Heartbeat Disable */
/* enable mhd tx */
ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG,
TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE);
/* set mhd power active mode */
ReadModifyWriteTPI(TPI_DEVICE_POWER_STATE_CTRL_REG,
TX_POWER_STATE_MASK, 0x00);
mhd_tx_fifo_stable(); /*fifo clear*/
#ifdef CONFIG_SAMSUNG_WORKAROUND_HPD_GLANCE
mhl_hpd_handler(true);
#endif
pr_info("[HDMI]9234 init --\n");
}
static void WriteInitialRegisterValues(void)
{
I2C_WriteByte(TPI_SLAVE_ADDR, 0x08, 0x37);
I2C_WriteByte(TPI_SLAVE_ADDR, 0xA0, 0xD0);
I2C_WriteByte(TPI_SLAVE_ADDR, 0xA1, 0xFC);
I2C_WriteByte(TPI_SLAVE_ADDR, 0xA3, 0xC0);
I2C_WriteByte(TPI_SLAVE_ADDR, 0xA6, 0x0C);
I2C_WriteByte(TPI_SLAVE_ADDR, 0x2B, 0x01);
ReadModifyWriteTPI(0x90, BIT_3 | BIT_2, BIT_2);
I2C_WriteByte(TPI_SLAVE_ADDR, 0x91, 0xA5);
I2C_WriteByte(TPI_SLAVE_ADDR, 0x94, 0x75);
I2C_WriteByte(CBUS_SLAVE_ADDR, 0x31, I2C_ReadByte(CBUS_SLAVE_ADDR, 0x31) | 0x0c);
I2C_WriteByte(TPI_SLAVE_ADDR, 0xA5, 0xA0);
TPI_DEBUG_PRINT(("1x Mode\n"));
I2C_WriteByte(TPI_SLAVE_ADDR, 0x95, 0x31);
I2C_WriteByte(TPI_SLAVE_ADDR, 0x96, 0x20);
ReadModifyWriteTPI(0x97, BIT_1, 0);
ReadModifyWriteTPI(0x95, BIT_6, BIT_6);
WriteByteTPI(0x92, 0x86);
WriteByteTPI(0x93, 0xCC);
if (txPowerState != TX_POWER_STATE_D3) {
ReadModifyWriteTPI(0x79, BIT_5 | BIT_4, BIT_4);
}
DelayMS(25);
ReadModifyWriteTPI(0x95, BIT_6, 0x00);
ReadModifyWriteTPI(0x78, BIT_5, 0);
I2C_WriteByte(TPI_SLAVE_ADDR, 0x90, 0x27);
I2C_WriteByte(TPI_SLAVE_ADDR, 0x05, 0x08);
DelayMS(2);
I2C_WriteByte(TPI_SLAVE_ADDR, 0x05, 0x00);
InitCBusRegs();
I2C_WriteByte(TPI_SLAVE_ADDR, 0x05, ASR_VALUE);
}
void MHD_OUT_EN(void)
{
byte state , int_stat;
int_stat = ReadIndexedRegister(INDEXED_PAGE_0, 0x74);
pr_info("[HDMI]MHD_OUT_EN INT register value is: 0x%02x\n", int_stat);
state = ReadIndexedRegister(INDEXED_PAGE_0, 0x81);
pr_info("[HDMI]MHD_OUT_EN register 0x81 value is: 0x%02x\n", state);
if ((state & 0x02) && (int_stat & 0x01)) {
pr_info("[HDMI]MHD_OUT_EN :: enable output\n");
ReadModifyWriteIndexedRegister(INDEXED_PAGE_0, 0x80, SI_BIT_4,
0x0);
msleep(20);
ReadModifyWriteIndexedRegister(INDEXED_PAGE_0, 0x80, SI_BIT_4,
SI_BIT_4);
msleep(60);
/* set mhd power active mode */
ReadModifyWriteTPI(TPI_DEVICE_POWER_STATE_CTRL_REG,
TX_POWER_STATE_MASK, 0x00);
mhd_tx_fifo_stable(); /*fifo clear*/
}
MHD_INT_clear();
}
void sii9234_register_init(void)
{
// Power Up
I2C_WriteByte(0x7A, 0x3D, 0x3F); // Power up CVCC 1.2V core
I2C_WriteByte(0x92, 0x11, 0x01); // Enable TxPLL Clock
I2C_WriteByte(0x92, 0x12, 0x15); // Enable Tx Clock Path & Equalizer
I2C_WriteByte(0x72, 0x08, 0x35); // Power Up TMDS Tx Core
I2C_WriteByte(0x92, 0x00, 0x00); // SIMG: correcting HW default
I2C_WriteByte(0x92, 0x13, 0x60); // SIMG: Set termination value
I2C_WriteByte(0x92, 0x14, 0xF0); // SIMG: Change CKDT level
I2C_WriteByte(0x92, 0x4B, 0x06); // SIMG: Correcting HW default
// Analog PLL Control
I2C_WriteByte(0x92, 0x17, 0x07); // SIMG: PLL Calrefsel
I2C_WriteByte(0x92, 0x1A, 0x20); // VCO Cal
I2C_WriteByte(0x92, 0x22, 0xE0); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x23, 0xC0); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x24, 0xA0); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x25, 0x80); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x26, 0x60); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x27, 0x40); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x28, 0x20); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x29, 0x00); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x4D, 0x02); // SIMG: PLL Mode Value (order is important)
I2C_WriteByte(0x92, 0x4C, 0xA0); // Manual zone control
I2C_WriteByte(0x72, 0x80, 0x14); // Enable Rx PLL Clock Value
I2C_WriteByte(0x92, 0x31, 0x0B); // SIMG: Rx PLL BW value from I2C BW ~ 4MHz
I2C_WriteByte(0x92, 0x45, 0x06); // SIMG: DPLL Mode
I2C_WriteByte(0x72, 0xA0, 0xD0); // SIMG: Term mode
I2C_WriteByte(0x72, 0xA1, 0xFC); // Disable internal Mobile HD driver
I2C_WriteByte(0x72, 0xA3, 0xF9); // SIMG: Output Swing default EB
I2C_WriteByte(0x72, 0xA6, 0x0C); // SIMG: Swing Offset
I2C_WriteByte(0x72, 0x2B, 0x01); // Enable HDCP Compliance workaround
// CBUS & Discovery
ReadModifyWriteTPI(0x90, SI_BIT_3 | SI_BIT_2, SI_BIT_3); // CBUS discovery cycle time for each drive and float = 150us
I2C_WriteByte(0x72, 0x91, 0xE5); // Skip RGND detection
I2C_WriteByte(0x72, 0x94, 0x66); // 1.8V CBUS VTH & GND threshold
//set bit 2 and 3, which is Initiator Timeout
I2C_WriteByte(CBUS_SLAVE_ADDR, 0x31, I2C_ReadByte(CBUS_SLAVE_ADDR, 0x31) | 0x0c);
// original 3x config
I2C_WriteByte(0x72, 0xA5, 0x80); // SIMG: RGND Hysterisis, 3x mode for Beast
I2C_WriteByte(0x72, 0x95, 0x31); // RGND & single discovery attempt (RGND blocking)
I2C_WriteByte(0x72, 0x96, 0x22); // use 1K and 2K setting
ReadModifyWriteTPI(0x95, SI_BIT_6, SI_BIT_6); // Force USB ID switch to open
WriteByteTPI(0x92, 0x46); // Force MHD mode
WriteByteTPI(0x93, 0xDC); // Disable CBUS pull-up during RGND measurement
ReadModifyWriteTPI(0x79, SI_BIT_1 | SI_BIT_2, 0); //daniel test...MHL_INT
delay_ms(25);
ReadModifyWriteTPI(0x95, SI_BIT_6, 0x00); // Release USB ID switch
I2C_WriteByte(0x72, 0x90, 0x27); // Enable CBUS discovery
InitCBusRegs();
I2C_WriteByte(0x72, 0x05, ASR_VALUE); // Enable Auto soft reset on SCDT = 0
I2C_WriteByte(0x72, 0x0D, 0x1C); // HDMI Transcode mode enable
}
void set_mhd_power_active_mode(void)
{
ReadModifyWriteTPI(TPI_DEVICE_POWER_STATE_CTRL_REG, TX_POWER_STATE_MASK, 0x00);
}
void enable_mhd_tx(void)
{
ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG, TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE);
}
static void InitReleaseUsbIdSwitchOpen (void)
{
delay_ms(25);
ReadModifyWriteTPI(0x95, SI_BIT_6, 0x00); // Release USB ID switch
ReadModifyWriteTPI(0x90, SI_BIT_0, SI_BIT_0); // Enable CBUS discovery
}
static void EnableInterrupts(uint8_t Interrupt_Pattern)
{
ReadModifyWriteTPI(0x3D,Interrupt_Pattern,Interrupt_Pattern);
ReadModifyWriteTPI(0x3C,Interrupt_Pattern,Interrupt_Pattern);
}
static void EnableInterrupts (void)
{
ReadModifyWriteTPI(TPI_INTERRUPT_ENABLE_REG, RECEIVER_SENSE_EVENT_MASK, RECEIVER_SENSE_EVENT_MASK);
WriteIndexedRegister(INDEXED_PAGE_0, 0x75, SI_BIT_5); // Enable
}
void RAPContentOn (void)
{
ReadModifyWriteTPI(0x1A, BIT_3, 0x00);
}
void RAPContentOff (void)
{
ReadModifyWriteTPI(0x1A, BIT_3, 0x08);
}
void DisableInterrupts (void)
{
ReadModifyWriteTPI(TPI_INTERRUPT_ENABLE_REG, RECEIVER_SENSE_EVENT_MASK, 0x00);
}
void sii9234_enable_interrupts(void)
{
ReadModifyWriteTPI(TPI_INTERRUPT_ENABLE_REG, HOT_PLUG_EVENT_MASK, HOT_PLUG_EVENT_MASK);
WriteIndexedRegister(INDEXED_PAGE_0, 0x75, SI_BIT_5); // Enable
}
void sii9234_initial_registers_set(void)
{
printk ("==[SIMG] sii9234_initial_registers_set Start ==\n");
#if 0 //old cable
// Power Up
I2C_WriteByte(0x7A, 0x3D, 0x3F); // Power up CVCC 1.2V core
I2C_WriteByte(0x92, 0x11, 0x01); // Enable TxPLL Clock
I2C_WriteByte(0x92, 0x12, 0x15); // Enable Tx Clock Path & Equalizer
I2C_WriteByte(0x72, 0x08, 0x35); // Power Up TMDS Tx Core
// Analog PLL Control
I2C_WriteByte(0x92, 0x17, 0x03); // PLL Calrefsel
I2C_WriteByte(0x92, 0x1A, 0x20); // VCO Cal
I2C_WriteByte(0x92, 0x22, 0x8A); // Auto EQ
I2C_WriteByte(0x92, 0x23, 0x6A); // Auto EQ
I2C_WriteByte(0x92, 0x24, 0xAA); // Auto EQ
I2C_WriteByte(0x92, 0x25, 0xCA); // Auto EQ
I2C_WriteByte(0x92, 0x26, 0xEA); // Auto EQ
I2C_WriteByte(0x92, 0x4C, 0xA0); // Manual zone control
I2C_WriteByte(0x92, 0x4D, 0x00); // PLL Mode Value
I2C_WriteByte(0x72, 0x80, 0x14); // Enable Rx PLL Clock Value
I2C_WriteByte(0x92, 0x45, 0x44); // Rx PLL BW value from I2C
I2C_WriteByte(0x92, 0x31, 0x0A); // Rx PLL BW ~ 4MHz
I2C_WriteByte(0x72, 0xA1, 0xFC); // Disable internal Mobile HD driver
I2C_WriteByte(0x72, 0xA3, 0xFF); //AMP
I2C_WriteByte(0x72, 0x2B, 0x01); // Enable HDCP Compliance workaround
I2C_WriteByte(0x72, 0x91, 0xE5); // Skip RGND detection
I2C_WriteByte(0x72, 0xA5, 0x00); // RGND Hysterisis.
I2C_WriteByte(0x72, 0x90, 0x27); // Enable CBUS discovery
//I2C_WriteByte(0x72, 0x05, ASR_VALUE); // Enable Auto soft reset on SCDT = 0
I2C_WriteByte(0x72, 0x0D, 0x1C); // HDMI Transcode mode enable
WriteByteTPI(TPI_ENABLE, 0x00);
delay_ms(100);
WriteIndexedRegister(INDEXED_PAGE_0, 0xA0, 0x10);
delay_ms(100);
ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG, TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE);
#endif
#if 0 //test pattern generate
WriteByteTPI(0xBC, 0x81);
I2C_WriteByte(0x72, 0xBD, 0x01); // Enable Auto soft reset on SCDT = 0
I2C_WriteByte(0x72, 0xBB, 0x1D);
#endif
#if 0 //new MHL cable
// Power Up
I2C_WriteByte(0x7A, 0x3D, 0x3F); // Power up CVCC 1.2V core
//I2C_WriteByte(0x7A, 0x3D, 0x37); // Power up CVCC 1.2V core
I2C_WriteByte(0x92, 0x11, 0x01); // Enable TxPLL Clock
I2C_WriteByte(0x92, 0x12, 0x15); // Enable Tx Clock Path & Equalizer
I2C_WriteByte(0x72, 0x08, 0x35); // Power Up TMDS Tx Core
//I2C_WriteByte(0x72, 0x08, 0x37); // Power Up TMDS Tx Core
// Analog PLL Control
I2C_WriteByte(0x92, 0x17, 0x03); // PLL Calrefsel
I2C_WriteByte(0x92, 0x1A, 0x20); // VCO Cal
I2C_WriteByte(0x92, 0x22, 0x8A); // Auto EQ
I2C_WriteByte(0x92, 0x23, 0x6A); // Auto EQ
I2C_WriteByte(0x92, 0x24, 0xAA); // Auto EQ
I2C_WriteByte(0x92, 0x25, 0xCA); // Auto EQ
I2C_WriteByte(0x92, 0x26, 0xEA); // Auto EQ
I2C_WriteByte(0x92, 0x4C, 0xA0); // Manual zone control
//I2C_WriteByte(0x92, 0x1C, 0x11); //daniel RX0_offset test
//I2C_WriteByte(0x92, 0x1D, 0x11); //daniel RX1_offset test
//I2C_WriteByte(0x92, 0x1E, 0x11); //daniel RX2_offset test
I2C_WriteByte(0x92, 0x4D, 0x00); // PLL Mode Value
I2C_WriteByte(0x72, 0x80, 0x14); // Enable Rx PLL Clock Value
//I2C_WriteByte(0x72, 0x80, 0x24); // Enable Rx PLL Clock Value
//I2C_WriteByte(0x72, 0x80, 0x34); // Enable Rx PLL Clock Value
I2C_WriteByte(0x92, 0x45, 0x44); // Rx PLL BW value from I2C
I2C_WriteByte(0x92, 0x31, 0x0A); // Rx PLL BW ~ 4MHz
I2C_WriteByte(0x72, 0xA0, 0xD0);
I2C_WriteByte(0x72, 0xA1, 0xFC); // Disable internal Mobile HD driver
I2C_WriteByte(0x72, 0xA3, 0xFF);
I2C_WriteByte(0x72, 0x2B, 0x01); // Enable HDCP Compliance workaround
// CBUS & Discovery
//ReadModifyWriteTPI(0x90, BIT_3 | BIT_2, BIT_3); // CBUS discovery cycle time for each drive and float = 150us
I2C_WriteByte(0x72, 0x91, 0xE5); // Skip RGND detection
I2C_WriteByte(0x72, 0x94, 0x66); // 1.8V CBUS VTH & GND threshold
//set bit 2 and 3, which is Initiator Timeout
//I2C_WriteByte(CBUS_SLAVE_ADDR, 0x31, I2C_ReadByte(CBUS_SLAVE_ADDR, 0x31) | 0x0c);
I2C_WriteByte(0x72, 0xA5, 0x00); // RGND Hysterisis.
I2C_WriteByte(0x72, 0x95, 0x31); // RGND & single discovery attempt (RGND blocking)
I2C_WriteByte(0x72, 0x96, 0x22); // use 1K and 2K setting
ReadModifyWriteTPI(0x95, SI_BIT_6, SI_BIT_6); // Force USB ID switch to open
WriteByteTPI(0x92, 0x46); // Force MHD mode
WriteByteTPI(0x93, 0xDC); // Disable CBUS pull-up during RGND measurement
//old cable
//WriteByteTPI(0x92, 0x86); // Force MHD mode
//WriteByteTPI(0x93, 0xCC); // Disable CBUS pull-up during RGND measurement
delay_ms(25);
ReadModifyWriteTPI(0x95, SI_BIT_6, 0x00); // Release USB ID switch
I2C_WriteByte(0x72, 0x90, 0x27); // Enable CBUS discovery
//InitCBusRegs();
I2C_WriteByte(0x72, 0x05, 0x04); // Enable Auto soft reset on SCDT = 0
I2C_WriteByte(0x72, 0x0D, 0x1C); // HDMI Transcode mode enable
WriteByteTPI(TPI_ENABLE, 0x00);
delay_ms(100);
WriteIndexedRegister(INDEXED_PAGE_0, 0xA0, 0x10);
//WriteByteCBUS(0x07, DDC_XLTN_TIMEOUT_MAX_VAL | 0x0E); // Increase DDC translation layer timer (burst mode)
//WriteByteCBUS(0x47, 0x03);
//WriteByteCBUS(0x21, 0x01); // Heartbeat Disable
delay_ms(100);
ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG, TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE);
#endif
#if 1 //0607 update
// Power Up
I2C_WriteByte(0x7A, 0x3D, 0x3F); // Power up CVCC 1.2V core
I2C_WriteByte(0x92, 0x11, 0x01); // Enable TxPLL Clock
I2C_WriteByte(0x92, 0x12, 0x15); // Enable Tx Clock Path & Equalizer
I2C_WriteByte(0x72, 0x08, 0x35); // Power Up TMDS Tx Core
I2C_WriteByte(0x92, 0x00, 0x00); // SIMG: correcting HW default
I2C_WriteByte(0x92, 0x13, 0x60); // SIMG: Set termination value
I2C_WriteByte(0x92, 0x14, 0xF0); // SIMG: Change CKDT level
I2C_WriteByte(0x92, 0x4B, 0x06); // SIMG: Correcting HW default
// Analog PLL Control
I2C_WriteByte(0x92, 0x17, 0x07); // SIMG: PLL Calrefsel
I2C_WriteByte(0x92, 0x1A, 0x20); // VCO Cal
I2C_WriteByte(0x92, 0x22, 0xE0); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x23, 0xC0); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x24, 0xA0); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x25, 0x80); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x26, 0x60); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x27, 0x40); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x28, 0x20); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x29, 0x00); // SIMG: Auto EQ
I2C_WriteByte(0x92, 0x4D, 0x02); // SIMG: PLL Mode Value (order is important)
I2C_WriteByte(0x92, 0x4C, 0xA0); // Manual zone control
I2C_WriteByte(0x72, 0x80, 0x14); // Enable Rx PLL Clock Value
I2C_WriteByte(0x92, 0x31, 0x0B); // SIMG: Rx PLL BW value from I2C BW ~ 4MHz
I2C_WriteByte(0x92, 0x45, 0x06); // SIMG: DPLL Mode
I2C_WriteByte(0x72, 0xA0, 0x10); // SIMG: Term mode
I2C_WriteByte(0x72, 0xA1, 0xFC); // Disable internal Mobile HD driver
I2C_WriteByte(0x72, 0xA3, 0xEB); // SIMG: Output Swing
I2C_WriteByte(0x72, 0xA6, 0x0C); // SIMG: Swing Offset
I2C_WriteByte(0x72, 0x2B, 0x01); // Enable HDCP Compliance workaround
// CBUS & Discovery
//ReadModifyWriteTPI(0x90, BIT_3 | BIT_2, BIT_3); // CBUS discovery cycle time for each drive and float = 150us
I2C_WriteByte(0x72, 0x91, 0xE5); // Skip RGND detection
I2C_WriteByte(0x72, 0x94, 0x66); // 1.8V CBUS VTH & GND threshold
//set bit 2 and 3, which is Initiator Timeout
//I2C_WriteByte(CBUS_SLAVE_ADDR, 0x31, I2C_ReadByte(CBUS_SLAVE_ADDR, 0x31) | 0x0c);
I2C_WriteByte(0x72, 0xA5, 0x80); // SIMG: RGND Hysterisis, 3x mode for Beast
I2C_WriteByte(0x72, 0x95, 0x31); // RGND & single discovery attempt (RGND blocking)
I2C_WriteByte(0x72, 0x96, 0x22); // use 1K and 2K setting
ReadModifyWriteTPI(0x95, SI_BIT_6, SI_BIT_6); // Force USB ID switch to open
//WriteByteTPI(0x92, 0x46); // Force MHD mode
//WriteByteTPI(0x93, 0xDC); // Disable CBUS pull-up during RGND measurement
//old cable
WriteByteTPI(0x92, 0x86); // Force MHD mode
WriteByteTPI(0x93, 0xCC); // Disable CBUS pull-up during RGND measurement
delay_ms(25);
ReadModifyWriteTPI(0x95, SI_BIT_6, 0x00); // Release USB ID switch
I2C_WriteByte(0x72, 0x90, 0x27); // Enable CBUS discovery
//InitCBusRegs();
I2C_WriteByte(0x72, 0x05, 0x04); // Enable Auto soft reset on SCDT = 0
I2C_WriteByte(0x72, 0x0D, 0x1C); // HDMI Transcode mode enable
WriteByteTPI(TPI_ENABLE, 0x00);
delay_ms(100);
WriteIndexedRegister(INDEXED_PAGE_0, 0xA0, 0x10);
WriteByteCBUS(0x07, DDC_XLTN_TIMEOUT_MAX_VAL | 0x0E); // Increase DDC translation layer timer (burst mode)
WriteByteCBUS(0x47, 0x03);
WriteByteCBUS(0x21, 0x01); // Heartbeat Disable
delay_ms(100);
ReadModifyWriteTPI(TPI_SYSTEM_CONTROL_DATA_REG, TMDS_OUTPUT_CONTROL_MASK, TMDS_OUTPUT_CONTROL_ACTIVE);
#endif
printk ("==[SIMG] sii9234_initial_registers_set END ==\n");
}
static void sii9234_register_init(void)
{
/*Power Up*/
I2C_WriteByte(0x7A, 0x3D, 0x3F); /* Power up CVCC 1.2V core */
I2C_WriteByte(0x92, 0x11, 0x01); /* Enable TxPLL Clock*/
I2C_WriteByte(0x92, 0x12, 0x15); /* Enable Tx Clock Path & Equalizer*/
I2C_WriteByte(0x72, 0x08, 0x35); /* Power Up TMDS Tx Core*/
I2C_WriteByte(0x92, 0x00, 0x00); /* SIMG: correcting HW default*/
I2C_WriteByte(0x92, 0x13, 0x60); /* SIMG: Set termination value*/
I2C_WriteByte(0x92, 0x14, 0xF0); /* SIMG: Change CKDT level*/
I2C_WriteByte(0x92, 0x4B, 0x06); /* SIMG: Correcting HW default*/
/*Analog PLL Control*/
I2C_WriteByte(0x92, 0x17, 0x07); /* SIMG: PLL Calrefsel*/
I2C_WriteByte(0x92, 0x1A, 0x20); /* VCO Cal*/
I2C_WriteByte(0x92, 0x22, 0xE0); /* SIMG: Auto EQ*/
I2C_WriteByte(0x92, 0x23, 0xC0); /* SIMG: Auto EQ*/
I2C_WriteByte(0x92, 0x24, 0xA0); /* SIMG: Auto EQ*/
I2C_WriteByte(0x92, 0x25, 0x80); /* SIMG: Auto EQ*/
I2C_WriteByte(0x92, 0x26, 0x60); /* SIMG: Auto EQ*/
I2C_WriteByte(0x92, 0x27, 0x40); /* SIMG: Auto EQ*/
I2C_WriteByte(0x92, 0x28, 0x20); /* SIMG: Auto EQ*/
I2C_WriteByte(0x92, 0x29, 0x00); /* SIMG: Auto EQ*/
/*I2C_WriteByte(0x92, 0x10, 0xF1);*/
I2C_WriteByte(0x92, 0x4D, 0x02); /* SIMG: PLL Mode Value (order is important)*/
/*I2C_WriteByte(0x92, 0x4D, 0x00);*/
I2C_WriteByte(0x92, 0x4C, 0xA0); /* Manual zone control*/
/*I2C_WriteByte(0x72, 0x80, 0x14);*/ /* Enable Rx PLL Clock Value*/
I2C_WriteByte(0x72, 0x80, 0x34);
I2C_WriteByte(0x92, 0x31, 0x0B); /* SIMG: Rx PLL BW value from I2C BW ~ 4MHz*/
I2C_WriteByte(0x92, 0x45, 0x06); /* SIMG: DPLL Mode*/
I2C_WriteByte(0x72, 0xA0, 0xD0); /* SIMG: Term mode*/
I2C_WriteByte(0x72, 0xA1, 0xFC); /* Disable internal Mobile HD driver*/
I2C_WriteByte(0x72, 0xA3, 0xEB); /* SIMG: Output Swing default EB*/
I2C_WriteByte(0x72, 0xA6, 0x00); /* SIMG: Swing Offset*/
I2C_WriteByte(0x72, 0x2B, 0x01); /* Enable HDCP Compliance workaround*/
/*CBUS & Discovery*/
ReadModifyWriteTPI(0x90, SI_BIT_3 | SI_BIT_2, SI_BIT_3);/* CBUS discovery cycle time for each drive and float = 150us*/
I2C_WriteByte(0x72, 0x91, 0xE5); /* Skip RGND detection*/
I2C_WriteByte(0x72, 0x94, 0x66); /* 1.8V CBUS VTH & GND threshold*/
/*set bit 2 and 3, which is Initiator Timeout*/
I2C_WriteByte(CBUS_SLAVE_ADDR, 0x31, I2C_ReadByte(CBUS_SLAVE_ADDR, 0x31) | 0x0c);
/*original 3x config*/
I2C_WriteByte(0x72, 0xA5, 0x80); /* SIMG: RGND Hysterisis, 3x mode for Beast*/
I2C_WriteByte(0x72, 0x95, 0x31); /* RGND & single discovery attempt (RGND blocking)*/
I2C_WriteByte(0x72, 0x96, 0x22); /* use 1K and 2K setting*/
ReadModifyWriteTPI(0x95, SI_BIT_6, SI_BIT_6); /* Force USB ID switch to open*/
WriteByteTPI(0x92, 0x46); /* Force MHD mode*/
WriteByteTPI(0x93, 0xDC); /* Disable CBUS pull-up during RGND measurement*/
ReadModifyWriteTPI(0x79, SI_BIT_1 | SI_BIT_2, 0); /*daniel test...MHL_INT*/
mdelay(25);
ReadModifyWriteTPI(0x95, SI_BIT_6, 0x00); /* Release USB ID switch*/
I2C_WriteByte(0x72, 0x90, 0x27); /* Enable CBUS discovery*/
InitCBusRegs();
I2C_WriteByte(0x72, 0x05, ASR_VALUE); /* Enable Auto soft reset on SCDT = 0*/
I2C_WriteByte(0x72, 0x0D, 0x1C); /* HDMI Transcode mode enable*/
}
