/**
* FchSataDriveDetectionFpga
*
* @param[in] LocalCfgPtr
* @param[in] Bar5
*
*/
VOID
FchSataDriveDetectionFpga (
IN FCH_DATA_BLOCK *LocalCfgPtr,
IN UINT32 *Bar5
)
{
UINT32 SataBarFpgaInfo;
UINT8 PortNum;
UINT8 SataFpaPortType;
UINT16 IoBase;
UINT32 SataFpgaLoopVarWord;
AMD_CONFIG_PARAMS *StdHeader;
StdHeader = LocalCfgPtr->StdHeader;
TRACE ((DMSG_FCH_TRACE, "FCH - Entering sata drive detection procedure\n\n"));
TRACE ((DMSG_FCH_TRACE, "SATA BAR5 is %X \n", *pBar5));
for ( PortNum = 0; PortNum < 4; PortNum++ ) {
ReadMem (*Bar5 + FCH_SATA_BAR5_REG128 + PortNum * 0x80, AccWidthUint32, &SataBarFpgaInfo);
if ( ( SataBarFpgaInfo & 0x0F ) == 0x03 ) {
if ( PortNum & BIT0 ) {
//this port belongs to secondary channel
ReadPci (((UINT32) (SATA_BUS_DEV_FUN_FPGA << 16) + FCH_SATA_REG18), AccWidthUint16, &IoBase);
} else {
//this port belongs to primary channel
ReadPci (((UINT32) (SATA_BUS_DEV_FUN_FPGA << 16) + FCH_SATA_REG10), AccWidthUint16, &IoBase);
}
//if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them
if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) {
IoBase = ( (0x170) | ((UINT16) ( (~((UINT8) (PortNum & BIT0) << 7)) & 0x80 )) );
}
if ( PortNum & BIT1 ) {
//this port is slave
SataFpaPortType = 0xB0;
} else {
//this port is master
SataFpaPortType = 0xA0;
}
IoBase &= 0xFFF8;
LibAmdIoWrite (AccessWidth8, IoBase + 6, &SataFpaPortType, StdHeader);
//Wait in loop for 30s for the drive to become ready
for ( SataFpgaLoopVarWord = 0; SataFpgaLoopVarWord < 300000; SataFpgaLoopVarWord++ ) {
LibAmdIoRead (AccessWidth8, IoBase + 7, &SataFpaPortType, StdHeader);
if ( (SataFpaPortType & 0x88) == 0 ) {
break;
}
FchStall (100, StdHeader);
}
}
}
}
/**
* FchGppSetAspm - Set GPP ASPM
*
*
* @param[in] PciAddress PCI Address.
* @param[in] LxState Lane State.
* @param[in] StdHeader
*
*/
VOID
FchGppSetAspm (
IN UINT32 PciAddress,
IN UINT8 LxState,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 PcieCapOffset;
UINT8 DeviceType;
PcieCapOffset = FchFindPciCap (PciAddress, PCIE_CAP_ID, StdHeader);
if (PcieCapOffset) {
//
// Read link capabilities register (0x0C[11:10] - ASPM support)
//
ReadPci (PciAddress + PcieCapOffset + 0x0D, AccessWidth8, &DeviceType, StdHeader);
if (DeviceType & BIT2) {
DeviceType = (DeviceType >> 2) & (BIT1 + BIT0);
//
// Set ASPM state in link control register
//
RwPci (PciAddress + PcieCapOffset + 0x10, AccessWidth8, 0xffffffff, LxState & DeviceType, StdHeader);
}
}
EFI_STATUS
EFIAPI
AmdSmiEinjErrorInjectionSetup (
IN OUT VOID
)
{
UINT8 PortId;
UINT32 Value32;
EFI_STATUS Status;
AMD_CONFIG_PARAMS StdHeader;
Status = EFI_SUCCESS;
for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
ReadPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x00), AccessWidth32, &Value32, &StdHeader);
if (Value32 != 0xffffffff) {
ACPIMMIO8 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x60)) |= 0x0F;
ACPIMMIO8 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x17C)) |= 0x07;
ACPIMMIO8 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x74)) |= 0x07;
ACPIMMIO16 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x04)) |= 0x0100;
ACPIMMIO8 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x3E)) |= 0x02;
ACPIMMIO32 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x158)) &= 0xffc22fef;
ACPIMMIO32 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x15C)) &= 0xffc22fef;
ACPIMMIO16 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x164)) &= 0xce3f;
ACPIMMIO16 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x168)) |= 0x0140;
}
}
RwAlink (FCH_ABCFG_REGF4 | (UINT32) (ABCFG << 29), ~BIT4, 0x00, &StdHeader);
return Status;
}
EFI_STATUS
EFIAPI
AmdSmiEinjClrStatus (
IN OUT VOID
)
{
UINT8 PortId;
UINT32 Value32;
EFI_STATUS Status;
AMD_CONFIG_PARAMS StdHeader;
Status = EFI_SUCCESS;
for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
ReadPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x00), AccessWidth32, &Value32, &StdHeader);
if (Value32 != 0xffffffff) {
ACPIMMIO8 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x62)) |= 0x0f;
ACPIMMIO32 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x154)) |= 0x003ff030;
ACPIMMIO16 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x160)) |= 0x31c0;
ACPIMMIO8 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x180)) |= 0x7f;
ACPIMMIO16 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x06)) |= 0x4000;
}
}
RwAlink (0x104C | (UINT32) (ABCFG << 29), 0xffffff0f, 0xf0, &StdHeader);
RwMem (ACPI_MMIO_BASE + SMI_BASE + 0x3C, AccessWidth8, 0x00, BIT2);
return Status;
}
/**
* FchSataBar5settingFpga
*
* @param[in] LocalCfgPtr
* @param[in] Bar5
*
*/
VOID
FchSataBar5settingFpga (
IN FCH_DATA_BLOCK *LocalCfgPtr,
IN UINT32 *Bar5
)
{
UINT8 Value;
//Get BAR5 value
ReadPci (((SATA_BUS_DEV_FUN_FPGA << 16) + FCH_SATA_REG24), AccWidthUint32, Bar5);
//Assign temporary BAR if is not already assigned
if ( (*Bar5 == 0) || (*Bar5 == - 1) ) {
//assign temporary BAR5
if ( (LocalCfgPtr->Sata.TempMMIO == 0) || (LocalCfgPtr->Sata.TempMMIO == - 1) ) {
*Bar5 = 0xFEC01000;
} else {
*Bar5 = LocalCfgPtr->Sata.TempMMIO;
}
WritePci (((SATA_BUS_DEV_FUN_FPGA << 16) + FCH_SATA_REG24), AccWidthUint32, Bar5);
}
//Clear Bits 9:0
*Bar5 = *Bar5 & 0xFFFFFC00;
Value = 0x07;
WritePci (((SATA_BUS_DEV_FUN_FPGA << 16) + 0x04), AccWidthUint8, &Value);
WritePci (((PCIB_BUS_DEV_FUN << 16) + 0x04), AccWidthUint8, &Value);
}
EFI_STATUS
EFIAPI
AmdSmiEinjSystemContextRestore (
IN OUT VOID
)
{
UINT8 PortId;
UINT32 Value32;
EFI_STATUS Status;
AMD_CONFIG_PARAMS StdHeader;
Status = EFI_SUCCESS;
if ((mEinjData != NULL) && (mEinjData->Valid)) {
for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
ReadPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x00), AccessWidth32, &Value32, &StdHeader);
if (Value32 != 0xffffffff) {
ACPIMMIO16 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x04)) = mEinjData->SystemContext[PortId].CmdReg;
ACPIMMIO16 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x3E)) = mEinjData->SystemContext[PortId].BridgeCntlReg;
ACPIMMIO16 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x60)) = mEinjData->SystemContext[PortId].DeviceStatusReg;
ACPIMMIO16 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x74)) = mEinjData->SystemContext[PortId].RootCntlReg;
ACPIMMIO32 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x158)) = mEinjData->SystemContext[PortId].PcieUncorrErrMaskReg;
ACPIMMIO32 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x15C)) = mEinjData->SystemContext[PortId].PcieUncorrErrSeverityReg;
ACPIMMIO32 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x164)) = mEinjData->SystemContext[PortId].PcieCorrErrMaskReg;
ACPIMMIO32 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x168)) = mEinjData->SystemContext[PortId].PcieAdvErrCapCntlReg;
ACPIMMIO32 (PCIE_ADDRESS (mEinjData->PcieBaseAddress, 0, GPP_DEV_NUM, PortId, 0x174)) = mEinjData->SystemContext[PortId].PcieRootErrCmdReg;
}
}
mEinjData->Valid = FALSE;
}
return Status;
}
/**
* FchPeiOscOutClockSel - Set Osc Out Clock Select Service
*
* @param[in] This Caller environment structure
* @param[in] OscOut1ClockSel Enable Set Osc Out Clock1 Select Service
* @param[in] OscOut1ClockFreq Set Osc Out Clock1 Frequency
*
*/
VOID
FchPeiOscOutClockSel (
IN AMD_FCH_PEI_AUX_PPI *This,
IN BOOLEAN OscOut1ClockSel,
IN FCH_OSC_OUT_CLOCK_SEL OscOut1ClockFreq
)
{
FCH_PEI_AUX_PRIVATE *FchAuxPrivate;
EFI_PEI_SERVICES **PeiServices;
AMD_CONFIG_PARAMS *StdHeader;
UINT32 MmioAddr;
UINT8 Value;
UINT8 OscKabiniSelect;
FchAuxPrivate = FCH_PEI_PRIVATE_FROM_THIS (This);
StdHeader = &FchAuxPrivate->StdHdr;
PeiServices = ( EFI_PEI_SERVICES** ) (StdHeader->AltImageBasePtr);
if ( OscOut1ClockSel ) {
MmioAddr = LibFchGetAcpiMmio ( PeiServices );
ReadPci (PCI_ADDRESS (0, FCH_ISA_DEV, 0, 0x08), AccessWidth8, &Value, StdHeader);
OscKabiniSelect = 0;
if ( OscOut1ClockFreq == KABINI_OSC_OUT_CLOCK_SEL_48MHz ) {
OscKabiniSelect = 0;
}
if ( OscOut1ClockFreq == KABINI_OSC_OUT_CLOCK_SEL_25MHz ) {
OscKabiniSelect = 1;
}
LibFchMemRMW8 ( PeiServices, MmioAddr + MISC_BASE + FCH_MISC_REG28 + 2, 0xF8, OscKabiniSelect);
}
}
/**
* CheckAvalonRevisionA0 - Check Avalon Revision A0
*
*
* @param[in] StdHeader
*
*/
BOOLEAN
CheckAvalonRevisionA0 (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 FchChipSetRevision;
ReadPci ((SMBUS_BUS_DEV_FUN << 16) + FCH_CFG_REG08, AccessWidth8, &FchChipSetRevision, StdHeader);
return (FCH_AVALONA0 == FchChipSetRevision);
}
/**
* GetFchRevision - Get FCH revision
*
*
* @param[in] StdHeader
*
*/
UINT8
GetFchRevision (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 FchChipSetRevision;
ReadPci ((SMBUS_BUS_DEV_FUN << 16) + FCH_CFG_REG08, AccessWidth8, &FchChipSetRevision, StdHeader);
return FchChipSetRevision;
}
/**
* ReadFchChipsetRevision - Get FCH chipset revision
*
*
* @param[in] StdHeader
*
*/
UINT8
ReadFchChipsetRevision (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 FchChipSetRevision;
UINT8 FchMiscRegister;
ReadPmio (FCH_PMIOA_REGC8 + 1, AccessWidth8, &FchMiscRegister, StdHeader);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8 + 1, AccessWidth8, ~(UINT32) BIT7, 0);
ReadPci ((SMBUS_BUS_DEV_FUN << 16) + FCH_CFG_REG08, AccessWidth8, &FchChipSetRevision, StdHeader);
WritePmio (FCH_PMIOA_REGC8 + 1, AccessWidth8, &FchMiscRegister, StdHeader);
return FchChipSetRevision;
}
/**
* ExitEcConfig - Force EC exit Config mode
*
*
*
*
*/
VOID
ExitEcConfig (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT16 EcIndexPortDword;
UINT8 FchEcData8;
ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4, AccessWidth16, &EcIndexPortDword, StdHeader);
EcIndexPortDword &= ~(BIT0);
FchEcData8 = 0xA5;
LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &FchEcData8, StdHeader);
}
/**
* FchInitEnvSataIde - Config SATA IDE controller before PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvSataIde (
IN VOID *FchDataPtr
)
{
UINT8 ChannelByte;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
UINT32 Bar5;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
SataBar5setting (LocalCfgPtr, &Bar5);
//
// Class code
//
if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0xFF, 0x01018A00, StdHeader);
} else {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0xFF, 0x01018F00, StdHeader);
}
//
// Device ID
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, KERN_FCH_SATA_DID, StdHeader);
//
// SSID
//
if (LocalCfgPtr->Sata.SataIdeSsid != NULL ) {
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Sata.SataIdeSsid, StdHeader);
}
//
// Sata IDE Channel configuration
//
ChannelByte = 0x00;
ReadPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, &ChannelByte, StdHeader);
ChannelByte &= 0xCF;
if ( LocalCfgPtr->Sata.SataDisUnusedIdePChannel ) {
ChannelByte |= 0x10;
}
if ( LocalCfgPtr->Sata.SataDisUnusedIdeSChannel ) {
ChannelByte |= 0x20;
}
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG04), AccessWidth32, 0xFFFFFFFF, 0x07, StdHeader);
// Clear AHCI Enable during POST time. DE is investigating when/how to restore this bit before goes to OS boot.
RwMem ((Bar5 + FCH_SATA_BAR5_REG04), AccessWidth32, ~(UINT32) (BIT31), 0);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG04), AccessWidth32, 0xFFFFFFFF, 0x00, StdHeader);
WritePci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, &ChannelByte, StdHeader);
}
/**
* WriteEc8 - Write date into EC register
*
*
*
* @param[in] Address - EC Register Offset Value
* @param[in] Value - Write Data Buffer
* @param[in] StdHeader
*
*/
VOID
WriteEc8 (
IN UINT8 Address,
IN UINT8 *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT16 EcIndexPortDword;
ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4, AccessWidth16, &EcIndexPortDword, StdHeader);
EcIndexPortDword &= ~(BIT0);
LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &Address, StdHeader);
LibAmdIoWrite (AccessWidth8, EcIndexPortDword + 1, Value, StdHeader);
}
/**
* EhciSetDebugPort - Config Ehci Debug Port
*
* @param[in] Value Controller PCI config address (bus# + device# + function#)
* @param[in] FchDataPtr Fch configuration structure pointer.
* @param[in] DebugPortSel Debug port selector.
*/
VOID
EhciSetDebugPort (
IN UINT32 Value,
IN FCH_DATA_BLOCK *FchDataPtr,
IN UINT8 DebugPortSel
)
{
AMD_CONFIG_PARAMS *StdHeader;
UINT16 UsbLegacySupportControl;
UINT16 UsbLegacySupportStatus;
UINT16 UsbPciCommand;
StdHeader = FchDataPtr->StdHeader;
if (DebugPortSel == 0) {
return;
}
if (!FchDataPtr->Usb.EhciSimpleDebugPort) {
ReadPci ((UINT32) Value + FCH_EHCI_REGA4 + 2, AccessWidth16, &UsbLegacySupportStatus, StdHeader);
if ((UsbLegacySupportStatus & BIT14) == 0) {
return;
}
ReadPci ((UINT32) Value + FCH_EHCI_REGA4, AccessWidth16, &UsbLegacySupportControl, StdHeader);
if ((UsbLegacySupportControl & BIT14) == 0) {
return;
}
ReadPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth16, &UsbPciCommand, StdHeader);
if ((UsbPciCommand & BIT1) != 0) {
return;
}
}
DebugPortSel--;
DebugPortSel &= (BIT0 + BIT1);
RwPci ((UINT32) Value + FCH_EHCI_REG90 + 2, AccessWidth8, ~(UINT32) (BIT0 + BIT1), DebugPortSel, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG90, AccessWidth32, ~(UINT32) BIT18, BIT18, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REGA4, AccessWidth16, 0, BIT0 + BIT13, StdHeader);
}
/**
* FchInitEnvSataIde - Config SATA IDE controller before PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvSataIde (
IN VOID *FchDataPtr
)
{
UINT8 ChannelByte;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// Class code
//
if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0, 0x01018A40, StdHeader);
} else {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0, 0x01018F40, StdHeader);
}
//
// Device ID
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, FCH_SATA_DID, StdHeader);
//
// SSID
//
if (LocalCfgPtr->Sata.SataIdeSsid != NULL ) {
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Sata.SataIdeSsid, StdHeader);
}
//
// Sata IDE Channel configuration
//
ChannelByte = 0x00;
ReadPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, &ChannelByte, StdHeader);
ChannelByte &= 0xCF;
if ( LocalCfgPtr->Sata.SataDisUnusedIdePChannel ) {
ChannelByte |= 0x10;
}
if ( LocalCfgPtr->Sata.SataDisUnusedIdeSChannel ) {
ChannelByte |= 0x20;
}
WritePci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, &ChannelByte, StdHeader);
}
/**
* EnableEhciController - Assign resources and enable EHCI controllers
*
* @param[in] Value Controller PCI config address (bus# + device# + function#)
* @param[in] BarAddress Base address for Ehci controller
* @param[in] StdHeader AMD standard header config param
*/
VOID
EnableEhciController (
IN UINT32 Value,
IN UINT32 BarAddress,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Var;
WritePci ((UINT32) Value + FCH_EHCI_REG10, AccessWidth32, &BarAddress, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, BIT1 + BIT2, StdHeader);
ReadPci ((UINT32) Value + FCH_EHCI_REG10, AccessWidth32, &BarAddress, StdHeader);
if ( (BarAddress != - 1) && (BarAddress != 0) ) {
RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, BIT1, StdHeader);
Var = 0x00020F00;
WriteMem (BarAddress + FCH_EHCI_BAR_REGC0, AccessWidth32, &Var);
RwMem (BarAddress + FCH_EHCI_BAR_REGA4, AccessWidth32, 0xFF00FF00, 0x00400040);
RwMem (BarAddress + FCH_EHCI_BAR_REGBC, AccessWidth32, ~( BIT12 + BIT14), BIT12 + BIT14);
RwMem (BarAddress + FCH_EHCI_BAR_REGB0, AccessWidth32, ~BIT5, BIT5);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth16, ~BIT12, BIT12);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~BIT16, BIT16);
RwMem (BarAddress + FCH_EHCI_BAR_REGB4, AccessWidth32, ~BIT12, BIT12);
RwMem (BarAddress + FCH_EHCI_BAR_REGC4, AccessWidth32, (UINT32) (~ 0x00000f00), 0x00000200);
RwMem (BarAddress + FCH_EHCI_BAR_REGC0, AccessWidth32, (UINT32) (~ 0x0000ff00), 0x00000f00);
RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x01 << 6)), (UINT32) (0x01 << 6), StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x0F << 8)), (UINT32) (0x01 << 8), StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x0F << 12)), (UINT32) (0x01 << 12), StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x01 << 17)), (UINT32) (0x01 << 17), StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x01 << 21)), (UINT32) (0x01 << 21), StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x01 << 29)), (UINT32) (0x01 << 29), StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50 + 2, AccessWidth16, (UINT16)0xFFFF, BIT16 + BIT10, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54, AccessWidth32, ~ (BIT0 + (3 << 5) + (7 << 7)), 0x0000026b, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54, AccessWidth32, ~BIT4, BIT4, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54, AccessWidth32, ~BIT11, BIT11, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54, AccessWidth16, (UINT16)0x5FFF, BIT13 + BIT15, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50 + 2, AccessWidth16, ~BIT3, BIT3, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54 + 2, AccessWidth16, (UINT16)0xFFFC, BIT0 + BIT1, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54 + 2, AccessWidth16, (UINT16)0xFFFB, BIT2, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54 + 2, AccessWidth16, (UINT16)0xFFF7, BIT3, StdHeader);
}
}
/**
* FchSwInitGecBootRom - Config GEC Boot ROM by Platform define
* ROM address
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchSwInitGecBootRom (
IN VOID *FchDataPtr
)
{
VOID* GecRomAddress;
VOID* GecShadowRomAddress;
UINT32 Temp;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
if ( !LocalCfgPtr->Gec.PtrDynamicGecRomAddress == NULL ) {
GecRomAddress = LocalCfgPtr->Gec.PtrDynamicGecRomAddress;
GecShadowRomAddress = (VOID*) (UINTN) LocalCfgPtr->Gec.GecShadowRomBase;
FchCopyMem (GecShadowRomAddress, GecRomAddress, 0x100);
ReadPci ((GEC_BUS_DEV_FUN << 16) + FCH_GEC_REG10, AccessWidth32, &Temp, StdHeader);
Temp = Temp & 0xFFFFFFF0;
RwMem (Temp + FCH_GEC_INTERNAL_REG, AccessWidth32, 0, BIT0 + BIT29);
}
}
/**
* sataBar5setting - Config SATA BAR5
*
*
* @param[in] FchDataPtr - Fch configuration structure pointer.
* @param[in] *Bar5Ptr - SATA BAR5 buffer.
*
*/
VOID
SataBar5setting (
IN VOID *FchDataPtr,
IN UINT32 *Bar5Ptr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//Get BAR5 value
//
ReadPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG24), AccessWidth32, Bar5Ptr, StdHeader);
//
//Assign temporary BAR if is not already assigned
//
if ( (*Bar5Ptr == 0) || (*Bar5Ptr == - 1) ) {
//
//assign temporary BAR5
//
if ( (LocalCfgPtr->Sata.TempMmio == 0) || (LocalCfgPtr->Sata.TempMmio == - 1) ) {
*Bar5Ptr = 0xFEC01000;
} else {
*Bar5Ptr = LocalCfgPtr->Sata.TempMmio;
}
WritePci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG24), AccessWidth32, Bar5Ptr, StdHeader);
}
//
//Clear Bits 9:0
//
*Bar5Ptr = *Bar5Ptr & 0xFFFFFC00;
}
/**
* FchXhciInitIndirectReg - Config XHCI Indirect Registers
*
*
*
* @param[in] StdHeader AMD Standard Header
*
*/
VOID
FchXhciInitIndirectReg (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 DrivingStrength;
UINT32 Port;
UINT32 Register;
UINT32 RegValue;
UINT8 Index;
DrivingStrength = 0;
Port = 0;
//
// SuperSpeed PHY Configuration (adaptation mode setting)
//
RwXhciIndReg ( FCH_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021, StdHeader);
//
// SuperSpeed PHY Configuration (CR phase and frequency filter settings)
//
RwXhciIndReg ( FCH_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A, StdHeader);
//
// BLM Meaasge
//
RwXhciIndReg ( FCH_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000, StdHeader);
//
// xHCI USB 2.0 PHY Settings
// Step 1 is done by hardware default
// Step 2
for (Port = 0; Port < 4; Port ++) {
DrivingStrength = BIT2;
if (Port < 2) {
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, (Port << 13) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, (Port << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0E78, (Port << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000, StdHeader);
} else {
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, ((Port - 2) << 13) + DrivingStrength, StdHeader);
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, ((Port - 2) << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader);
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0E78, ((Port - 2) << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000, StdHeader);
}
}
// Step 3
RwXhciIndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)), StdHeader);
RwXhciIndReg ( FCH_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)), StdHeader);
}
/**
* FchInitResetXhciProgram - Config Xhci controller during
* Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitResetXhciProgram (
IN VOID *FchDataPtr
)
{
UINT8 IndexValue;
UINT32 ValueDword;
UINT8 ValueByte;
FCH_RESET_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader);
if ( ValueDword == (FCH_USB_XHCI_DID << 16) + FCH_USB_XHCI_VID) {
//
// First Xhci controller.
//
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader);
ValueDword = 0;
IndexValue = XHCI_REGISTER_BAR00;
ReadBiosram (IndexValue, AccessWidth32, &ValueDword, StdHeader);
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccessWidth32, &ValueDword, StdHeader);
IndexValue = XHCI_REGISTER_04H;
ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &ValueByte, StdHeader);
IndexValue = XHCI_REGISTER_0CH;
ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &ValueByte, StdHeader);
IndexValue = XHCI_REGISTER_3CH;
ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &ValueByte, StdHeader);
//
// Second Xhci controller.
//
ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader);
ValueDword = 0;
IndexValue = XHCI1_REGISTER_BAR00;
ReadBiosram (IndexValue, AccessWidth32, &ValueDword, StdHeader);
WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccessWidth32, &ValueDword, StdHeader);
IndexValue = XHCI1_REGISTER_04H;
ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &ValueByte, StdHeader);
IndexValue = XHCI1_REGISTER_0CH;
ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &ValueByte, StdHeader);
IndexValue = XHCI1_REGISTER_3CH;
ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &ValueByte, StdHeader);
}
}
/**
* FchInitLateUsbXhciProgram - Config USB3 controller before OS
* Boot
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateUsbXhciProgram (
IN VOID *FchDataPtr
)
{
UINT8 IndexValue;
UINT8 Value;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
if ( LocalCfgPtr->Usb.Xhci1Enable == TRUE ) {
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccessWidth8, &Value, StdHeader);
IndexValue = XHCI_REGISTER_BAR00;
WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x11, AccessWidth8, &Value, StdHeader);
IndexValue = XHCI_REGISTER_BAR01;
WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x12, AccessWidth8, &Value, StdHeader);
IndexValue = XHCI_REGISTER_BAR02;
WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x13, AccessWidth8, &Value, StdHeader);
IndexValue = XHCI_REGISTER_BAR03;
WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &Value, StdHeader);
IndexValue = XHCI_REGISTER_04H;
WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &Value, StdHeader);
IndexValue = XHCI_REGISTER_0CH;
WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &Value, StdHeader);
IndexValue = XHCI_REGISTER_3CH;
WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccessWidth8, &Value, StdHeader);
IndexValue = XHCI1_REGISTER_BAR00;
WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x11, AccessWidth8, &Value, StdHeader);
IndexValue = XHCI1_REGISTER_BAR01;
WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x12, AccessWidth8, &Value, StdHeader);
IndexValue = XHCI1_REGISTER_BAR02;
WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x13, AccessWidth8, &Value, StdHeader);
IndexValue = XHCI1_REGISTER_BAR03;
WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &Value, StdHeader);
IndexValue = XHCI1_REGISTER_04H;
WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &Value, StdHeader);
IndexValue = XHCI1_REGISTER_0CH;
WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &Value, StdHeader);
IndexValue = XHCI1_REGISTER_3CH;
WriteBiosram (IndexValue, AccessWidth8, &Value, StdHeader);
}
}
/**
* FchXhciInitIndirectReg - Config XHCI Indirect Registers
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchXhciInitIndirectReg (
IN FCH_DATA_BLOCK *FchDataPtr
)
{
UINT8 Index;
UINT32 DrivingStrength;
UINT32 Port;
UINT32 Register;
UINT32 RegValue;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
DrivingStrength = 0;
//
// SuperSpeed PHY Configuration (adaptation mode setting)
//
RwXhciIndReg ( FCH_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021, StdHeader);
//
// SuperSpeed PHY Configuration (CR phase and frequency filter settings)
//
RwXhciIndReg ( FCH_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A, StdHeader);
//
// BLM Meaasge
//
RwXhciIndReg ( FCH_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000, StdHeader);
//
// xHCI USB 2.0 PHY Settings
// Step 1 is done by hardware default
// Step 2
for (Port = 0; Port < 4; Port ++) {
DrivingStrength = (UINT32) (LocalCfgPtr->Usb.Xhci20Phy[Port]);
if (Port < 2) {
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
} else {
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + BIT12 + DrivingStrength, StdHeader);
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + DrivingStrength, StdHeader);
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + BIT12 + DrivingStrength, StdHeader);
}
}
// Step 3
RwXhciIndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)), StdHeader);
RwXhciIndReg ( FCH_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)), StdHeader);
// RPR 8.25 Clock Gating in PHY
for (Port = 0; Port < 4; Port ++) {
DrivingStrength = 0x1E4;
if (Port < 2) {
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
} else {
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, ((Port - 2) << 13) + BIT12 + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, ((Port - 2) << 13) + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, ((Port - 2) << 13) + BIT12 + DrivingStrength, StdHeader);
}
}
if ( ReadFchChipsetRevision ( StdHeader ) >= FCH_BOLTON ) {
// RRG 8.36 Enhance XHC LS Rise time
for (Port = 0; Port < 2; Port ++) {
DrivingStrength = 0x1C4;
RwXhciIndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + DrivingStrength, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
}
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(UINT32) (BIT23), BIT23);
// RPR 8.61 XHCI ISO device CRC false error detection
for (Port = 0; Port < 4; Port ++) {
if (Port < 2) {
ReadXhci0Phy (Port, (0x7 << 7), &DrivingStrength, StdHeader);
DrivingStrength &= 0x0000000F8;
DrivingStrength |= BIT0 + BIT2;
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + (0x7 << 7) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader);
} else {
ReadXhci1Phy ((Port - 2), (0x7 << 7), &DrivingStrength, StdHeader);
DrivingStrength &= 0x0000000F8;
DrivingStrength |= BIT0 + BIT2;
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader);
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + (0x7 << 7) + DrivingStrength, StdHeader);
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader);
}
}
//8.64 L1 Residency Duration
RwXhciIndReg ( FCH_XHCI_IND60_REG48, 0xFFFFFFFE0, BIT0, StdHeader);
}
}
/**
* FchInitMidAzalia - Config Azalia controller after PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitMidAzalia (
IN VOID *FchDataPtr
)
{
UINT8 Index;
BOOLEAN EnableAzalia;
UINT32 PinRouting;
UINT8 ChannelNum;
UINT8 AzaliaTempVariableByte;
UINT16 AzaliaTempVariableWord;
UINT32 BAR0;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
EnableAzalia = FALSE;
ChannelNum = 0;
AzaliaTempVariableByte = 0;
AzaliaTempVariableWord = 0;
BAR0 = 0;
if ( LocalCfgPtr->Azalia.AzaliaEnable == 1 ) {
return;
} else {
RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG04, AccessWidth8, (UINT32)~BIT1, BIT1, StdHeader);
if ( LocalCfgPtr->Azalia.AzaliaSsid != 0 ) {
RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Azalia.AzaliaSsid, StdHeader);
}
ReadPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG10, AccessWidth32, &BAR0, StdHeader);
if ( BAR0 != 0 ) {
if ( BAR0 != 0xFFFFFFFF ) {
BAR0 &= ~(0x03FFF);
EnableAzalia = TRUE;
}
}
}
if ( EnableAzalia ) {
//
// Get SDIN Configuration
//
if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin0 == 2 ) {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xA7, AccessWidth8, 0, 0x3E);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xA7, AccessWidth8, 0, 0x00);
} else {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xA7, AccessWidth8, 0, 0x0);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xA7, AccessWidth8, 0, 0x01);
}
if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin1 == 2 ) {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xA8, AccessWidth8, 0, 0x3E);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xA8, AccessWidth8, 0, 0x00);
} else {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xA8, AccessWidth8, 0, 0x0);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xA8, AccessWidth8, 0, 0x01);
}
if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin2 == 2 ) {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xA9, AccessWidth8, 0, 0x3E);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xA9, AccessWidth8, 0, 0x00);
} else {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xA9, AccessWidth8, 0, 0x0);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xA9, AccessWidth8, 0, 0x01);
}
if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin3 == 2 ) {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xAA, AccessWidth8, 0, 0x3E);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xAA, AccessWidth8, 0, 0x00);
} else {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xAA, AccessWidth8, 0, 0x0);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xAA, AccessWidth8, 0, 0x01);
}
Index = 11;
do {
ReadMem ( BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte);
AzaliaTempVariableByte |= BIT0;
WriteMem (BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte);
FchStall (1000, StdHeader);
ReadMem (BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte);
Index--;
} while ((! (AzaliaTempVariableByte & BIT0)) && (Index > 0) );
if ( Index == 0 ) {
return;
}
FchStall (1000, StdHeader);
ReadMem ( BAR0 + FCH_AZ_BAR_REG0E, AccessWidth16, &AzaliaTempVariableWord);
if ( AzaliaTempVariableWord & 0x0F ) {
//
//at least one azalia codec found
//
//PinRouting = LocalCfgPtr->Azalia.AZALIA_CONFIG.AzaliaSdinPin;
//new structure need make up PinRouting
//need adjust later!!!
//
PinRouting = 0;
PinRouting = (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin3;
PinRouting <<= 8;
PinRouting |= (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin2;
PinRouting <<= 8;
PinRouting |= (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin1;
PinRouting <<= 8;
PinRouting |= (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin0;
do {
if ( ( ! (PinRouting & BIT0) ) && (PinRouting & BIT1) ) {
ConfigureAzaliaPinCmd (LocalCfgPtr, BAR0, ChannelNum);
}
PinRouting >>= 8;
ChannelNum++;
} while ( ChannelNum != 4 );
} else {
//
//No Azalia codec found
//
if ( LocalCfgPtr->Azalia.AzaliaEnable != 2 ) {
/*********************************************************************************
* Name: FchXhciOnRecovery
*
* Description
*
*
* Input
* FchPrivate : FCH PEI private data structure
* XhciRomAddress : temporary base address value of Xhci controller
*
* Output
*
*
*********************************************************************************/
EFI_STATUS
FchXhciOnRecovery (
IN FCH_PEI_PRIVATE FchPrivate,
IN UINT32 XhciRomAddress
)
{
UINT16 BcdAddress;
UINT16 BcdSize;
UINT16 AcdAddress;
UINT16 AcdSize;
UINT16 FwAddress;
UINT16 FwSize;
UINT32 XhciFwStarting;
UINT32 SpiValidBase;
UINT32 RegData;
UINT16 Index;
AMD_CONFIG_PARAMS *StdHeader;
UINT8 FchRevision;
UINT32 XhcBootRamSize;
UINTN RomSigStartingAddr;
UINT32 RomStore[NUM_OF_ROMSIG_FILED];
UINT32 SelNum;
StdHeader = &FchPrivate.StdHdr;
FchRevision = 0;
ReadPci (PCI_ADDRESS (0, FCH_ISA_DEV, 0, 0x08), AccessWidth8, &FchRevision, StdHeader);
GetRomSigPtr (&RomSigStartingAddr, StdHeader);
for ( SelNum = 0; SelNum < NUM_OF_ROMSIG_FILED; SelNum++) {
RomStore[SelNum] = ACPIMMIO32 (RomSigStartingAddr + (SelNum << 2));
}
if ( XhciRomAddress != 0 ) {
RomStore[XHCI_FILED_NUM] = XhciRomAddress;
}
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader);
for ( SelNum = 1; SelNum < NUM_OF_ROMSIG_FILED; SelNum++) {
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGCC, AccessWidth32, ~ (BIT2 + BIT1 + BIT0), (BIT2 + SelNum), StdHeader);
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGCC, AccessWidth32, ROMSIG_CFG_MASK, RomStore[SelNum], StdHeader);
}
XhciFwStarting = RomStore[XHCI_FILED_NUM];
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0x00090000, 0x00400700);
FchStall (20, StdHeader);
//
// Enable SuperSpeed receive special error case logic. 0x20 bit8
// Enable USB2.0 RX_Valid Synchronization. 0x20 bit9
// Enable USB2.0 DIN/SE0 Synchronization. 0x20 bit10
//
XhcBootRamSize = XHC_BOOT_RAM_SIZE;
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, 0xFFFFF9FF, 0x00000600);
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG50 + 1, AccessWidth8, ~BIT1, BIT1);
//
// SuperSpeed PHY Configuration (adaptation timer setting)
// XHC U1 LFPS Exit time
//
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccessWidth32, 0xCFF00000, 0x000AAAAA);
//RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90 + 0x40, AccessWidth32, 0xFFF00000, 0x000AAAAA);
//
// Step 1. to enable Xhci IO and Firmware load mode
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, ~(BIT4 + BIT5), 0); /// Disable Device 22
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, ~(BIT7), BIT7); /// Enable 2.0 devices
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xF0FFFFFC, 0x01);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xEFFFFFFF, 0x10000000);
//
// Step 2. to read a portion of the USB3_APPLICATION_CODE from BIOS ROM area and program certain registers.
//
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA0, AccessWidth32, 0x00000000, (SPI_HEAD_LENGTH << 16));
BcdAddress = ACPIMMIO16 (XhciFwStarting + BCD_ADDR_OFFSET + XhcBootRamSize);
BcdSize = ACPIMMIO16 (XhciFwStarting + BCD_SIZE_OFFSET + XhcBootRamSize);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4, AccessWidth16, 0x0000, BcdAddress);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4 + 2, AccessWidth16, 0x0000, BcdSize);
AcdAddress = ACPIMMIO16 (XhciFwStarting + ACD_ADDR_OFFSET + XhcBootRamSize);
AcdSize = ACPIMMIO16 (XhciFwStarting + ACD_SIZE_OFFSET + XhcBootRamSize);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8, AccessWidth16, 0x0000, AcdAddress);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8 + 2, AccessWidth16, 0x0000, AcdSize);
SpiValidBase = SPI_BASE2 (XhciFwStarting + 4 + XHC_BOOT_RAM_SIZE) | SPI_BAR0_VLD | SPI_BASE0 | SPI_BAR1_VLD | SPI_BASE1 | SPI_BAR2_VLD;
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB0, AccessWidth32, 0x00000000, SpiValidBase);
//
// Copy Type0/1/2 data block from ROM image to MMIO starting from 0xC0
//
for (Index = 0; Index < SPI_HEAD_LENGTH; Index++) {
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + XhcBootRamSize + Index));
}
for (Index = 0; Index < BcdSize; Index++) {
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + BcdAddress + Index));
}
for (Index = 0; Index < AcdSize; Index++) {
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + BcdSize + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + AcdAddress + Index));
}
//
// Step 3. to enable the BOOT RAM preload functionality.
//
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~BIT0, BIT0);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~BIT29, 0);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccessWidth16, 0x7FFF, BIT15);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccessWidth16, 0x0000, 0);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08 + 2, AccessWidth16, 0x0000, 0x8000);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccessWidth16, 0x0000, 0);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~BIT29, BIT29);
for (;;) {
ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccessWidth32, &RegData);
if (RegData & BIT30) {
break;
}
}
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~BIT29, 0);
//
// Set the starting address offset for Instruction RAM preload.
//
FwAddress = ACPIMMIO16 (XhciFwStarting + FW_ADDR_OFFSET + XhcBootRamSize);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth16, 0x0000, ACPIMMIO16 (XhciFwStarting + FwAddress));
FwAddress += 2;
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccessWidth16, 0x0000, FwAddress + XhcBootRamSize);
FwSize = ACPIMMIO16 (XhciFwStarting + FW_SIZE_OFFSET + XhcBootRamSize);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccessWidth16, 0x0000, 0);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08 + 2, AccessWidth16, 0x0000, FwSize);
//
// Step 3.5 to enable the instruction RAM preload functionality.
//
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccessWidth16, 0x7FFF, 0);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~BIT29, BIT29);
for (;;) {
ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccessWidth32, &RegData);
if (RegData & BIT30) {
break;
}
}
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~BIT29, 0);
//
// Step 4. to release resets in XHCI_ACPI_MMIO_AMD_REG00. wait for USPLL to lock by polling USPLL lock.
//
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~U3PLL_RESET, 0); ///Release U3PLLreset
for (;;) {
ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccessWidth32, &RegData);
if (RegData & U3PLL_LOCK) {
break;
}
}
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~U3PHY_RESET, 0); ///Release U3PHY
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~U3CORE_RESET, 0); ///Release core reset
FchXhciRecoveryInitIndirectReg ( StdHeader, FchRevision );
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, ~(BIT4 + BIT5), 0); /// Disable Device 22
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, ~(BIT7), BIT7); /// Enable 2.0 devices
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~(BIT21), BIT21);
//
// Step 5.
//
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~(BIT17 + BIT18 + BIT19), BIT17 + BIT18 + BIT19);
//
// PLUG/UNPLUG of USB 2.0 devices make the XHCI USB 2.0 ports unfunctional - fix enable
// ACPI_USB3.0_REG 0x20[12:11] = 2'b11
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x3 << 11)), (UINT32) (0x3 << 11));
//
// XHC 2 USB2 ports interactional issue - fix enable
// ACPI_USB3.0_REG 0x20[16] = 1'b1
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x1 << 16)), (UINT32) (0x1 << 16));
//
// XHC USB2.0 Ports suspend Enhancement
// ACPI_USB3.0_REG 0x20[15] = 1'b1
//
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x1 << 15)), (UINT32) (0x1 << 15));
//
// XHC HS/FS IN Data Buffer Underflow issue - fix enable
// ACPI_USB3.0_REG 0x20[20:18] = 0x7
//
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x7 << 18)), (UINT32) (0x7 << 18));
//
// EHCI3/OHCI3 blocks Blink Global Clock Gating when EHCI/OHCI Dev 22 fn 0/2 are disabled
// ACPI_PMIO_F0[13] =1
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 13)), (UINT32) (0x1 << 13));
//
// USB leakage current on differential lines when ports are switched to XHCI - Fix enable
// ACPI_PMIO_F0[14] =1
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 14)), (UINT32) (0x1 << 14));
// RRG 8.26 XHCI Clear pending PME on Sx entry
RwXhciIndReg ( FCH_XHCI_IND_REG54, ~(BIT15), BIT15, StdHeader);
//
// UMI Lane Configuration Information for XHCI Firmware to Calculate the Bandwidth for USB 3.0 ISOC Devices
//
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~(BIT25 + BIT24), BIT24);
// RPR 8.23 FS/LS devices not functional after resume from S4 fix enable (SB02699)
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~(BIT22), BIT22);
// RPR 8.24 XHC USB2.0 Hub disable issue fix enable (SB02702)
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT20), BIT20);
// Set HCIVERSION to 1.0
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT15), BIT15);
// xHCI 1.0 Sub-Features Supported
// Blobk Event Interrupt Flag (BEI)
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT1), BIT1);
// Force Stopped Event (FSE)
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT2), BIT2);
// Software LPM
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT3), 0);
// Hardware LPM
// Skip TRB IOC Event
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT6), BIT6);
// Remove Secondary Bandwith Domain Reporting
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT7), BIT7);
// Cold Attach Status
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT8), BIT8);
// Endpoint Status Update Ordering
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT9), BIT9);
// Report Event during SKIP on Missed Service Error
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT10), BIT10);
// Soft Retry
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT11), BIT11);
// U3 Exit
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT12), BIT12);
// USB3.0 Link Command
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT13), BIT13);
// MSE FrameId invalid
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT14), BIT14);
// Port Test Mode
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT16), BIT16);
// Miscellaneous Design Improvements
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG40, AccessWidth32, ~(BIT0), BIT0);
//RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG40, AccessWidth32, ~(BIT25), 0);
// XHC USB2 Loopback RX SE0
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~(BIT13 + BIT14 + BIT21), BIT13 + BIT14 + BIT21);
// XHC U2IF_Enabled_Quiettermination off
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT20), BIT20);
// XHC S0 BLM Reset Mode
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF2, AccessWidth8, ~(BIT3), BIT3);
// Enhance XHC Ent_Flag
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT22), BIT22);
// Enhance TRB Pointer when both MSE and SKIP TRB IOC evt opened
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT17), BIT17);
// LPM Broadcast disable
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT18), BIT18);
// Enhance XHC FS/LS connect
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT24), BIT24);
// Enhance XHC ISOCH td_cmp
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT25), BIT25);
// LPM Clock 5us Select
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(BIT8), BIT8);
// Enhance DPP ERR as XactErr
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(BIT9), BIT9);
// Enhance U2IF PME Enable
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(BIT10), BIT10);
// U2IF S3 Disconnect detection
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(BIT12), BIT12);
// Stream Error Handling
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT20 + BIT21 + BIT22), (BIT20 + BIT21 + BIT22));
// FLA Deassert
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT23), BIT23);
// Enhance LPM Host initial L1 Exit
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~BIT29, BIT29);
// Enhance resume after disconnect
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG98, AccessWidth32, ~(BIT30), BIT30);
// Enhance SS HD Detected on Plug-in during S3
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG98, AccessWidth32, ~(BIT31), BIT31);
// Frame Babble Reporting
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT27), BIT27);
// xHCI Debug Capability
// DCP Halt RSTSM OFF
// Enable DCP DPH check
// DCP LTSSM Inactive to Rxdetect
// Enhance DCP EP State
// DCP Remote Wakeup Capable
// Enable ERDY send once DBC detectes HIT/HOT
// Block HIT/HOT until service interval done
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG100);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(BIT0 + BIT1 + BIT2), BIT0 + BIT1 + BIT2);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG120);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(BIT3), BIT3);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG100);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(BIT21), BIT21);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG128);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(BIT0), BIT0);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG100);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(BIT3 + BIT4), BIT3 + BIT4);
// Enhance SS HS detected during S3
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG48);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(BIT1), BIT1);
// Enhance U1 timer (shorten U1 exit response time)
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG48);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(BIT14), BIT14);
// Enhance HW LPM U2Entry state
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(BIT17), BIT17);
// Enhance SSIF PME
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(BIT15 + BIT14), (BIT15 + BIT14));
// U2IF Remote Wake Select
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(BIT11), BIT11);
// HS Data Toggle Error Handling
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(BIT16), BIT16);
// USB20PHY FL Speed select
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT28), BIT28);
// Enable Fix for DBC compatibility
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG100);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(BIT5), BIT5);
// Enable Fix for ACPI registers write issue.
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG28, AccessWidth32, ~(BIT0), BIT0);
//
// For BTS only
//
// LPM reated items
// HwLpmAddrSel (22) U2LpmTranArbEn, ColdAttachMode.
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(BIT20 + BIT21 + BIT22), (BIT20 + BIT21 + BIT22));
// HwLpmStateSel (24), HwLpmDeconfigL1Exit (25), HwLpmL1StopEpEn (26).
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(BIT24 + BIT25 + BIT26), (BIT24 + BIT25 + BIT26));
// Xhci10En: xHCI 10 Enable (0), HwLpmEn (4), SkipTrbIocEvtLenMode (24)
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT0 + BIT4 + BIT24), (BIT4 + BIT24));
// DcpNumP1En
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG100);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~ BIT5, BIT5);
// LtssmDisconnectToConnect
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG48);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(BIT16), BIT16);
// CcuMode
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG10, AccessWidth32, 0xFFFF00FF, 0x2A00);
// XtalPciClk_UseEcClkSel clear
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG50 + 1, AccessWidth8, ~BIT1, 0);
// Change PHY LFPS Detection threshold (RX_LFPSDET_TH[2:0]) to 6h from default setting 4h
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, 0x80);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, 0xFFFFFFF8, 0x06);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, 0xC0);
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, 0xFFFFFFF8, 0x06);
return EFI_SUCCESS;
}
/**
* FchXhciInitIndirectReg - Config XHCI Indirect Registers
*
*
*
* @param[in] StdHeader AMD Standard Header
* @param[in] FchRevision FCH Chip revision
*
*/
VOID
FchXhciRecoveryInitIndirectReg (
IN AMD_CONFIG_PARAMS *StdHeader,
IN UINT8 FchRevision
)
{
UINT8 Index;
UINT32 DrivingStrength;
UINT32 Port;
UINT32 Register;
UINT32 RegValue;
UINT32 Xhci20Phy[MAX_XHCI_PORTS];
Xhci20Phy[0] = 0x21;
Xhci20Phy[1] = 0x21;
Xhci20Phy[2] = 0x24;
Xhci20Phy[3] = 0x24;
DrivingStrength = 0;
//
// SuperSpeed PHY Configuration (adaptation mode setting)
//
RwXhciIndReg ( FCH_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021, StdHeader);
//
// BLM Meaasge
//
RwXhciIndReg ( FCH_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000, StdHeader);
//
// xHCI USB 2.0 PHY Settings
// Step 1 is done by hardware default
// Step 2
for (Port = 0; Port < 2; Port ++) {
DrivingStrength = (UINT32) (Xhci20Phy[Port]);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
}
RwXhci0IndReg ( FCH_XHCI_IND60_REG50, ~ ((UINT32) (0x0f)), ((UINT32) (0x07)), StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 4)), ((UINT32) (0x02 << 4)), StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)), StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG08, 0x80FC00FF, 0, StdHeader);
// RPR 8.25 Clock Gating in PHY
for (Port = 0; Port < 4; Port ++) {
DrivingStrength = 0x1E4;
if (Port < 2) {
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
}
}
// Enhance XHC LS Rise time
for (Port = 0; Port < 2; Port ++) {
DrivingStrength = 0x1C4;
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
}
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT23), BIT23);
// XHCI ISO device CRC false error detection
for (Port = 0; Port < 4; Port ++) {
if (Port < 2) {
ReadXhci0Phy (Port, (0x7 << 7), &DrivingStrength, StdHeader);
DrivingStrength &= 0x0000000F8;
DrivingStrength |= BIT0 + BIT2;
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + (0x7 << 7) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader);
}
}
// L1 Residency Duration
RwXhci0IndReg ( FCH_XHCI_IND60_REG48, 0xFFFFFFFE0, BIT0, StdHeader);
}
/**
* FchInitLateSata - Prepare SATA controller to boot to OS.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateSata (
IN VOID *FchDataPtr
)
{
UINT8 SataPciCommandByte;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//Return immediately is sata controller is not enabled
//
if ( LocalCfgPtr->Sata.SataMode.SataEnable == 0 ) {
return;
}
//
// Set Sata PCI Configuration Space Write enable
//
SataEnableWriteAccess (StdHeader);
//
// Set Sata Controller Memory & IO access enable
//
ReadPci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, &SataPciCommandByte, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, 0xFF, 0x03, StdHeader);
//
// Call Sub-function for each Sata mode
//
if (( LocalCfgPtr->Sata.SataClass == SataAhci7804) || (LocalCfgPtr->Sata.SataClass == SataAhci )) {
FchInitLateSataAhci ( LocalCfgPtr );
}
if (( LocalCfgPtr->Sata.SataClass == SataIde2Ahci) || (LocalCfgPtr->Sata.SataClass == SataIde2Ahci7804 )) {
FchInitLateSataIde2Ahci ( LocalCfgPtr );
}
if (( LocalCfgPtr->Sata.SataClass == SataNativeIde) || (LocalCfgPtr->Sata.SataClass == SataLegacyIde )) {
FchInitLateSataIde ( LocalCfgPtr );
}
if ( LocalCfgPtr->Sata.SataClass == SataRaid) {
FchInitLateSataRaid ( LocalCfgPtr );
}
FchInitLateProgramSataRegs ( LocalCfgPtr );
//
// Restore Sata Controller Memory & IO access status
//
WritePci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, &SataPciCommandByte, StdHeader);
//
// Set Sata PCI Configuration Space Write disable
//
SataDisableWriteAccess (StdHeader);
}
/**
* FchInitLateGpp - Prepare Gpp controller to boot to OS.
*
* PcieGppLateInit
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateGpp (
IN VOID *FchDataPtr
)
{
UINT8 PortId;
UINT8 BusNum;
UINT8 AspmValue;
UINT8 PortAspmValue;
UINT8 AllowStrapControlByAB;
UINT8 FchGppPhyPllPowerDown;
FCH_GPP_PORT_CONFIG *PortCfg;
UINT32 PciAspmValue;
UINT32 AbValue;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// Disable hidden register decode and serial number capability
//
AbValue = ReadAlink (FCH_ABCFG_REG330 | (UINT32) (ABCFG << 29), StdHeader);
WriteAlink (FCH_ABCFG_REG330 | (UINT32) (ABCFG << 29), AbValue & ~(BIT26 + BIT10), StdHeader);
if (ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader) & BIT8) {
return;
}
//
// Configure ASPM
//
AspmValue = (UINT8)LocalCfgPtr->Gpp.GppPortAspm;
FchGppPhyPllPowerDown = (UINT8) LocalCfgPtr->Gpp.GppPhyPllPowerDown;
AllowStrapControlByAB = 0x01;
for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
//
// write pci_reg3d with 0x01 to fix yellow mark for GPP bridge under some OS
// when native PCIE is enabled but MSI is not available
// BIF/GPP allowing strap STRAP_BIF_INTERRUPT_PIN_SB controlled by AB reg
//
PortCfg = &LocalCfgPtr->Gpp.PortCfg[PortId];
if (PortCfg->PortHotPlug) {
RwPci (PCI_ADDRESS (0, 21, PortId, 0x04), AccessWidth8, 0xFE, 0x00, StdHeader); ///clear IO enable to fix possible hotplug hang
}
WritePci (PCI_ADDRESS (0, 21, PortId, 0x3d), AccessWidth8, &AllowStrapControlByAB, StdHeader);
ReadPci (PCI_ADDRESS (0, 21, PortId, 0x19), AccessWidth8, &BusNum, StdHeader);
if (BusNum != 0xFF) {
ReadPci (PCI_ADDRESS (BusNum, 0, 0, 0x00), AccessWidth32, &PciAspmValue, StdHeader);
if (PciAspmValue != 0xffffffff) {
PortAspmValue = AspmValue;
//
// Validate ASPM support on EP side
//
FchGppValidateAspm (PCI_ADDRESS (BusNum, 0, 0, 0), &PortAspmValue, StdHeader);
//
// Set ASPM on EP side
//
FchGppSetEpAspm (PCI_ADDRESS (BusNum, 0, 0, 0), PortAspmValue, StdHeader);
//
// Set ASPM on port side
//
FchGppSetAspm (PCI_ADDRESS (0, 21, PortId, 0), PortAspmValue, StdHeader);
}
}
RwAlink ((FCH_RCINDXP_REG02 | (UINT32) (RCINDXP << 29) | (PortId << 24) ), ~(BIT15), (BIT15), StdHeader);
}
RwAlink ((FCH_RCINDXC_REG02 | (UINT32) (RCINDXC << 29)), ~(BIT0), (BIT0), StdHeader);
//
// Configure Lock HWInit registers
//
AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader);
if (AbValue & 0xF0) {
AbValue = ReadAlink (FCH_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), StdHeader);
WriteAlink (FCH_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), AbValue | BIT0, StdHeader); /// Set HWINIT_WR_LOCK
if ( FchGppPhyPllPowerDown == TRUE ) {
//
// Power Saving Feature for GPP Lanes
//
// Set PCIE_P_CNTL in Alink PCIEIND space
//
AbValue = ReadAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29), StdHeader);
AbValue |= BIT12 + BIT3 + BIT0;
AbValue &= ~(BIT9 + BIT4);
WriteAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29), AbValue, StdHeader);
RwAlink (FCH_RCINDXC_REG02, ~(BIT8), (BIT8), StdHeader);
RwAlink (FCH_RCINDXC_REG02, ~(BIT3), (BIT3), StdHeader);
}
}
//
// Restore strap0 via override
//
if (LocalCfgPtr->Gpp.PcieAer) {
RwAlink (FCH_ABCFG_REG310 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT7, StdHeader);
RwAlink (RC_INDXC_REGC0, 0xFFFFFFFF, BIT9, StdHeader);
}
}
