/** * ReadFchChipsetRevision - Get FCH chipset revision * * * @param[in] StdHeader * */ UINT8 ReadFchChipsetRevision ( IN AMD_CONFIG_PARAMS *StdHeader ) { UINT8 FchChipSetRevision; UINT8 FchMiscRegister; ReadPmio (FCH_PMIOA_REGC8 + 1, AccessWidth8, &FchMiscRegister, StdHeader); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8 + 1, AccessWidth8, ~(UINT32) BIT7, 0); ReadPci ((SMBUS_BUS_DEV_FUN << 16) + FCH_CFG_REG08, AccessWidth8, &FchChipSetRevision, StdHeader); WritePmio (FCH_PMIOA_REGC8 + 1, AccessWidth8, &FchMiscRegister, StdHeader); return FchChipSetRevision; }
/** * FchInitEnvSataIde - Config SATA IDE controller before PCI * emulation * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchInitEnvSataIde ( IN VOID *FchDataPtr ) { UINT8 ChannelByte; FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; UINT32 Bar5; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; SataBar5setting (LocalCfgPtr, &Bar5); // // Class code // if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) { RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0xFF, 0x01018A00, StdHeader); } else { RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0xFF, 0x01018F00, StdHeader); } // // Device ID // RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, KERN_FCH_SATA_DID, StdHeader); // // SSID // if (LocalCfgPtr->Sata.SataIdeSsid != NULL ) { RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Sata.SataIdeSsid, StdHeader); } // // Sata IDE Channel configuration // ChannelByte = 0x00; ReadPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, &ChannelByte, StdHeader); ChannelByte &= 0xCF; if ( LocalCfgPtr->Sata.SataDisUnusedIdePChannel ) { ChannelByte |= 0x10; } if ( LocalCfgPtr->Sata.SataDisUnusedIdeSChannel ) { ChannelByte |= 0x20; } RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG04), AccessWidth32, 0xFFFFFFFF, 0x07, StdHeader); // Clear AHCI Enable during POST time. DE is investigating when/how to restore this bit before goes to OS boot. RwMem ((Bar5 + FCH_SATA_BAR5_REG04), AccessWidth32, ~(UINT32) (BIT31), 0); RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG04), AccessWidth32, 0xFFFFFFFF, 0x00, StdHeader); WritePci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, &ChannelByte, StdHeader); }
/** * ProgramSpecificFchInitEnvAcpiMmio - Config HwAcpi MMIO before * PCI emulation * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID ProgramSpecificFchInitEnvAcpiMmio ( IN VOID *FchDataPtr ) { CPUID_DATA CpuId; FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchYangtzeInitEnvSpecificHwAcpiMmioTable[0]), StdHeader); LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, StdHeader); if ((LocalCfgPtr->HwAcpi.AnyHt200MhzLink) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100080) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100090) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x1000A0)) { RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x0A); RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0x80 + 3, AccessWidth8, 0xFE, 0x28); } else { RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x01); RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0x80 + 3, AccessWidth8, 0xFE, 0x20); } RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG6C + 2, AccessWidth8, 0x5F, 0xA0); // // Ac Loss Control // AcLossControl ((UINT8) LocalCfgPtr->HwAcpi.PwrFailShadow); // // FCH VGA Init // FchVgaInit (); // // Set ACPIMMIO by OEM Input table // ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE *) (LocalCfgPtr->HwAcpi.OemProgrammingTablePtr), StdHeader); }
/** * FchInitEnvLpc - Config LPC controller before PCI emulation * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchInitEnvLpc ( IN VOID *FchDataPtr ) { FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; // // LPC CFG programming // // // Turn on and configure LPC clock (48MHz) // RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x28, AccessWidth32, (UINT32)~(BIT21 + BIT20 + BIT19), 2 << 19); RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, (UINT32)~BIT7, 0); // // Initialization of pci config space // FchInitEnvLpcProgram (FchDataPtr); // // SSID for LPC Controller // if (LocalCfgPtr->Spi.LpcSsid != 0 ) { RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Spi.LpcSsid, StdHeader); } // // LPC MSI // if ( LocalCfgPtr->Spi.LpcMsiEnable ) { RwPci ((LPC_BUS_DEV_FUN << 16) + 0x78 , AccessWidth32, (UINT32)~BIT1, (UINT32)BIT1, StdHeader); } }
/** * ProgramGppTogglePcieReset - Toggle PCIE_RST2# * * * @param[in] DoToggling * @param[in] StdHeader * */ VOID ProgramGppTogglePcieReset ( IN BOOLEAN DoToggling, IN AMD_CONFIG_PARAMS *StdHeader ) { if (DoToggling) { FchResetPcie (FchBlock, AssertReset, StdHeader); FchStall (500, StdHeader); FchResetPcie (FchBlock, DeassertReset, StdHeader); } else { RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG04, AccessWidth8, ~(BIT1 + BIT0), 0x02); } }
/** * * emulation * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchInitEnvAzalia ( IN VOID *FchDataPtr ) { FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; if ( LocalCfgPtr->Azalia.AzaliaEnable == AzDisable ) { RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xEB , AccessWidth8, (UINT32)~BIT0, 0); } else { RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xEB , AccessWidth8, (UINT32)~BIT0, BIT0); RwPci ((((0x14<<3)+2) << 16) + 0x4C, AccessWidth8, (UINT32)~BIT0, BIT0, StdHeader); if ( LocalCfgPtr->Azalia.AzaliaMsiEnable) { RwPci ((((0x14<<3)+2) << 16) + 0x44, AccessWidth32, (UINT32)~BIT8, BIT8, StdHeader); RwPci ((((0x14<<3)+2) << 16) + 0x60, AccessWidth32, (UINT32)~BIT16, BIT16, StdHeader); } } }
/** * FchInitEnvAzalia - Config Azalia controller before PCI * emulation * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchInitEnvAzalia ( IN VOID *FchDataPtr ) { FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; if ( LocalCfgPtr->Azalia.AzaliaEnable == AzDisable ) { RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEB, AccessWidth8, ~BIT0, 0); } else { RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEB, AccessWidth8, ~BIT0, BIT0); RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG4C, AccessWidth8, ~BIT0, BIT0, StdHeader); if ( LocalCfgPtr->Azalia.AzaliaMsiEnable) { RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG44, AccessWidth32, ~BIT8, BIT8, StdHeader); RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG60, AccessWidth32, ~BIT16, BIT16, StdHeader); } } }
/** * FchSmmAcpiOn - Config Fch during ACPI_ON * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchSmmAcpiOn ( IN FCH_DATA_BLOCK *FchDataPtr ) { // // Commented the following code since we need to leave the IRQ1/12 filtering enabled always as per latest // recommendation. This is required to fix the keyboard stuck issue when playing games under Windows // // // Disable Power Button SMI // RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGAC, AccessWidth8, ~(BIT6), 0); }
/** * FchInitEnvLpcProgram - Config LPC controller before PCI * emulation * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchInitEnvLpcProgram ( IN VOID *FchDataPtr ) { FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; ProgramPciByteTable ((REG8_MASK*) (&FchInitHudson2EnvLpcPciTable[0]), sizeof (FchInitHudson2EnvLpcPciTable) / sizeof (REG8_MASK), StdHeader); // // Disable LPC A-Link Cycle Bypass // RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG50 + 2, AccessWidth8, 0xF7, BIT3); }
VOID FchSataRestore ( IN FCH_DATA_BLOCK *FchDataPtr ) { FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth8, 0, 0x11); RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84), AccessWidth32, 0, 0x04140006, StdHeader); RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REGA0), AccessWidth8, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), 0, StdHeader); FchStall (1000, StdHeader); FchInitEnvSata (FchDataPtr); FchInitLateSata (FchDataPtr); }
/** * FchXhciPowerSavingProgram - Config XHCI for Power Saving mode * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchXhciPowerSavingProgram ( IN FCH_DATA_BLOCK *FchDataPtr ) { UINT8 XhciEfuse; FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; // add Efuse checking for Xhci enable/disable XhciEfuse = XHCI_EFUSE_LOCATION; GetEfuseStatus (&XhciEfuse, StdHeader); if ((XhciEfuse & (BIT0 + BIT1)) != (BIT0 + BIT1)) { RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xF0FFFBFF, 0x0); } }
/** * FchSpiUnlock - Fch SPI Unlock * * * @param[in] FchDataPtr * */ VOID FchSpiUnlock ( IN VOID *FchDataPtr ) { UINT32 SpiRomBase; FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; SpiRomBase = LocalCfgPtr->Spi.RomBaseAddress; RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG50, AccessWidth32, ~(UINT32) (BIT0 + BIT1), 0, StdHeader); RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG54, AccessWidth32, ~(UINT32) (BIT0 + BIT1), 0, StdHeader); RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG58, AccessWidth32, ~(UINT32) (BIT0 + BIT1), 0, StdHeader); RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG5C, AccessWidth32, ~(UINT32) (BIT0 + BIT1), 0, StdHeader); RwMem (SpiRomBase + FCH_SPI_MMIO_REG00, AccessWidth32, ~(UINT32) (BIT22 + BIT23), (BIT22 + BIT23)); }
/** * EnableEhciController - Assign resources and enable EHCI controllers * * @param[in] Value Controller PCI config address (bus# + device# + function#) * @param[in] BarAddress Base address for Ehci controller * @param[in] StdHeader AMD standard header config param */ VOID EnableEhciController ( IN UINT32 Value, IN UINT32 BarAddress, IN AMD_CONFIG_PARAMS *StdHeader ) { UINT32 Var; WritePci ((UINT32) Value + FCH_EHCI_REG10, AccessWidth32, &BarAddress, StdHeader); RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, BIT1 + BIT2, StdHeader); ReadPci ((UINT32) Value + FCH_EHCI_REG10, AccessWidth32, &BarAddress, StdHeader); if ( (BarAddress != - 1) && (BarAddress != 0) ) { RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, BIT1, StdHeader); Var = 0x00020F00; WriteMem (BarAddress + FCH_EHCI_BAR_REGC0, AccessWidth32, &Var); RwMem (BarAddress + FCH_EHCI_BAR_REGA4, AccessWidth32, 0xFF00FF00, 0x00400040); RwMem (BarAddress + FCH_EHCI_BAR_REGBC, AccessWidth32, ~( BIT12 + BIT14), BIT12 + BIT14); RwMem (BarAddress + FCH_EHCI_BAR_REGB0, AccessWidth32, ~BIT5, BIT5); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth16, ~BIT12, BIT12); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~BIT16, BIT16); RwMem (BarAddress + FCH_EHCI_BAR_REGB4, AccessWidth32, ~BIT12, BIT12); RwMem (BarAddress + FCH_EHCI_BAR_REGC4, AccessWidth32, (UINT32) (~ 0x00000f00), 0x00000200); RwMem (BarAddress + FCH_EHCI_BAR_REGC0, AccessWidth32, (UINT32) (~ 0x0000ff00), 0x00000f00); RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x01 << 6)), (UINT32) (0x01 << 6), StdHeader); RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x0F << 8)), (UINT32) (0x01 << 8), StdHeader); RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x0F << 12)), (UINT32) (0x01 << 12), StdHeader); RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x01 << 17)), (UINT32) (0x01 << 17), StdHeader); RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x01 << 21)), (UINT32) (0x01 << 21), StdHeader); RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x01 << 29)), (UINT32) (0x01 << 29), StdHeader); RwPci ((UINT32) Value + FCH_EHCI_REG50 + 2, AccessWidth16, (UINT16)0xFFFF, BIT16 + BIT10, StdHeader); RwPci ((UINT32) Value + FCH_EHCI_REG54, AccessWidth32, ~ (BIT0 + (3 << 5) + (7 << 7)), 0x0000026b, StdHeader); RwPci ((UINT32) Value + FCH_EHCI_REG54, AccessWidth32, ~BIT4, BIT4, StdHeader); RwPci ((UINT32) Value + FCH_EHCI_REG54, AccessWidth32, ~BIT11, BIT11, StdHeader); RwPci ((UINT32) Value + FCH_EHCI_REG54, AccessWidth16, (UINT16)0x5FFF, BIT13 + BIT15, StdHeader); RwPci ((UINT32) Value + FCH_EHCI_REG50 + 2, AccessWidth16, ~BIT3, BIT3, StdHeader); RwPci ((UINT32) Value + FCH_EHCI_REG54 + 2, AccessWidth16, (UINT16)0xFFFC, BIT0 + BIT1, StdHeader); RwPci ((UINT32) Value + FCH_EHCI_REG54 + 2, AccessWidth16, (UINT16)0xFFFB, BIT2, StdHeader); RwPci ((UINT32) Value + FCH_EHCI_REG54 + 2, AccessWidth16, (UINT16)0xFFF7, BIT3, StdHeader); } }
/** * FchSwInitGecBootRom - Config GEC Boot ROM by Platform define * ROM address * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchSwInitGecBootRom ( IN VOID *FchDataPtr ) { VOID* GecRomAddress; VOID* GecShadowRomAddress; UINT32 Temp; FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; if ( !LocalCfgPtr->Gec.PtrDynamicGecRomAddress == NULL ) { GecRomAddress = LocalCfgPtr->Gec.PtrDynamicGecRomAddress; GecShadowRomAddress = (VOID*) (UINTN) LocalCfgPtr->Gec.GecShadowRomBase; FchCopyMem (GecShadowRomAddress, GecRomAddress, 0x100); ReadPci ((GEC_BUS_DEV_FUN << 16) + FCH_GEC_REG10, AccessWidth32, &Temp, StdHeader); Temp = Temp & 0xFFFFFFF0; RwMem (Temp + FCH_GEC_INTERNAL_REG, AccessWidth32, 0, BIT0 + BIT29); } }
/** * FchInitMidAzalia - Config Azalia controller after PCI * emulation * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchInitMidAzalia ( IN VOID *FchDataPtr ) { UINT8 Index; BOOLEAN EnableAzalia; UINT32 PinRouting; UINT8 ChannelNum; UINT8 AzaliaTempVariableByte; UINT16 AzaliaTempVariableWord; UINT32 BAR0; FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; EnableAzalia = FALSE; ChannelNum = 0; AzaliaTempVariableByte = 0; AzaliaTempVariableWord = 0; BAR0 = 0; if ( LocalCfgPtr->Azalia.AzaliaEnable == 1 ) { return; } else { RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG04, AccessWidth8, (UINT32)~BIT1, BIT1, StdHeader); if ( LocalCfgPtr->Azalia.AzaliaSsid != 0 ) { RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Azalia.AzaliaSsid, StdHeader); } ReadPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG10, AccessWidth32, &BAR0, StdHeader); if ( BAR0 != 0 ) { if ( BAR0 != 0xFFFFFFFF ) { BAR0 &= ~(0x03FFF); EnableAzalia = TRUE; } } } if ( EnableAzalia ) { // // Get SDIN Configuration // if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin0 == 2 ) { RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xA7, AccessWidth8, 0, 0x3E); RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xA7, AccessWidth8, 0, 0x00); } else { RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xA7, AccessWidth8, 0, 0x0); RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xA7, AccessWidth8, 0, 0x01); } if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin1 == 2 ) { RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xA8, AccessWidth8, 0, 0x3E); RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xA8, AccessWidth8, 0, 0x00); } else { RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xA8, AccessWidth8, 0, 0x0); RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xA8, AccessWidth8, 0, 0x01); } if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin2 == 2 ) { RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xA9, AccessWidth8, 0, 0x3E); RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xA9, AccessWidth8, 0, 0x00); } else { RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xA9, AccessWidth8, 0, 0x0); RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xA9, AccessWidth8, 0, 0x01); } if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin3 == 2 ) { RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xAA, AccessWidth8, 0, 0x3E); RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xAA, AccessWidth8, 0, 0x00); } else { RwMem (ACPI_MMIO_BASE + GPIO_BASE + 0xAA, AccessWidth8, 0, 0x0); RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0xAA, AccessWidth8, 0, 0x01); } Index = 11; do { ReadMem ( BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte); AzaliaTempVariableByte |= BIT0; WriteMem (BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte); FchStall (1000, StdHeader); ReadMem (BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte); Index--; } while ((! (AzaliaTempVariableByte & BIT0)) && (Index > 0) ); if ( Index == 0 ) { return; } FchStall (1000, StdHeader); ReadMem ( BAR0 + FCH_AZ_BAR_REG0E, AccessWidth16, &AzaliaTempVariableWord); if ( AzaliaTempVariableWord & 0x0F ) { // //at least one azalia codec found // //PinRouting = LocalCfgPtr->Azalia.AZALIA_CONFIG.AzaliaSdinPin; //new structure need make up PinRouting //need adjust later!!! // PinRouting = 0; PinRouting = (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin3; PinRouting <<= 8; PinRouting |= (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin2; PinRouting <<= 8; PinRouting |= (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin1; PinRouting <<= 8; PinRouting |= (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin0; do { if ( ( ! (PinRouting & BIT0) ) && (PinRouting & BIT1) ) { ConfigureAzaliaPinCmd (LocalCfgPtr, BAR0, ChannelNum); } PinRouting >>= 8; ChannelNum++; } while ( ChannelNum != 4 ); } else { // //No Azalia codec found // if ( LocalCfgPtr->Azalia.AzaliaEnable != 2 ) {
/** * FchInitEnvAbLinkInit - Set ABCFG registers before PCI * emulation. * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchInitEnvAbLinkInit ( IN VOID *FchDataPtr ) { UINT16 AbTempVar; UINT8 AbValue8; UINT8 FchALinkClkGateOff; UINT8 FchBLinkClkGateOff; AB_TBL_ENTRY *AbTblPtr; FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; FchALinkClkGateOff = (UINT8) LocalCfgPtr->Ab.ALinkClkGateOff; FchBLinkClkGateOff = (UINT8) LocalCfgPtr->Ab.BLinkClkGateOff; // // AB CFG programming // if ( LocalCfgPtr->Ab.SlowSpeedAbLinkClock ) { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, ~(UINT32) BIT1, BIT1); } else { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, ~(UINT32) BIT1, 0); } // // Read Arbiter address, Arbiter address is in PMIO 6Ch // ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6C, AccessWidth16, &AbTempVar); /// Write 0 to enable the arbiter AbValue8 = 0; LibAmdIoWrite (AccessWidth8, AbTempVar, &AbValue8, StdHeader); if ( LocalCfgPtr->Ab.PcieOrderRule == 1 ) { AbTblPtr = (AB_TBL_ENTRY *) (&Hudson2PcieOrderRule[0]); AbCfgTbl (AbTblPtr, StdHeader); } if ( LocalCfgPtr->Ab.PcieOrderRule == 2 ) { RwAlink (FCH_ABCFG_REG10090 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x7 << 10), (UINT32) (0x7 << 10), StdHeader); RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1F << 11), (UINT32) (0x1C << 11), StdHeader); RwAlink (FCH_ABCFG_REGB4 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 0), (UINT32) (0x3 << 0), StdHeader); } AbTblPtr = (AB_TBL_ENTRY *) (&Hudson2InitEnvAbTable[0]); AbCfgTbl (AbTblPtr, StdHeader); if ( LocalCfgPtr->Ab.ResetCpuOnSyncFlood ) { RwAlink (FCH_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~(UINT32) BIT2, BIT2, StdHeader); } if ( LocalCfgPtr->Ab.AbClockGating ) { RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16), StdHeader); RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16), StdHeader); RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24), StdHeader); RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24), StdHeader); } else { RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x0 << 24), StdHeader); RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x0 << 24), StdHeader); } if ( LocalCfgPtr->Ab.GppClockGating ) { RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 12), (UINT32) (0x4 << 12), StdHeader); RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 8), (UINT32) (0x7 << 8), StdHeader); RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0), StdHeader); } else { RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 8), (UINT32) (0x0 << 8), StdHeader); RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x0 << 0), StdHeader); } if ( LocalCfgPtr->Ab.UmiL1TimerOverride ) { RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x7 << 12), (UINT32) (LocalCfgPtr->Ab.UmiL1TimerOverride << 12), StdHeader); RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 15), (UINT32) (0x1 << 15), StdHeader); } if ( LocalCfgPtr->Ab.UmiLinkWidth ) { // RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16)); } if ( LocalCfgPtr->Ab.PcieRefClockOverClocking ) { // RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16)); } if ( LocalCfgPtr->Ab.UmiGppTxDriverStrength ) { RwAlink (FCH_ABCFG_REGA8 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 18), (UINT32) ((LocalCfgPtr->Ab.UmiGppTxDriverStrength - 1) << 18), StdHeader); RwAlink (FCH_ABCFG_REGA0 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 8), (UINT32) (0x1 << 8), StdHeader); } if ( LocalCfgPtr->Gpp.PcieAer ) { // RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16)); } if ( LocalCfgPtr->Gpp.PcieRas ) { // RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16)); } // // Ab Bridge MSI // if ( LocalCfgPtr->Ab.AbMsiEnable) { // AbValue = ReadAlink (FCH_ABCFG_REG94 | (UINT32) (ABCFG << 29), StdHeader); // AbValue = AbValue | BIT20; // WriteAlink (FCH_ABCFG_REG94 | (UINT32) (ABCFG << 29), AbValue, StdHeader); } // // A/B Clock Gate-OFF // if ( FchALinkClkGateOff ) { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFE, BIT0); } else { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFE, 0x00); } if ( FchBLinkClkGateOff ) { //RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2D, AccessWidth8, 0xEF, 0x10); /// A11 Only RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFD, BIT1); } else { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFD, 0x00); } if ( FchALinkClkGateOff | FchBLinkClkGateOff ) { RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG04 + 2, AccessWidth8, 0xFE, BIT0); } else { RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG04 + 2, AccessWidth8, 0xFE, 0); } if ( ReadFchChipsetRevision ( StdHeader ) == FCH_BOLTON ) { // Enable fix for race problem between PLL calibrator and LC wake up from L1. RwAlink (FCH_AX_INDXC_REG02, ~(UINT32) (BIT8), BIT8, StdHeader); // Set this bit to 1 to allow for proper ASPM L1 and L0s transitions when PLL power-down in L1 is enabled. RwAlink ((FCH_ABCFG_REGB8 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, BIT30, StdHeader); // A/B Clock Gate-OFF RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFC, 0x03); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG04 + 2, AccessWidth8, 0xFE, BIT0); } }
/** * FchInitEnvAbLinkInit - Set ABCFG registers before PCI * emulation. * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchInitEnvAbLinkInit ( IN VOID *FchDataPtr ) { UINT16 AbTempVar; UINT8 AbValue8; AB_TBL_ENTRY *AbTblPtr; FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; // // Set A-Link bridge access address. // This is an I/O address. The I/O address must be on 16-byte boundary. // RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGE0, AccessWidth32, 00, ALINK_ACCESS_INDEX); // // AB CFG programming // if ( LocalCfgPtr->Ab.SlowSpeedAbLinkClock ) { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, ~(UINT32) BIT1, BIT1); } else { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, ~(UINT32) BIT1, 0); } // // Read Arbiter address, Arbiter address is in PMIO 6Ch // ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6C, AccessWidth16, &AbTempVar); /// Write 0 to enable the arbiter AbValue8 = 0; LibAmdIoWrite (AccessWidth8, AbTempVar, &AbValue8, StdHeader); AbTblPtr = (AB_TBL_ENTRY *) (&KernInitEnvAbTable[0]); AbCfgTbl (AbTblPtr, StdHeader); // // Need to check // if ( LocalCfgPtr->Ab.ResetCpuOnSyncFlood ) { RwAlink (FCH_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~(UINT32) BIT2, BIT2, StdHeader); } if ( LocalCfgPtr->Ab.AbDmaMemoryWrtie3264B ) { RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x0 << 0), StdHeader); RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 2), (UINT32) (0x1 << 2), StdHeader); } else { RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0), StdHeader); RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 2), (UINT32) 0x0, StdHeader); } // // A Clock Gate-OFF // if ( LocalCfgPtr->Ab.ALinkClkGateOff ) { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFE, BIT0); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG04, AccessWidth32, 0xFFFEFFFF, BIT16); } else { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFE, 0); } // // B Clock Gate-OFF // if ( LocalCfgPtr->Ab.BLinkClkGateOff ) { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFD, BIT1); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG04, AccessWidth32, 0xFFFEFFFF, BIT16); } else { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFD, 0); } if ((LocalCfgPtr->Ab.ALinkClkGateOff == 0) && (LocalCfgPtr->Ab.BLinkClkGateOff == 0)) { RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG04, AccessWidth32, 0xFFFEFFFF, 0); } // // GPP and GFX Clock Request // remove to enable pci-e device // RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG00, AccessWidth8, 0xF0, LocalCfgPtr->Ab.GppClockRequest0); // RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG00, AccessWidth8, 0x0F, LocalCfgPtr->Ab.GppClockRequest1); // RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG00 + 1, AccessWidth8, 0xF0, LocalCfgPtr->Ab.GppClockRequest2); // RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG00 + 1, AccessWidth8, 0x0F, LocalCfgPtr->Ab.GppClockRequest3); // RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG04, AccessWidth8, 0x0F, LocalCfgPtr->Ab.GfxClockRequest); // // AB Clock Gating // if ( LocalCfgPtr->Ab.AbClockGating ) { RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 4), (UINT32) (0x1 << 4), StdHeader); RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24), StdHeader); RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 20), (UINT32) (0x1 << 20), StdHeader); RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 24), (UINT32) (0x3 << 24), StdHeader); RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 20), (UINT32) (0x1 << 20), StdHeader); } else { RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 20), 0, StdHeader); RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 24), 0, StdHeader); RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 20), 0, StdHeader); RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), 0, StdHeader); RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 4), 0, StdHeader); } // // AB Memory Power Saving // if ( LocalCfgPtr->Ab.AbMemoryPowerSaving ) { RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x68, AccessWidth8, 0xFB, 0x00); RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 29), (UINT32) (0x1 << 29), StdHeader); RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 31), (UINT32) (0x1 << 31), StdHeader); } else { RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x5 << 29), (UINT32) 0x0, StdHeader); RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x68, AccessWidth8, 0xFB, 0x04); } // // SBG Memory Power Saving // if ( LocalCfgPtr->Ab.SbgMemoryPowerSaving ) { RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x68, AccessWidth8, 0xFD, 0x00); RwAlink (FCH_ABCFG_REG208 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 7), (UINT32) (0x1 << 7), StdHeader); RwAlink (FCH_ABCFG_REG208 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 9), (UINT32) (0x1 << 9), StdHeader); } else { RwAlink (FCH_ABCFG_REG208 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 7), (UINT32) 0x0, StdHeader); RwAlink (FCH_ABCFG_REG208 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 9), (UINT32) 0x0, StdHeader); RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x68, AccessWidth8, 0xFD, 0x02); } // // SBG Clock Gating // if ( LocalCfgPtr->Ab.SbgClockGating ) { RwAlink (FCH_ABCFG_REG208 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 4), (UINT32) (0x1 << 4), StdHeader); RwAlink (FCH_ABCFG_REG208 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 15), (UINT32) (0x1 << 15), StdHeader); RwAlink (FCH_ABCFG_REG208 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 22), (UINT32) (0x1 << 22), StdHeader); } else { RwAlink (FCH_ABCFG_REG208 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 4), (UINT32) (0x0), StdHeader); RwAlink (FCH_ABCFG_REG208 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 15), (UINT32) (0x0), StdHeader); RwAlink (FCH_ABCFG_REG208 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 22), (UINT32) (0x0), StdHeader); } // // XDMA DMA Write 16 byte Mode // if ( LocalCfgPtr->Ab.XdmaDmaWrite16ByteMode ) { RwAlink (FCH_ABCFG_REG180 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0), StdHeader); } else { RwAlink (FCH_ABCFG_REG180 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x0), StdHeader); } // // XDMA Memory Power Saving // if ( LocalCfgPtr->Ab.XdmaMemoryPowerSaving ) { RwAlink (FCH_ABCFG_REG184 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 2), (UINT32) (0x1 << 2), StdHeader); } else { RwAlink (FCH_ABCFG_REG184 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 2), (UINT32) 0x0, StdHeader); } // // XDMA Pending NPR Threshold // if ( LocalCfgPtr->Ab.XdmaPendingNprThreshold ) { AbValue8 = LocalCfgPtr->Ab.XdmaPendingNprThreshold; RwAlink (FCH_ABCFG_REG180 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x03 << 2), (UINT32) (AbValue8 << 2), StdHeader); } else { RwAlink (FCH_ABCFG_REG180 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x03 << 2), (UINT32) (0x0), StdHeader); } // // XDMA DNCPL Order Dis // if ( LocalCfgPtr->Ab.XdmaDncplOrderDis ) { RwAlink (FCH_ABCFG_REG180 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 5), (UINT32) (0x1 << 5), StdHeader); } else { RwAlink (FCH_ABCFG_REG180 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 5), (UINT32) (0x0), StdHeader); } }
/** * FchXhciInitBeforePciInit - Config XHCI controller before PCI * emulation * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchXhciInitBeforePciInit ( IN FCH_DATA_BLOCK *FchDataPtr ) { UINT16 BcdAddress; UINT16 BcdSize; UINT16 AcdAddress; UINT16 AcdSize; UINT16 FwAddress; UINT16 FwSize; UINTN XhciFwStarting; UINT32 SpiValidBase; UINT32 RegData; UINT16 Index; BOOLEAN Xhci0Enable; BOOLEAN Xhci1Enable; FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; Xhci0Enable = LocalCfgPtr->Usb.Xhci0Enable; Xhci1Enable = LocalCfgPtr->Usb.Xhci1Enable; if (( Xhci0Enable == 0 ) && (Xhci1Enable == 0)) { return; } RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0x00000000, 0x00400700); FchStall (20, StdHeader); if ( LocalCfgPtr->Usb.UserDefineXhciRomAddr == 0 ) { // // Get ROM SIG starting address for USB firmware starting address (offset 0x0C to SIG address) // GetRomSigPtr (&XhciFwStarting, StdHeader); if (XhciFwStarting == 0) { return; } XhciFwStarting = ACPIMMIO32 (XhciFwStarting + FW_TO_SIGADDR_OFFSET); } else { XhciFwStarting = ( UINTN ) LocalCfgPtr->Usb.UserDefineXhciRomAddr; } if (IsLpcRom ()) { // // XHCI firmware re-load // RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGCC, AccessWidth32, (UINT32)~BIT2, (UINT32)(BIT2 + BIT1 + BIT0), StdHeader); RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGCC, AccessWidth32, 0x00000FFF, (UINT32) (XhciFwStarting), StdHeader); } // // Enable SuperSpeed receive special error case logic. 0x20 bit8 // Enable USB2.0 RX_Valid Synchronization. 0x20 bit9 // Enable USB2.0 DIN/SE0 Synchronization. 0x20 bit10 // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, 0xFFFFF8FF, 0x00000700); // // SuperSpeed PHY Configuration (adaptation timer setting) // XHC U1 LFPS Exit time // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccessWidth32, 0xCFF00000, 0x000AAAAA); //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90 + 0x40, AccessWidth32, 0xFFF00000, 0x000AAAAA); // // Step 1. to enable Xhci IO and Firmware load mode // RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, (UINT32)~(BIT4 + BIT5), 0); /// Disable Device 22 RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, (UINT32)~(BIT7), (UINT32)BIT7); /// Enable 2.0 devices RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xF0FFFFFC, (Xhci0Enable + (Xhci1Enable << 1)) & 0x03); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xEFFFFFFF, 0x10000000); // // Step 2. to read a portion of the USB3_APPLICATION_CODE from BIOS ROM area and program certain registers. // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA0, AccessWidth32, 0x00000000, (SPI_HEAD_LENGTH << 16)); BcdAddress = ACPIMMIO16 (XhciFwStarting + BCD_ADDR_OFFSET); BcdSize = ACPIMMIO16 (XhciFwStarting + BCD_SIZE_OFFSET); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4, AccessWidth16, 0x0000, BcdAddress); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4 + 2, AccessWidth16, 0x0000, BcdSize); AcdAddress = ACPIMMIO16 (XhciFwStarting + ACD_ADDR_OFFSET); AcdSize = ACPIMMIO16 (XhciFwStarting + ACD_SIZE_OFFSET); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8, AccessWidth16, 0x0000, AcdAddress); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8 + 2, AccessWidth16, 0x0000, AcdSize); SpiValidBase = SPI_BASE2 (XhciFwStarting + 4) | SPI_BAR0_VLD | SPI_BASE0 | SPI_BAR1_VLD | SPI_BASE1 | SPI_BAR2_VLD; RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB0, AccessWidth32, 0x00000000, SpiValidBase); // // Copy Type0/1/2 data block from ROM image to MMIO starting from 0xC0 // for (Index = 0; Index < SPI_HEAD_LENGTH; Index++) { RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + Index)); } for (Index = 0; Index < BcdSize; Index++) { RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + BcdAddress + Index)); } for (Index = 0; Index < AcdSize; Index++) { RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + BcdSize + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + AcdAddress + Index)); } // // Step 3. to enable the instruction RAM preload functionality. // FwAddress = ACPIMMIO16 (XhciFwStarting + FW_ADDR_OFFSET); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth16, 0x0000, ACPIMMIO16 (XhciFwStarting + FwAddress)); FwAddress += 2; RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccessWidth16, 0x0000, FwAddress); FwSize = ACPIMMIO16 (XhciFwStarting + FW_SIZE_OFFSET); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccessWidth16, 0x0000, FwSize); // // Set the starting address offset for Instruction RAM preload. // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccessWidth16, 0x0000, 0); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~BIT29, (UINT32)BIT29); for (;;) { ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccessWidth32, &RegData); if (RegData & BIT30) { break; } } RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~BIT29, 0); // // Step 4. to release resets in XHCI_ACPI_MMIO_AMD_REG00. wait for USPLL to lock by polling USPLL lock. // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~U3PLL_RESET, 0); ///Release U3PLLreset for (;;) { ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccessWidth32, &RegData); if (RegData & U3PLL_LOCK) { break; } } RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~U3PHY_RESET, 0); ///Release U3PHY RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~U3CORE_RESET, 0); ///Release core reset // // SuperSpeed PHY Configuration // //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccessWidth32, 0xFFF00000, 0x000AAAAA); //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGD0, AccessWidth32, 0xFFF00000, 0x000AAAAA); FchXhciInitIndirectReg (StdHeader); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, (UINT32)~(BIT4 + BIT5), 0); /// Disable Device 22 RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, (UINT32)~(BIT7), (UINT32)BIT7); /// Enable 2.0 devices RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~(BIT21), (UINT32)BIT21); // // Step 5. // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, (UINT32)~(BIT17 + BIT18 + BIT19), (UINT32)(BIT17 + BIT18)); XhciA12Fix (); // // UMI Lane Configuration Information for XHCI Firmware to Calculate the Bandwidth for USB 3.0 ISOC Devices // if (!(IsUmiOneLaneGen1Mode (StdHeader))) { RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, (UINT32)~(BIT25 + BIT24), (UINT32)BIT24); } // RPR 8.23 FS/LS devices not functional after resume from S4 fix enable (SB02699) RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, (UINT32)~(BIT22), (UINT32)BIT22); // RPR 8.24 XHC USB2.0 Hub disable issue fix enable (SB02702) RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, (UINT32)~(BIT20), (UINT32)BIT20); }
/** * FchInitResetHwAcpi - Config HwAcpi controller during Power-On * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchInitResetHwAcpi ( IN VOID *FchDataPtr ) { UINT16 SmbusBase; UINT8 Value; UINT16 AsfPort; FCH_RESET_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; // // Set Build option into SB // WritePci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG64, AccessWidth16, &(UserOptions.CfgSioPmeBaseAddress), StdHeader); // // Enabled SMBUS0/SMBUS1 (ASF) Base Address // RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2C, AccessWidth16, 06, (UserOptions.CfgSmbus0BaseAddress) + BIT0); ///protect BIT[2:1] RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG28, AccessWidth16, 06, (UserOptions.CfgSmbus1BaseAddress) + BIT0); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, 00, (UserOptions.CfgAcpiPm1EvtBlkAddr)); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG62, AccessWidth16, 00, (UserOptions.CfgAcpiPm1CntBlkAddr)); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64, AccessWidth16, 00, (UserOptions.CfgAcpiPmTmrBlkAddr)); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG66, AccessWidth16, 00, (UserOptions.CfgCpuControlBlkAddr)); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG68, AccessWidth16, 00, (UserOptions.CfgAcpiGpe0BlkAddr)); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6A, AccessWidth16, 00, (UserOptions.CfgSmiCmdPortAddr)); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6C, AccessWidth16, 00, (UserOptions.CfgAcpiPmaCntBlkAddr)); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6E, AccessWidth16, 00, (UserOptions.CfgSmiCmdPortAddr) + 8); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG48, AccessWidth32, 00, (UserOptions.CfgWatchDogTimerBase)); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2E, AccessWidth8, ~(BIT1 + BIT2), 0); ///clear BIT[2:1] SmbusBase = (UINT16) (UserOptions.CfgSmbus0BaseAddress); Value = 0x00; LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &Value, StdHeader); ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchInitResetAcpiMmioTable[0]), StdHeader); // // Prevent RTC error // Value = 0x0A; LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader); LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); Value &= 0xEF; LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); Value = 0x08; LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader); LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); if ( !LocalCfgPtr->EcKbd ) { // // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input // Value = Value | 0x0A; } LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); Value = 0x09; LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader); LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); if ( !LocalCfgPtr->EcKbd ) { // // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input // Value = Value & 0xF9; } if ( LocalCfgPtr->LegacyFree ) { // // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation. // Value = Value & 0x9F; } // // Enabled IRQ input // Value = Value | BIT4; LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); AsfPort = ((UINT16) UserOptions.CfgSmbus1BaseAddress & 0xFFF0); if ( AsfPort != 0 ) { UINT8 dbValue; dbValue = 0x70; LibAmdIoWrite (AccessWidth8, AsfPort + 0x0E, &dbValue, StdHeader); } }
/** * FchProgramSataPhy - Program Sata PHY registers * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchProgramSataPhy ( IN VOID *FchDataPtr ) { SATA_PHY_SETTING *PhyTablePtr; UINT16 Index; UINT8 eFuseSquelchValue; UINT32 SquelchValue[2]; UINT8 PortNum; FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; PhyTablePtr = &SataPhyTable[0]; for (Index = 0; Index < (sizeof (SataPhyTable) / sizeof (SATA_PHY_SETTING)); Index++) { RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0xFC00, PhyTablePtr->PhyCoreControlWord, StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG98, AccessWidth32, 0x00, PhyTablePtr->PhyFineTuneDword, StdHeader); ++PhyTablePtr; } SquelchValue[0] = (0x07 << 9); SquelchValue[1] = (0x07 << 9); eFuseSquelchValue = 0; // // SATA RX register settings need to be updated to pass Gen3 RX JTOL // for (PortNum = 0; PortNum < 2; PortNum ++) { RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, ( 0x30 + PortNum), StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0xF << 24)), (UINT32) (0xF << 24), StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x3 << 22)), (UINT32) (0x2 << 22), StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x1F << 17)), (UINT32) (0x07 << 17), StdHeader); //ENH454807 RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x1 << 16)), (UINT32) (0x1 << 16), StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x1 << 12)), 0, StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0xF << 5)), (UINT32) (0x4 << 5), StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x1F)), (UINT32) ( 0x6), StdHeader); } RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG94, AccessWidth32, (UINT32) (~(0x1F << 2)), (UINT32) ( 0x1F << 2 ), StdHeader); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8, AccessWidth8, 0xDF, 0x20); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8, AccessWidth8, 0, 1); ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8 + 1, AccessWidth8, &eFuseSquelchValue); if ( (eFuseSquelchValue & BIT4) == BIT4) { SquelchValue[0] = ( UINT32 ) ( eFuseSquelchValue & 0xE0); SquelchValue[0] = (SquelchValue[0] << 4); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8, AccessWidth8, 0, 2); ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8 + 1, AccessWidth8, &eFuseSquelchValue); SquelchValue[1] = ( UINT32 ) ( eFuseSquelchValue & 0x07); SquelchValue[1] = (SquelchValue[1] << 9); } else { SquelchValue[0] = (0x05 << 9); SquelchValue[1] = (0x05 << 9); } RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8, AccessWidth8, 0, 0); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8, AccessWidth8, 0xDF, 0); for (PortNum = 0; PortNum < 2; PortNum ++) { RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, ( 0x30 + PortNum), StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x7 << 13)), (UINT32) (0x0 << 13), StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, ( 0x20 + PortNum), StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG94, AccessWidth32, (UINT32) (~(0x1F << 2)), (UINT32) ( 0x04 << 2 ), StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, ( 0x10 + PortNum), StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG94, AccessWidth32, (UINT32) (~(0x1F << 2)), (UINT32) ( 0x03 << 2 ), StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, 0x010, StdHeader); } RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, ( 0x30 + 0), StdHeader); RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG98, AccessWidth32, (UINT32) (~(0x7FF << 0)), (UINT32) ( (LocalCfgPtr->Sata.SataDbgTX_DRV_STR << 8) | LocalCfgPtr->Sata.SataDbgTX_DE_EMPH_STR ), StdHeader); }
/** * FchInitEnvAbLinkInit - Set ABCFG registers before PCI * emulation. * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchInitEnvAbLinkInit ( IN VOID *FchDataPtr ) { UINT16 AbTempVar; UINT8 AbValue8; AB_TBL_ENTRY *AbTblPtr; FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; // // AB CFG programming // if ( LocalCfgPtr->Ab.SlowSpeedAbLinkClock ) { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, (UINT32)~BIT1, BIT1); } else { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, (UINT32)~BIT1, 0); } // // Read Arbiter address, Arbiter address is in PMIO 6Ch // ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6C, AccessWidth16, &AbTempVar); /// Write 0 to enable the arbiter AbValue8 = 0; LibAmdIoWrite (AccessWidth8, AbTempVar, &AbValue8, StdHeader); AbTblPtr = (AB_TBL_ENTRY *) (&YangtzeInitEnvAbTable[0]); AbCfgTbl (AbTblPtr, StdHeader); if ( LocalCfgPtr->Ab.ResetCpuOnSyncFlood ) { RwAlink (0x10050ul | (UINT32) (ABCFG << 29), (UINT32)~BIT2, BIT2, StdHeader); } if ( LocalCfgPtr->Ab.AbClockGating ) { RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 4), (UINT32) (0x1 << 4), StdHeader); RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24), StdHeader); RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 20), (UINT32) (0x1 << 20), StdHeader); RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 24), (UINT32) (0x3 << 24), StdHeader); RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 20), (UINT32) (0x1 << 20), StdHeader); } else { RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 20), 0, StdHeader); RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 24), 0, StdHeader); RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 20), 0, StdHeader); RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), 0, StdHeader); RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 4), 0, StdHeader); } if ( LocalCfgPtr->Ab.AbDmaMemoryWrtie3264B ) { RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x0 << 0), StdHeader); RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 2), (UINT32) (0x1 << 2), StdHeader); } else { RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0), StdHeader); RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 2), (UINT32) 0x0, StdHeader); } if ( LocalCfgPtr->Ab.AbMemoryPowerSaving ) { RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x68, AccessWidth8, 0xFB, 0x00); RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 29), (UINT32) (0x1 << 29), StdHeader); RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 31), (UINT32) (0x1 << 31), StdHeader); } else { RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x5 << 29), (UINT32) 0x0, StdHeader); RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x68, AccessWidth8, 0xFB, 0x04); } // // A/B Clock Gate-OFF // if ( LocalCfgPtr->Ab.ALinkClkGateOff ) { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFE, BIT0); } else { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFE, 0); } if ( LocalCfgPtr->Ab.BLinkClkGateOff ) { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFD, BIT1); } else { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG2C + 2, AccessWidth8, 0xFD, 0); } if ( LocalCfgPtr->Ab.ALinkClkGateOff | LocalCfgPtr->Ab.BLinkClkGateOff ) { RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG04 + 2, AccessWidth8, 0xFE, BIT0); } else { RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG04 + 2, AccessWidth8, 0xFE, 0); } }
/** * ProgramFchEnvSpreadSpectrum - Config SpreadSpectrum before * PCI emulation * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID ProgramFchEnvSpreadSpectrum ( IN VOID *FchDataPtr ) { UINT8 PortStatus; UINT8 FchSpreadSpectrum; FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; FchSpreadSpectrum = LocalCfgPtr->HwAcpi.SpreadSpectrum; if ( FchSpreadSpectrum ) { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, 0x00); if ( LocalCfgPtr->HwAcpi.SpreadSpectrumOptions == 0 ) { /// -0.362% RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG18 + 1, AccessWidth8, 0xF0, 0x01); RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14 + 2, AccessWidth16, 0, 0xCF5C); RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14, AccessWidth16, 0, 0x0137); } if ( LocalCfgPtr->HwAcpi.SpreadSpectrumOptions == 1 ) { /// -0.375% RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG18 + 1, AccessWidth8, 0xF0, 0x01); RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14 + 2, AccessWidth16, 0, 0xE000); RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14, AccessWidth16, 0, 0x0142); } if ( LocalCfgPtr->HwAcpi.SpreadSpectrumOptions == 2 ) { /// -0.4% RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG18 + 1, AccessWidth8, 0xF0, 0x02); RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14 + 2, AccessWidth16, 0, 0); RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14, AccessWidth16, 0, 0x0158); } if ( LocalCfgPtr->HwAcpi.SpreadSpectrumOptions == 3 ) { /// -0.425% RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG18 + 1, AccessWidth8, 0xF0, 0x02); RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14 + 2, AccessWidth16, 0, 0x1FFF); RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14, AccessWidth16, 0, 0x016D); } if ( LocalCfgPtr->HwAcpi.SpreadSpectrumOptions == 4 ) { /// -0.45% RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG18 + 1, AccessWidth8, 0xF0, 0x02); RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14 + 2, AccessWidth16, 0, 0x4000); RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14, AccessWidth16, 0, 0x0183); } if ( LocalCfgPtr->HwAcpi.SpreadSpectrumOptions == 5 ) { /// -0.475% RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG18 + 1, AccessWidth8, 0xF0, 0x02); RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14 + 2, AccessWidth16, 0, 0x6000); RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG14, AccessWidth16, 0, 0x0198); } RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, BIT0); } else { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, 0x00); } // // PLL 100Mhz Reference Clock Buffer setting for internal clock generator mode (BIT5) // OSC Clock setting for internal clock generator mode (BIT6) // GetChipSysMode (&PortStatus, StdHeader); if ( ((PortStatus & ChipSysIntClkGen) == ChipSysIntClkGen) ) { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG04 + 1, AccessWidth8, (UINT32)~(BIT5 + BIT6), BIT5 + BIT6); } }
/** * FchInitResetSataProgram - Config Sata controller during * Power-On * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchInitResetSataProgram ( IN VOID *FchDataPtr ) { UINT8 SataPortNum; UINT8 PortStatusByte; UINT8 EfuseByte; UINT8 FchSataMode; UINT8 FchSataInternal100Spread; FCH_RESET_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; // //FchSataMode = LocalCfgPtr->Sata.SATA_MODE.SataMode.SataModeReg; //New structure need calculate Sata Register value // FchSataMode = 0; if ( LocalCfgPtr->FchReset.SataEnable ) { FchSataMode |= 0x01; } if ( LocalCfgPtr->Sata6AhciCap ) { FchSataMode |= 0x02; } if ( LocalCfgPtr->SataSetMaxGen2 ) { FchSataMode |= 0x04; } if ( LocalCfgPtr->FchReset.IdeEnable ) { FchSataMode |= 0x08; } FchSataMode |= (( LocalCfgPtr->SataClkMode ) << 4 ) ; LocalCfgPtr->SataModeReg = FchSataMode; ///Save Back to Structure FchSataInternal100Spread = ( UINT8 ) LocalCfgPtr->SataInternal100Spread; SataPortNum = 0; if ( ReadFchChipsetRevision ( StdHeader ) >= FCH_BOLTON ) { // ECO host link domain may not be reset correctly by device's OOB issue. RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, ~(UINT32) BIT6, BIT6, StdHeader); } // // Sata Workaround // for ( SataPortNum = 0; SataPortNum < 0x08; SataPortNum++ ) { RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40 + 2), AccessWidth8, 0xFF, 1 << SataPortNum, StdHeader); FchStall (2, StdHeader); RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40 + 2), AccessWidth8, (0xFF ^ (1 << SataPortNum)) , 0x00, StdHeader); FchStall (2, StdHeader); } RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84 + 3), AccessWidth8, ~(UINT32) BIT2, 0, StdHeader); RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REGA0), AccessWidth8, ~(UINT32) (BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5, StdHeader); // // Sata Setting for clock mode only // RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth8, 0, FchSataMode); if ( FchSataInternal100Spread ) { RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccessWidth8, 0xFF, BIT4); RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84), AccessWidth32, 0xFFFFFFFB, 0x00, StdHeader); } else { RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccessWidth8, ~(UINT32) BIT4, 0x00); } EfuseByte = SATA_FIS_BASE_EFUSE_LOC; GetEfuseStatus (&EfuseByte, StdHeader); if (EfuseByte & BIT0) { RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth8, 0xFB, 0x04); } ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth8, &PortStatusByte); if ( ((PortStatusByte & 0xF0) == 0x10) ) { RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_PMIOA_REG08, AccessWidth8, 0, BIT5); } if ( FchSataInternal100Spread ) { RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84), AccessWidth32, 0xFFFFFFFF, 0x04, StdHeader); } }
/** * FchXhciInitBeforePciInit - Config XHCI controller before PCI * emulation * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchXhciInitBeforePciInit ( IN FCH_DATA_BLOCK *FchDataPtr ) { UINT16 BcdAddress; UINT16 BcdSize; UINT16 AcdAddress; UINT16 AcdSize; UINT16 FwAddress; UINT16 FwSize; UINT32 XhciFwStarting; UINT32 SpiValidBase; UINT32 RegData; UINT16 Index; BOOLEAN Xhci0Enable; BOOLEAN Xhci1Enable; FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; Xhci0Enable = LocalCfgPtr->Usb.Xhci0Enable; Xhci1Enable = LocalCfgPtr->Usb.Xhci1Enable; if (( Xhci0Enable == 0 ) && (Xhci1Enable == 0)) { return; } RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0x00000000, 0x00400700); FchStall (20, StdHeader); XhciFwStarting = FchCombineSigRomInfo (FchDataPtr); if ( XhciFwStarting == 0 ) { return; } // // Enable SuperSpeed receive special error case logic. 0x20 bit8 // Enable USB2.0 RX_Valid Synchronization. 0x20 bit9 // Enable USB2.0 DIN/SE0 Synchronization. 0x20 bit10 // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, 0xFFFFF8FF, 0x00000700); // // SuperSpeed PHY Configuration (adaptation timer setting) // XHC U1 LFPS Exit time // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccessWidth32, 0xCFF00000, 0x000AAAAA); //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90 + 0x40, AccessWidth32, 0xFFF00000, 0x000AAAAA); // // Step 1. to enable Xhci IO and Firmware load mode // RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, ~(UINT32) (BIT4 + BIT5), 0); /// Disable Device 22 RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, ~(UINT32) (BIT7), BIT7); /// Enable 2.0 devices RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xF0FFFFFC, (Xhci0Enable + (Xhci1Enable << 1)) & 0x03); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xEFFFFFFF, 0x10000000); // // Step 2. to read a portion of the USB3_APPLICATION_CODE from BIOS ROM area and program certain registers. // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA0, AccessWidth32, 0x00000000, (SPI_HEAD_LENGTH << 16)); BcdAddress = ACPIMMIO16 (XhciFwStarting + BCD_ADDR_OFFSET); BcdSize = ACPIMMIO16 (XhciFwStarting + BCD_SIZE_OFFSET); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4, AccessWidth16, 0x0000, BcdAddress); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4 + 2, AccessWidth16, 0x0000, BcdSize); AcdAddress = ACPIMMIO16 (XhciFwStarting + ACD_ADDR_OFFSET); AcdSize = ACPIMMIO16 (XhciFwStarting + ACD_SIZE_OFFSET); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8, AccessWidth16, 0x0000, AcdAddress); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8 + 2, AccessWidth16, 0x0000, AcdSize); SpiValidBase = SPI_BASE2 (XhciFwStarting + 4) | SPI_BAR0_VLD | SPI_BASE0 | SPI_BAR1_VLD | SPI_BASE1 | SPI_BAR2_VLD; RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB0, AccessWidth32, 0x00000000, SpiValidBase); // // Copy Type0/1/2 data block from ROM image to MMIO starting from 0xC0 // for (Index = 0; Index < SPI_HEAD_LENGTH; Index++) { RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + Index)); } for (Index = 0; Index < BcdSize; Index++) { RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + BcdAddress + Index)); } for (Index = 0; Index < AcdSize; Index++) { RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + BcdSize + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + AcdAddress + Index)); } // // Step 3. to enable the instruction RAM preload functionality. // FwAddress = ACPIMMIO16 (XhciFwStarting + FW_ADDR_OFFSET); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth16, 0x0000, ACPIMMIO16 (XhciFwStarting + FwAddress)); FwAddress += 2; RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccessWidth16, 0x0000, FwAddress); FwSize = ACPIMMIO16 (XhciFwStarting + FW_SIZE_OFFSET); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccessWidth16, 0x0000, FwSize); // // Set the starting address offset for Instruction RAM preload. // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccessWidth16, 0x0000, 0); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~(UINT32) BIT29, BIT29); for (;;) { ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccessWidth32, &RegData); if (RegData & BIT30) { break; } } RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~(UINT32) BIT29, 0); // // Step 4. to release resets in XHCI_ACPI_MMIO_AMD_REG00. wait for USPLL to lock by polling USPLL lock. // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~(UINT32) U3PLL_RESET, 0); ///Release U3PLLreset for (;;) { ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccessWidth32, &RegData); if (RegData & U3PLL_LOCK) { break; } } RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~(UINT32) U3PHY_RESET, 0); ///Release U3PHY RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~(UINT32) U3CORE_RESET, 0); ///Release core reset // // SuperSpeed PHY Configuration // //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccessWidth32, 0xFFF00000, 0x000AAAAA); //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGD0, AccessWidth32, 0xFFF00000, 0x000AAAAA); FchXhciInitIndirectReg (LocalCfgPtr); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, ~(UINT32) (BIT4 + BIT5), 0); /// Disable Device 22 RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, ~(UINT32) (BIT7), BIT7); /// Enable 2.0 devices RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~(UINT32) (BIT21), BIT21); // // Step 5. // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~(UINT32) (BIT17 + BIT18 + BIT19), BIT17 + BIT18); // // PLUG/UNPLUG of USB 2.0 devices make the XHCI USB 2.0 ports unfunctional - fix enable // ACPI_USB3.0_REG 0x20[12:11] = 2'b11 RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x3 << 11)), (UINT32) (0x3 << 11)); // // XHC 2 USB2 ports interactional issue - fix enable // ACPI_USB3.0_REG 0x20[16] = 1'b1 RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x1 << 16)), (UINT32) (0x1 << 16)); // // XHC USB2.0 Ports suspend Enhancement // ACPI_USB3.0_REG 0x20[15] = 1'b1 // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x1 << 15)), (UINT32) (0x1 << 15)); // // XHC HS/FS IN Data Buffer Underflow issue - fix enable // ACPI_USB3.0_REG 0x20[20:18] = 0x7 // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x7 << 18)), (UINT32) (0x7 << 18)); // // XHC stuck in U3 after system resuming from S3 -fix enable // ACPI_USB3.0_REG 0x98[19] = 1'b1 // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG98, AccessWidth32, ~((UINT32) (0x1 << 19)), (UINT32) (0x1 << 19)); // // Change XHC1 ( Dev 16 function 1) Interrupt Pin register to INTB# - Fix enable // ACPI_PMIO_F0[18] =1 // RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 18)), (UINT32) (0x1 << 18)); // // EHCI3/OHCI3 blocks Blink Global Clock Gating when EHCI/OHCI Dev 22 fn 0/2 are disabled // ACPI_PMIO_F0[13] =1 // RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 13)), (UINT32) (0x1 << 13)); // // Access register through JTAG fail when switch from XHCI to EHCI/OHCI - Fix enable // ACPI_PMIO_F0[17] =1 // RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 17)), (UINT32) (0x1 << 17)); // // USB leakage current on differential lines when ports are switched to XHCI - Fix enable // ACPI_PMIO_F0[14] =1 // RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 14)), (UINT32) (0x1 << 14)); // RRG 8.26 XHCI Clear pending PME on Sx entry RwXhciIndReg ( FCH_XHCI_IND_REG54, ~(UINT32) (BIT15), BIT15, StdHeader); // // UMI Lane Configuration Information for XHCI Firmware to Calculate the Bandwidth for USB 3.0 ISOC Devices // if (!(IsUmiOneLaneGen1Mode (StdHeader))) { RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~(UINT32) (BIT25 + BIT24), BIT24); } // RPR 8.23 FS/LS devices not functional after resume from S4 fix enable (SB02699) RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~(UINT32) (BIT22), BIT22); // RPR 8.24 XHC USB2.0 Hub disable issue fix enable (SB02702) RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(UINT32) (BIT20), BIT20); if ( ReadFchChipsetRevision ( FchDataPtr->StdHeader ) >= FCH_BOLTON ) { // RPR 8.27 Enhance D3Cold ccu sequencing RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG10, AccessWidth32, ~(UINT32) (BIT11), BIT11); // RPR 8.28 Set HCIVERSION to 1.0 RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) (BIT15), BIT15); // RPR 8.29 xHCI 1.0 Sub-Features Supported // Blobk Event Interrupt Flag (BEI) RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) (BIT1), BIT1); // Force Stopped Event (FSE) RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) (BIT2), BIT2); // Software LPM RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) (BIT3), BIT3); // Hardware LPM // Skip TRB IOC Event RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) (BIT6), BIT6); // Remove Secondary Bandwith Domain Reporting RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) (BIT7), BIT7); // Cold Attach Status RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) (BIT8), BIT8); // Endpoint Status Update Ordering RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) (BIT9), BIT9); // Report Event during SKIP on Missed Service Error RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) (BIT10), BIT10); // Soft Retry RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) (BIT11), BIT11); // U3 Exit RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) (BIT12), BIT12); // USB3.0 Link Command RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) (BIT13), BIT13); // MSE FrameId invalid RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) (BIT14), BIT14); // Port Test Mode RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) (BIT16), BIT16); // Miscellaneous Design Improvements RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG40, AccessWidth32, ~(UINT32) (BIT0), BIT0); //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG40, AccessWidth32, ~(UINT32) (BIT25), 0); // RRG 8.29 End // RRG 8.30 XHC USB2 Loopback RX SE0 RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~(UINT32) (BIT13 + BIT14 + BIT21), BIT13 + BIT14 + BIT21); // RRG 8.31 XHC U2IF_Enabled_Quiettermination off RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(UINT32) (BIT20), BIT20); // RRG 8.32 XHC S0 BLM Reset Mode RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF2, AccessWidth8, ~(UINT32) (BIT3), BIT3); // RRG 8.33 Enhance XHC Ent_Flag RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(UINT32) (BIT22), BIT22); // RRG 8.34 Enhance TRB Pointer when both MSE and SKIP TRB IOC evt opened RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) (BIT17), BIT17); // RRG 8.35 LPM Broadcast disable RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) (BIT18), BIT18); // RRG 8.37 Enhance XHC FS/LS connect RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(UINT32) (BIT24), BIT24); // RRG 8.38 Enhance XHC ISOCH td_cmp RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(UINT32) (BIT25), BIT25); // RRG 8.39 LPM Clock 5us Select RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(UINT32) (BIT8), BIT8); // RRG 8.40 Enhance DPP ERR as XactErr RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(UINT32) (BIT9), BIT9); // RRG 8.41 Enhance U2IF PME Enable RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(UINT32) (BIT10), BIT10); // RRG 8.42 U2IF S3 Disconnect detection RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(UINT32) (BIT12), BIT12); // RRG 8.43 Stream Error Handling RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) (BIT20 + BIT21 + BIT22), (BIT20 + BIT21 + BIT22)); // RRG 8.44 FLA Deassert RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) (BIT23), BIT23); // RRG 8.45 LPM Ctrl Improve RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) (BIT27), BIT27); // 393674 Enable fix for control transfer error RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) (BIT24), BIT24); //8.60 Enhance LPM Host initial L1 Exit RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(UINT32) BIT29, BIT29); // RRG 8.46 Enhance resume after disconnect RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG98, AccessWidth32, ~(UINT32) (BIT30), BIT30); // RRG 8.47 Enhance SS HD Detected on Plug-in during S3 RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG98, AccessWidth32, ~(UINT32) (BIT31), BIT31); // RRG 8.48 Frame Babble Reporting RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(UINT32) (BIT27), BIT27); // xHCI Debug Capability // RRG 8.49 DCP Halt RSTSM OFF // RRG 8.50 Enable DCP DPH check // RRG 8.51 DCP LTSSM Inactive to Rxdetect // RRG 8.52 Enhance DCP EP State // RRG 8.53 DCP Remote Wakeup Capable // RRG 8.58 Enable ERDY send once DBC detectes HIT/HOT // RRG 8.59 Block HIT/HOT until service interval done //RegData = FCH_XHCI_IND_REG100; //WriteMem ( ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, &RegData); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG100); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(UINT32) (BIT0 + BIT1 + BIT2), BIT0 + BIT1 + BIT2); //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(UINT32) (BIT0 + BIT1 + BIT2), BIT0 + BIT1 + BIT2); //ReadMem ( ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, &RegData); //RegData = FCH_XHCI_IND_REG120; //WriteMem ( ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, &RegData); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG120); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(UINT32) (BIT3), BIT3); //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(UINT32) (BIT3), BIT3); //ReadMem ( ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, &RegData); //RegData = FCH_XHCI_IND_REG100; //WriteMem ( ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, &RegData); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG100); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(UINT32) (BIT21), BIT21); //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(UINT32) (BIT21), BIT21); //ReadMem ( ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, &RegData); //RegData = FCH_XHCI_IND_REG128; //WriteMem ( ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, &RegData); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG128); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(UINT32) (BIT0), BIT0); //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(UINT32) (BIT0), BIT0); //ReadMem ( ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, &RegData); //RegData = FCH_XHCI_IND_REG100; //WriteMem ( ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, &RegData); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG100); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(UINT32) (BIT3 + BIT4), BIT3 + BIT4); //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(UINT32) (BIT3 + BIT4), BIT3 + BIT4); //ReadMem ( ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, &RegData); // RRG 8.54 Enhance SS HS detected during S3 //RegData = FCH_XHCI_IND_REG48; //WriteMem ( ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, &RegData); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG48); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(UINT32) (BIT1), BIT1); // RRG 8.55 Enhance U1 timer (shorten U1 exit response time) //RegData = FCH_XHCI_IND_REG48; //WriteMem ( ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, &RegData); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG48); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(UINT32) (BIT14), BIT14); // RRG 8.56 Enhance HW LPM U2Entry state RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(UINT32) (BIT17), BIT17); // RRG 8.57 Enhance SSIF PME RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(UINT32) (BIT14), BIT14); // RPR 8.62 Enable FW enhancement on XHC clock control when memory power saving is disabled RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG10, AccessWidth32, ~(UINT32) (BIT13), BIT13); // RPR 8.63 U2IF Remote Wake Select RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(UINT32) (BIT11), BIT11); // RPR 8.64 HS Data Toggle Error Handling RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(UINT32) (BIT16), BIT16); // A1 // UBTS 444589 PIL failures when reset device command hit link td points to invaild trb RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG28, AccessWidth32, ~(UINT32) (BIT3), BIT3); // UBTS 437021 PME not generated by U2IF logic during S3 shutdown RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(UINT32) (BIT30 + BIT31), (BIT30 + BIT31)); // UBTS 432864 When a USB3 device is disconnected, and connected again, xHC cannot detect it. RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG48); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(UINT32) (BIT16), BIT16); // UBTS 430710 USB3 port enters compliance state when debug port enabled (0: enable) RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(UINT32) (BIT27), BIT27); // UBTS 430715 [DbC] Compatibility issue with 3rd party (I) chip as Host and AMD as Target RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG100); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(UINT32) (BIT5), BIT5); // UBTS 430708 The second configure endpoint command haven't been executed completely when the port was in L1 RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(UINT32) (BIT26), BIT26); // UBTS 428048 [LPM] LPM 2ports interrupt in is ERROR after host initiate L1exit respond a nak in HS RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(UINT32) (BIT23), 0); // UBTS 428045 LPM packet with incorrect address RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(UINT32) (BIT22 + BIT24 + BIT25), 0); // UBTS 443139 Buffer overrun during S4 loop RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG48); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(UINT32) (BIT17), BIT17); // UBTS 419582 LPM arbitration between USB ports RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(UINT32) (BIT21), 0); // UBTS 429765 USB3.0 ACPI Indirect registers get changed after reboot RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG28, AccessWidth32, ~(UINT32) (BIT0), BIT0); // UBTS 439658 Black Magic USB 3.0 device when enabled/disabled under windows causes the driver to register disconnect RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG28, AccessWidth32, ~(UINT32) (BIT1 + BIT2), BIT2); // UBTS SS RX terminations blocked unexpectedly RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(UINT32) (BIT15), BIT15); } }
/** * FchXhciInitIndirectReg - Config XHCI Indirect Registers * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchXhciInitIndirectReg ( IN FCH_DATA_BLOCK *FchDataPtr ) { UINT8 Index; UINT32 DrivingStrength; UINT32 Port; UINT32 Register; UINT32 RegValue; FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; DrivingStrength = 0; // // SuperSpeed PHY Configuration (adaptation mode setting) // RwXhciIndReg ( FCH_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021, StdHeader); RwXhciIndReg ( FCH_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021, StdHeader); // // SuperSpeed PHY Configuration (CR phase and frequency filter settings) // RwXhciIndReg ( FCH_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A, StdHeader); RwXhciIndReg ( FCH_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A, StdHeader); // // BLM Meaasge // RwXhciIndReg ( FCH_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000, StdHeader); // // xHCI USB 2.0 PHY Settings // Step 1 is done by hardware default // Step 2 for (Port = 0; Port < 4; Port ++) { DrivingStrength = (UINT32) (LocalCfgPtr->Usb.Xhci20Phy[Port]); if (Port < 2) { RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader); RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + DrivingStrength, StdHeader); RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader); } else { RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + BIT12 + DrivingStrength, StdHeader); RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + DrivingStrength, StdHeader); RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + BIT12 + DrivingStrength, StdHeader); } } // Step 3 RwXhciIndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)), StdHeader); RwXhciIndReg ( FCH_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)), StdHeader); // RPR 8.25 Clock Gating in PHY for (Port = 0; Port < 4; Port ++) { DrivingStrength = 0x1E4; if (Port < 2) { RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + BIT12 + DrivingStrength, StdHeader); Register = FCH_XHCI_IND60_REG00; Index = 0; do { WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader); ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader); Index++; FchStall (10, StdHeader); } while ((RegValue & BIT17) && (Index < 10 )); RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + DrivingStrength, StdHeader); Register = FCH_XHCI_IND60_REG00; Index = 0; do { WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader); ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader); Index++; FchStall (10, StdHeader); } while ((RegValue & BIT17) && (Index < 10 )); RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + BIT12 + DrivingStrength, StdHeader); } else { RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, ((Port - 2) << 13) + BIT12 + DrivingStrength, StdHeader); Register = FCH_XHCI_IND60_REG00; Index = 0; do { WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader); ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader); Index++; FchStall (10, StdHeader); } while ((RegValue & BIT17) && (Index < 10 )); RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, ((Port - 2) << 13) + DrivingStrength, StdHeader); Register = FCH_XHCI_IND60_REG00; Index = 0; do { WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader); ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader); Index++; FchStall (10, StdHeader); } while ((RegValue & BIT17) && (Index < 10 )); RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, ((Port - 2) << 13) + BIT12 + DrivingStrength, StdHeader); } } if ( ReadFchChipsetRevision ( StdHeader ) >= FCH_BOLTON ) { // RRG 8.36 Enhance XHC LS Rise time for (Port = 0; Port < 2; Port ++) { DrivingStrength = 0x1C4; RwXhciIndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader); RwXhciIndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + DrivingStrength, StdHeader); RwXhciIndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader); } RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(UINT32) (BIT23), BIT23); // RPR 8.61 XHCI ISO device CRC false error detection for (Port = 0; Port < 4; Port ++) { if (Port < 2) { ReadXhci0Phy (Port, (0x7 << 7), &DrivingStrength, StdHeader); DrivingStrength &= 0x0000000F8; DrivingStrength |= BIT0 + BIT2; RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader); RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + (0x7 << 7) + DrivingStrength, StdHeader); RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader); } else { ReadXhci1Phy ((Port - 2), (0x7 << 7), &DrivingStrength, StdHeader); DrivingStrength &= 0x0000000F8; DrivingStrength |= BIT0 + BIT2; RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader); RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + (0x7 << 7) + DrivingStrength, StdHeader); RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader); } } //8.64 L1 Residency Duration RwXhciIndReg ( FCH_XHCI_IND60_REG48, 0xFFFFFFFE0, BIT0, StdHeader); } }
/********************************************************************************* * Name: FchXhciOnRecovery * * Description * * * Input * FchPrivate : FCH PEI private data structure * XhciRomAddress : temporary base address value of Xhci controller * * Output * * *********************************************************************************/ EFI_STATUS FchXhciOnRecovery ( IN FCH_PEI_PRIVATE FchPrivate, IN UINT32 XhciRomAddress ) { UINT16 BcdAddress; UINT16 BcdSize; UINT16 AcdAddress; UINT16 AcdSize; UINT16 FwAddress; UINT16 FwSize; UINT32 XhciFwStarting; UINT32 SpiValidBase; UINT32 RegData; UINT16 Index; AMD_CONFIG_PARAMS *StdHeader; UINT8 FchRevision; UINT32 XhcBootRamSize; UINTN RomSigStartingAddr; UINT32 RomStore[NUM_OF_ROMSIG_FILED]; UINT32 SelNum; StdHeader = &FchPrivate.StdHdr; FchRevision = 0; ReadPci (PCI_ADDRESS (0, FCH_ISA_DEV, 0, 0x08), AccessWidth8, &FchRevision, StdHeader); GetRomSigPtr (&RomSigStartingAddr, StdHeader); for ( SelNum = 0; SelNum < NUM_OF_ROMSIG_FILED; SelNum++) { RomStore[SelNum] = ACPIMMIO32 (RomSigStartingAddr + (SelNum << 2)); } if ( XhciRomAddress != 0 ) { RomStore[XHCI_FILED_NUM] = XhciRomAddress; } RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader); for ( SelNum = 1; SelNum < NUM_OF_ROMSIG_FILED; SelNum++) { RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGCC, AccessWidth32, ~ (BIT2 + BIT1 + BIT0), (BIT2 + SelNum), StdHeader); RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGCC, AccessWidth32, ROMSIG_CFG_MASK, RomStore[SelNum], StdHeader); } XhciFwStarting = RomStore[XHCI_FILED_NUM]; RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0x00090000, 0x00400700); FchStall (20, StdHeader); // // Enable SuperSpeed receive special error case logic. 0x20 bit8 // Enable USB2.0 RX_Valid Synchronization. 0x20 bit9 // Enable USB2.0 DIN/SE0 Synchronization. 0x20 bit10 // XhcBootRamSize = XHC_BOOT_RAM_SIZE; RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, 0xFFFFF9FF, 0x00000600); RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG50 + 1, AccessWidth8, ~BIT1, BIT1); // // SuperSpeed PHY Configuration (adaptation timer setting) // XHC U1 LFPS Exit time // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccessWidth32, 0xCFF00000, 0x000AAAAA); //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90 + 0x40, AccessWidth32, 0xFFF00000, 0x000AAAAA); // // Step 1. to enable Xhci IO and Firmware load mode // RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, ~(BIT4 + BIT5), 0); /// Disable Device 22 RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, ~(BIT7), BIT7); /// Enable 2.0 devices RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xF0FFFFFC, 0x01); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xEFFFFFFF, 0x10000000); // // Step 2. to read a portion of the USB3_APPLICATION_CODE from BIOS ROM area and program certain registers. // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA0, AccessWidth32, 0x00000000, (SPI_HEAD_LENGTH << 16)); BcdAddress = ACPIMMIO16 (XhciFwStarting + BCD_ADDR_OFFSET + XhcBootRamSize); BcdSize = ACPIMMIO16 (XhciFwStarting + BCD_SIZE_OFFSET + XhcBootRamSize); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4, AccessWidth16, 0x0000, BcdAddress); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4 + 2, AccessWidth16, 0x0000, BcdSize); AcdAddress = ACPIMMIO16 (XhciFwStarting + ACD_ADDR_OFFSET + XhcBootRamSize); AcdSize = ACPIMMIO16 (XhciFwStarting + ACD_SIZE_OFFSET + XhcBootRamSize); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8, AccessWidth16, 0x0000, AcdAddress); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8 + 2, AccessWidth16, 0x0000, AcdSize); SpiValidBase = SPI_BASE2 (XhciFwStarting + 4 + XHC_BOOT_RAM_SIZE) | SPI_BAR0_VLD | SPI_BASE0 | SPI_BAR1_VLD | SPI_BASE1 | SPI_BAR2_VLD; RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB0, AccessWidth32, 0x00000000, SpiValidBase); // // Copy Type0/1/2 data block from ROM image to MMIO starting from 0xC0 // for (Index = 0; Index < SPI_HEAD_LENGTH; Index++) { RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + XhcBootRamSize + Index)); } for (Index = 0; Index < BcdSize; Index++) { RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + BcdAddress + Index)); } for (Index = 0; Index < AcdSize; Index++) { RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + BcdSize + Index, AccessWidth8, 0, ACPIMMIO8 (XhciFwStarting + AcdAddress + Index)); } // // Step 3. to enable the BOOT RAM preload functionality. // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~BIT0, BIT0); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~BIT29, 0); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccessWidth16, 0x7FFF, BIT15); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccessWidth16, 0x0000, 0); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08 + 2, AccessWidth16, 0x0000, 0x8000); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccessWidth16, 0x0000, 0); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~BIT29, BIT29); for (;;) { ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccessWidth32, &RegData); if (RegData & BIT30) { break; } } RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~BIT29, 0); // // Set the starting address offset for Instruction RAM preload. // FwAddress = ACPIMMIO16 (XhciFwStarting + FW_ADDR_OFFSET + XhcBootRamSize); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth16, 0x0000, ACPIMMIO16 (XhciFwStarting + FwAddress)); FwAddress += 2; RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccessWidth16, 0x0000, FwAddress + XhcBootRamSize); FwSize = ACPIMMIO16 (XhciFwStarting + FW_SIZE_OFFSET + XhcBootRamSize); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccessWidth16, 0x0000, 0); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08 + 2, AccessWidth16, 0x0000, FwSize); // // Step 3.5 to enable the instruction RAM preload functionality. // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccessWidth16, 0x7FFF, 0); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~BIT29, BIT29); for (;;) { ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccessWidth32, &RegData); if (RegData & BIT30) { break; } } RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~BIT29, 0); // // Step 4. to release resets in XHCI_ACPI_MMIO_AMD_REG00. wait for USPLL to lock by polling USPLL lock. // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~U3PLL_RESET, 0); ///Release U3PLLreset for (;;) { ReadMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccessWidth32, &RegData); if (RegData & U3PLL_LOCK) { break; } } RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~U3PHY_RESET, 0); ///Release U3PHY RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~U3CORE_RESET, 0); ///Release core reset FchXhciRecoveryInitIndirectReg ( StdHeader, FchRevision ); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, ~(BIT4 + BIT5), 0); /// Disable Device 22 RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEF, AccessWidth8, ~(BIT7), BIT7); /// Enable 2.0 devices RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~(BIT21), BIT21); // // Step 5. // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, ~(BIT17 + BIT18 + BIT19), BIT17 + BIT18 + BIT19); // // PLUG/UNPLUG of USB 2.0 devices make the XHCI USB 2.0 ports unfunctional - fix enable // ACPI_USB3.0_REG 0x20[12:11] = 2'b11 RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x3 << 11)), (UINT32) (0x3 << 11)); // // XHC 2 USB2 ports interactional issue - fix enable // ACPI_USB3.0_REG 0x20[16] = 1'b1 RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x1 << 16)), (UINT32) (0x1 << 16)); // // XHC USB2.0 Ports suspend Enhancement // ACPI_USB3.0_REG 0x20[15] = 1'b1 // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x1 << 15)), (UINT32) (0x1 << 15)); // // XHC HS/FS IN Data Buffer Underflow issue - fix enable // ACPI_USB3.0_REG 0x20[20:18] = 0x7 // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~((UINT32) (0x7 << 18)), (UINT32) (0x7 << 18)); // // EHCI3/OHCI3 blocks Blink Global Clock Gating when EHCI/OHCI Dev 22 fn 0/2 are disabled // ACPI_PMIO_F0[13] =1 // RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 13)), (UINT32) (0x1 << 13)); // // USB leakage current on differential lines when ports are switched to XHCI - Fix enable // ACPI_PMIO_F0[14] =1 // RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~((UINT32) (0x1 << 14)), (UINT32) (0x1 << 14)); // RRG 8.26 XHCI Clear pending PME on Sx entry RwXhciIndReg ( FCH_XHCI_IND_REG54, ~(BIT15), BIT15, StdHeader); // // UMI Lane Configuration Information for XHCI Firmware to Calculate the Bandwidth for USB 3.0 ISOC Devices // RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~(BIT25 + BIT24), BIT24); // RPR 8.23 FS/LS devices not functional after resume from S4 fix enable (SB02699) RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~(BIT22), BIT22); // RPR 8.24 XHC USB2.0 Hub disable issue fix enable (SB02702) RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT20), BIT20); // Set HCIVERSION to 1.0 RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT15), BIT15); // xHCI 1.0 Sub-Features Supported // Blobk Event Interrupt Flag (BEI) RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT1), BIT1); // Force Stopped Event (FSE) RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT2), BIT2); // Software LPM RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT3), 0); // Hardware LPM // Skip TRB IOC Event RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT6), BIT6); // Remove Secondary Bandwith Domain Reporting RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT7), BIT7); // Cold Attach Status RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT8), BIT8); // Endpoint Status Update Ordering RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT9), BIT9); // Report Event during SKIP on Missed Service Error RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT10), BIT10); // Soft Retry RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT11), BIT11); // U3 Exit RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT12), BIT12); // USB3.0 Link Command RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT13), BIT13); // MSE FrameId invalid RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT14), BIT14); // Port Test Mode RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT16), BIT16); // Miscellaneous Design Improvements RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG40, AccessWidth32, ~(BIT0), BIT0); //RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG40, AccessWidth32, ~(BIT25), 0); // XHC USB2 Loopback RX SE0 RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccessWidth32, ~(BIT13 + BIT14 + BIT21), BIT13 + BIT14 + BIT21); // XHC U2IF_Enabled_Quiettermination off RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT20), BIT20); // XHC S0 BLM Reset Mode RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF2, AccessWidth8, ~(BIT3), BIT3); // Enhance XHC Ent_Flag RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT22), BIT22); // Enhance TRB Pointer when both MSE and SKIP TRB IOC evt opened RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT17), BIT17); // LPM Broadcast disable RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT18), BIT18); // Enhance XHC FS/LS connect RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT24), BIT24); // Enhance XHC ISOCH td_cmp RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT25), BIT25); // LPM Clock 5us Select RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(BIT8), BIT8); // Enhance DPP ERR as XactErr RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(BIT9), BIT9); // Enhance U2IF PME Enable RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(BIT10), BIT10); // U2IF S3 Disconnect detection RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(BIT12), BIT12); // Stream Error Handling RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT20 + BIT21 + BIT22), (BIT20 + BIT21 + BIT22)); // FLA Deassert RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT23), BIT23); // Enhance LPM Host initial L1 Exit RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~BIT29, BIT29); // Enhance resume after disconnect RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG98, AccessWidth32, ~(BIT30), BIT30); // Enhance SS HD Detected on Plug-in during S3 RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG98, AccessWidth32, ~(BIT31), BIT31); // Frame Babble Reporting RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT27), BIT27); // xHCI Debug Capability // DCP Halt RSTSM OFF // Enable DCP DPH check // DCP LTSSM Inactive to Rxdetect // Enhance DCP EP State // DCP Remote Wakeup Capable // Enable ERDY send once DBC detectes HIT/HOT // Block HIT/HOT until service interval done RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG100); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(BIT0 + BIT1 + BIT2), BIT0 + BIT1 + BIT2); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG120); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(BIT3), BIT3); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG100); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(BIT21), BIT21); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG128); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(BIT0), BIT0); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG100); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(BIT3 + BIT4), BIT3 + BIT4); // Enhance SS HS detected during S3 RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG48); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(BIT1), BIT1); // Enhance U1 timer (shorten U1 exit response time) RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG48); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(BIT14), BIT14); // Enhance HW LPM U2Entry state RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(BIT17), BIT17); // Enhance SSIF PME RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(BIT15 + BIT14), (BIT15 + BIT14)); // U2IF Remote Wake Select RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(BIT11), BIT11); // HS Data Toggle Error Handling RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(BIT16), BIT16); // USB20PHY FL Speed select RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT28), BIT28); // Enable Fix for DBC compatibility RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG100); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(BIT5), BIT5); // Enable Fix for ACPI registers write issue. RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG28, AccessWidth32, ~(BIT0), BIT0); // // For BTS only // // LPM reated items // HwLpmAddrSel (22) U2LpmTranArbEn, ColdAttachMode. RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(BIT20 + BIT21 + BIT22), (BIT20 + BIT21 + BIT22)); // HwLpmStateSel (24), HwLpmDeconfigL1Exit (25), HwLpmL1StopEpEn (26). RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG24, AccessWidth32, ~(BIT24 + BIT25 + BIT26), (BIT24 + BIT25 + BIT26)); // Xhci10En: xHCI 10 Enable (0), HwLpmEn (4), SkipTrbIocEvtLenMode (24) RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG30, AccessWidth32, ~(BIT0 + BIT4 + BIT24), (BIT4 + BIT24)); // DcpNumP1En RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG100); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~ BIT5, BIT5); // LtssmDisconnectToConnect RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, FCH_XHCI_IND_REG48); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, ~(BIT16), BIT16); // CcuMode RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG10, AccessWidth32, 0xFFFF00FF, 0x2A00); // XtalPciClk_UseEcClkSel clear RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG50 + 1, AccessWidth8, ~BIT1, 0); // Change PHY LFPS Detection threshold (RX_LFPSDET_TH[2:0]) to 6h from default setting 4h RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, 0x80); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, 0xFFFFFFF8, 0x06); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG48, AccessWidth32, 0x00000000, 0xC0); RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG4C, AccessWidth32, 0xFFFFFFF8, 0x06); return EFI_SUCCESS; }
/** * FchInitResetHwAcpi - Config HwAcpi controller during Power-On * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchInitResetHwAcpi ( IN VOID *FchDataPtr ) { UINT16 SmbusBase; UINT8 Value; UINT16 AsfPort; UINT32 GeventEnableBits; UINT32 GeventValue; FCH_RESET_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; // // Set Build option into SB // WritePci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG64, AccessWidth16, &(UserOptions.FchBldCfg->CfgSioPmeBaseAddress), StdHeader); // // Enabled SMBUS0/SMBUS1 (ASF) Base Address // RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2C, AccessWidth16, 06, (UserOptions.FchBldCfg->CfgSmbus0BaseAddress) + BIT0); ///protect BIT[2:1] RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG28, AccessWidth16, 06, (UserOptions.FchBldCfg->CfgSmbus1BaseAddress) + BIT0); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr)); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG62, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr)); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr)); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG66, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgCpuControlBlkAddr)); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG68, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr)); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6A, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgSmiCmdPortAddr)); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6E, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgSmiCmdPortAddr) + 8); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG48, AccessWidth32, 00, (UserOptions.FchBldCfg->CfgWatchDogTimerBase)); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2E, AccessWidth8, (UINT32)~(BIT1 + BIT2), 0); ///clear BIT[2:1] SmbusBase = (UINT16) (UserOptions.FchBldCfg->CfgSmbus0BaseAddress); Value = 0x00; LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &Value, StdHeader); ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchInitResetAcpiMmioTable[0]), StdHeader); if (UserOptions.FchBldCfg->CfgFchGpioControl != NULL) { ProgramFchGpioTbl ((UserOptions.FchBldCfg->CfgFchGpioControl), LocalCfgPtr); } if (UserOptions.FchBldCfg->CfgFchSataPhyControl != NULL) { ProgramFchSataPhyTbl ((UserOptions.FchBldCfg->CfgFchSataPhyControl), LocalCfgPtr); } // // RTC Workaround for Daylight saving time enable bit // RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5E, AccessWidth8, 0, 0); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5F, AccessWidth8, 0xFE, BIT0 ); // Enable DltSavEnable Value = 0x0B; LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader); LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); Value &= 0xFE; LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5E, AccessWidth8, 0, 0); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5F, AccessWidth8, 0xFE, 0 ); // Disable DltSavEnable // // Prevent RTC error // Value = 0x0A; LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader); LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); Value &= 0xEF; LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); Value = 0x08; LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader); LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); if ( !LocalCfgPtr->EcKbd ) { // // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input // Value = Value | 0x0A; } LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); if ( UserOptions.FchBldCfg->CfgFchRtcWorkAround ) { Value = RTC_WORKAROUND_SECOND; LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader); LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); if ( Value > RTC_VALID_SECOND_VALUE ) { Value = RTC_SECOND_RESET_VALUE; LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); } LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); Value &= RTC_SECOND_LOWER_NIBBLE; if ( Value > RTC_VALID_SECOND_VALUE_LN ) { LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); Value = RTC_SECOND_RESET_VALUE; LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader); } } Value = 0x09; LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader); LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); if ( !LocalCfgPtr->EcKbd ) { // // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input // Value = Value & 0xF9; } if ( LocalCfgPtr->LegacyFree ) { // // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation. // Value = Value & 0x9F; } // // Enabled IRQ input // Value = Value | BIT4; LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader); AsfPort = ((UINT16) UserOptions.FchBldCfg->CfgSmbus1BaseAddress & 0xFFF0); if ( AsfPort != 0 ) { UINT8 dbValue; dbValue = 0x70; LibAmdIoWrite (AccessWidth8, AsfPort + 0x0E, &dbValue, StdHeader); dbValue = 0x2F; LibAmdIoWrite (AccessWidth8, AsfPort + 0x0A, &dbValue, StdHeader); } // // PciExpWakeStatus workaround // ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, &AsfPort); AsfPort++; ReadMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG04, AccessWidth32, &GeventEnableBits); ReadMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG00, AccessWidth32, &GeventValue); if ( (GeventValue & GeventEnableBits) != 0 ) { Value = 0x40; LibAmdIoWrite (AccessWidth8, AsfPort, &Value, StdHeader); } LibAmdIoRead (AccessWidth8, AsfPort, &Value, StdHeader); if ((Value & (BIT2 + BIT0)) != 0) { Value = 0x40; LibAmdIoWrite (AccessWidth8, AsfPort, &Value, StdHeader); } // // Set ACPIMMIO by OEM Input table // if ( LocalCfgPtr->OemResetProgrammingTablePtr != NULL ) { ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE *) (LocalCfgPtr->OemResetProgrammingTablePtr), StdHeader); } }
/** * FchXhciInitIndirectReg - Config XHCI Indirect Registers * * * * @param[in] StdHeader AMD Standard Header * @param[in] FchRevision FCH Chip revision * */ VOID FchXhciRecoveryInitIndirectReg ( IN AMD_CONFIG_PARAMS *StdHeader, IN UINT8 FchRevision ) { UINT8 Index; UINT32 DrivingStrength; UINT32 Port; UINT32 Register; UINT32 RegValue; UINT32 Xhci20Phy[MAX_XHCI_PORTS]; Xhci20Phy[0] = 0x21; Xhci20Phy[1] = 0x21; Xhci20Phy[2] = 0x24; Xhci20Phy[3] = 0x24; DrivingStrength = 0; // // SuperSpeed PHY Configuration (adaptation mode setting) // RwXhciIndReg ( FCH_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021, StdHeader); RwXhciIndReg ( FCH_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021, StdHeader); // // BLM Meaasge // RwXhciIndReg ( FCH_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000, StdHeader); // // xHCI USB 2.0 PHY Settings // Step 1 is done by hardware default // Step 2 for (Port = 0; Port < 2; Port ++) { DrivingStrength = (UINT32) (Xhci20Phy[Port]); RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader); RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + DrivingStrength, StdHeader); RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader); } RwXhci0IndReg ( FCH_XHCI_IND60_REG50, ~ ((UINT32) (0x0f)), ((UINT32) (0x07)), StdHeader); RwXhci0IndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 4)), ((UINT32) (0x02 << 4)), StdHeader); RwXhci0IndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)), StdHeader); RwXhci0IndReg ( FCH_XHCI_IND60_REG08, 0x80FC00FF, 0, StdHeader); // RPR 8.25 Clock Gating in PHY for (Port = 0; Port < 4; Port ++) { DrivingStrength = 0x1E4; if (Port < 2) { RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + BIT12 + DrivingStrength, StdHeader); Register = FCH_XHCI_IND60_REG00; Index = 0; do { WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader); ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader); Index++; FchStall (10, StdHeader); } while ((RegValue & BIT17) && (Index < 10 )); RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + DrivingStrength, StdHeader); Register = FCH_XHCI_IND60_REG00; Index = 0; do { WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader); ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader); Index++; FchStall (10, StdHeader); } while ((RegValue & BIT17) && (Index < 10 )); RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + BIT12 + DrivingStrength, StdHeader); } } // Enhance XHC LS Rise time for (Port = 0; Port < 2; Port ++) { DrivingStrength = 0x1C4; RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader); RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + DrivingStrength, StdHeader); RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader); } RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT23), BIT23); // XHCI ISO device CRC false error detection for (Port = 0; Port < 4; Port ++) { if (Port < 2) { ReadXhci0Phy (Port, (0x7 << 7), &DrivingStrength, StdHeader); DrivingStrength &= 0x0000000F8; DrivingStrength |= BIT0 + BIT2; RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader); RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + (0x7 << 7) + DrivingStrength, StdHeader); RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader); } } // L1 Residency Duration RwXhci0IndReg ( FCH_XHCI_IND60_REG48, 0xFFFFFFFE0, BIT0, StdHeader); }
/** * C3PopupSetting - Program Fch C state function * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID C3PopupSetting ( IN VOID *FchDataPtr ) { #define NON_SUPPORT_PREVIOUS_C3 TRUE #ifndef NON_SUPPORT_PREVIOUS_C3 UINT32 Value; BOOLEAN ProcessorPresent; // // C-State and VID/FID Change // ProcessorPresent = GetActiveCoresInGivenSocket (0, &Value, ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader); if (ProcessorPresent && (Value > 1)) { // //PM 0x80[2]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated. //PM 0x80[1]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD //PM 0x7E[6]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the FCH will de-assert //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time. // RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth8, ~(UINT32) (BIT1 + BIT2), (BIT1 + BIT2)); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7E, AccessWidth8, ~(UINT32) BIT6, BIT6); } // //PM 0x80 [8] = 0 for system with NB //Note: North bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link. //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle. //PM_IO 0x80[3]=1, Ignore BM_STS_SET message from NB // RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(UINT32) (BIT9 + BIT8 + BIT7 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x21F); // //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT //link is disconnected. // RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94 + 2, AccessWidth8, 0, 0x10); // //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The //delay will allow USB DMA to go on in a continuous manner // RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG98 + 1, AccessWidth8, 0, 0x10); // // ASIC info // RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7C, AccessWidth8, 0, 0x85); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7C + 1, AccessWidth8, 0, 0x01); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7E + 1, AccessWidth8, ~(UINT32) (BIT7 + BIT5), BIT7 + BIT5); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88 + 1, AccessWidth8, ~(UINT32) BIT4, BIT4); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG98 + 3, AccessWidth8, 0, 0x10); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGB4 + 1, AccessWidth8, 0, 0x0B); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88, AccessWidth8, ~(UINT32) (BIT4 + BIT5), BIT4 + BIT5); #else // C-State and VID/FID Change RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88, AccessWidth8, ~(UINT32) (BIT5), BIT5); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(UINT32) (BIT2), BIT2); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(UINT32) (BIT1), BIT1); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7E, AccessWidth8, ~(UINT32) (BIT6), BIT6); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x01); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG89, AccessWidth8, ~(UINT32) BIT4, BIT4); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88, AccessWidth8, ~(UINT32) BIT4, BIT4); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG9B, AccessWidth8, ~(UINT32) (BIT6 + BIT5 + BIT4), BIT4); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG9B, AccessWidth8, ~(UINT32) (BIT1 + BIT0), 0); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG96, AccessWidth8, 0, 0x10); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG99, AccessWidth8, 0, 0x10); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG8E, AccessWidth8, 0, 0x80); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG97, AccessWidth8, ~(UINT32) (BIT1 + BIT0), 0); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(UINT32) (BIT4), BIT4); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(UINT32) (BIT9), BIT9); RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(UINT32) (BIT7), 0); #endif }
/** * HwmInitRegister - Init Hardware Monitor Register. * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID HwmInitRegister ( IN VOID *FchDataPtr ) { RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xB2, AccessWidth8, 0, 0x55); RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xB3, AccessWidth8, 0, 0x55); RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x91, AccessWidth8, 0, 0x55); RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x92, AccessWidth8, 0, 0x55); RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x00, AccessWidth8, 0, 0x06); RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x10, AccessWidth8, 0, 0x06); RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x20, AccessWidth8, 0, 0x06); RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x30, AccessWidth8, 0, 0x06); RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x40, AccessWidth8, 0, 0x06); RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x66, AccessWidth8, 0, 0x01); RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x6B, AccessWidth8, 0, 0x01); RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x70, AccessWidth8, 0, 0x01); RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x75, AccessWidth8, 0, 0x01); RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x7A, AccessWidth8, 0, 0x01); RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xE6, AccessWidth8, 0xff, 0x02); RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xF8, AccessWidth8, 0, 0x05); RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xF9, AccessWidth8, 0, 0x06); RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xFF, AccessWidth8, 0, 0x42); RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xE9, AccessWidth8, 0, 0xFF); RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xEB, AccessWidth8, 0, 0x1F); //RPR 2.12 HWM Sensor Clk RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xEF, AccessWidth8, 0, 0x0A); RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xFB, AccessWidth8, 0, 0x00); //2.9 Enhancement of FanOut0 Control RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x50 , AccessWidth32, (UINT32)~ (BIT11 + BIT20), (BIT11 + BIT20)); RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xB6 , AccessWidth8, 0x0F, 0x10); }