static int s3c64xx_i2s_cfg_gpio(struct platform_device *pdev)
{
unsigned int base;
switch (pdev->id) {
case 0:
base = S3C64XX_GPD(0);
break;
case 1:
base = S3C64XX_GPE(0);
break;
case 2:
s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin_range(S3C64XX_GPH(6), 4, S3C_GPIO_SFN(5));
return 0;
default:
printk(KERN_DEBUG "Invalid I2S Controller number: %d\n",
pdev->id);
return -EINVAL;
}
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3));
return 0;
}
static int s3c64xx_i2s_probe(struct platform_device *pdev,
struct snd_soc_dai *dai)
{
/* configure GPIO for i2s port */
switch (dai->id) {
case 0:
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_I2S0_CLK);
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_I2S0_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_I2S0_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_I2S0_DI);
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_I2S0_DO);
break;
case 1:
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_I2S1_CLK);
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_I2S1_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI);
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_DO);
break;
case 2:
s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S_V40_DO0);
s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S_V40_DO1);
s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S_V40_DO2);
s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C64XX_GPH6_I2S_V40_BCLK);
s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C64XX_GPH7_I2S_V40_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPH(8), S3C64XX_GPH8_I2S_V40_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPH(9), S3C64XX_GPH9_I2S_V40_DI);
break;
}
return 0;
}
static int mcp251x_ioSetup(struct spi_device *spi)
{
printk(KERN_INFO "mcp251x: setup gpio pins CS and External Int\n");
s3c_gpio_setpull(S3C64XX_GPL(8), S3C_GPIO_PULL_UP); // External interrupt from CAN controller
s3c_gpio_cfgpin(S3C64XX_GPL(8), S3C_GPIO_SFN(3)); // External interrupt from CAN controller (hopefully external interrupt)
//s3c_gpio_cfgpin(S3C64XX_GPL(8), S3C_GPIO_INPUT); // External interrupt from CAN controller
s3c_gpio_setpull(S3C64XX_GPC(7), S3C_GPIO_PULL_NONE); // Manual chip select pin as used in 6410_set_cs
s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C_GPIO_OUTPUT); // Manual chip select pin as used in 6410_set_cs
return 0;
}
static int s3c64xx_i2sv4_cfg_gpio(struct platform_device *pdev)
{
s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S_V40_DO0);
s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S_V40_DO1);
s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S_V40_DO2);
s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C64XX_GPH6_I2S_V40_BCLK);
s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C64XX_GPH7_I2S_V40_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPH(8), S3C64XX_GPH8_I2S_V40_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPH(9), S3C64XX_GPH9_I2S_V40_DI);
return 0;
}
static int s3c64xx_i2sv4_probe(struct platform_device *pdev,
struct snd_soc_dai *dai)
{
/* configure GPIO for i2s port */
s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S_V40_DO0);
s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S_V40_DO1);
s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S_V40_DO2);
s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C64XX_GPH6_I2S_V40_BCLK);
s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C64XX_GPH7_I2S_V40_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPH(8), S3C64XX_GPH8_I2S_V40_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPH(9), S3C64XX_GPH9_I2S_V40_DI);
return 0;
}
static void setup_pin_cs0(void)
{
int ret;
//ret = gpio_request(S3C64XX_GPP(8), "CS0");
ret = gpio_request(S3C64XX_GPC(3), "CS0");
if (ret) {
printk(KERN_ERR "SPI: Setup CS-Pin0 Error\n");
}
printk(KERN_INFO "SPI: Set output pin 3 enabled\n");
//s3c_gpio_setpull(S3C64XX_GPP(8), S3C_GPIO_PULL_UP); // Manual chip select pin as used in 6410_set_cs
s3c_gpio_setpull(S3C64XX_GPC(3), S3C_GPIO_PULL_NONE); // Manual chip select pin as used in 6410_set_cs
s3c_gpio_cfgpin(S3C64XX_GPC(3), S3C_GPIO_OUTPUT); // Manual chip select pin as used in 6410_set_cs
//s3c_gpio_cfgpin(S3C64XX_GPP(8), S3C_GPIO_OUTPUT); // Manual chip select pin as used in 6410_set_cs
};
static void __init hmt_machine_init(void)
{
s3c_i2c0_set_platdata(NULL);
s3c_fb_set_platdata(&hmt_lcd_pdata);
s3c_nand_set_platdata(&hmt_nand_info);
gpio_request(S3C64XX_GPC(7), "usb power");
gpio_direction_output(S3C64XX_GPC(7), 0);
gpio_request(S3C64XX_GPM(0), "usb power");
gpio_direction_output(S3C64XX_GPM(0), 1);
gpio_request(S3C64XX_GPK(7), "usb power");
gpio_direction_output(S3C64XX_GPK(7), 1);
gpio_request(S3C64XX_GPF(13), "usb power");
gpio_direction_output(S3C64XX_GPF(13), 1);
platform_add_devices(hmt_devices, ARRAY_SIZE(hmt_devices));
}
void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
{
/* Set all the necessary GPH pins to special-function 3 */
s3c_gpio_cfgrange_nopull(S3C64XX_GPH(6), width, S3C_GPIO_SFN(3));
/* Set all the necessary GPC pins to special-function 3 */
s3c_gpio_cfgrange_nopull(S3C64XX_GPC(4), 2, S3C_GPIO_SFN(3));
}
void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
{
unsigned int gpio;
unsigned int end;
end = S3C64XX_GPH(6 + width);
/* Set all the necessary GPH pins to special-function 1 */
for (gpio = S3C64XX_GPH(6); gpio < end; gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
/* Set all the necessary GPC pins to special-function 1 */
for (gpio = S3C64XX_GPC(4); gpio < S3C64XX_GPC(6); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
}
/*
* gpio 设置,配置GPIO功能
* */
static void gpio_select(void)
{
#ifdef _DEBUG_GM814X
printk(KERN_INFO "2.1-----gpio_select\n");
#endif
//SPI0
s3c_gpio_cfgpin(S3C64XX_GPC(0), S3C64XX_GPC0_SPI_MISO0);
s3c_gpio_cfgpin(S3C64XX_GPC(1), S3C64XX_GPC1_SPI_CLK0);
s3c_gpio_cfgpin(S3C64XX_GPC(2), S3C64XX_GPC2_SPI_MOSI0);
s3c_gpio_cfgpin(S3C64XX_GPC(3), S3C64XX_GPC3_SPI_nCS0);
s3c_gpio_setpull(S3C64XX_GPC(0), S3C_GPIO_PULL_NONE);
s3c_gpio_setpull(S3C64XX_GPC(1), S3C_GPIO_PULL_NONE);
s3c_gpio_setpull(S3C64XX_GPC(2), S3C_GPIO_PULL_NONE);
s3c_gpio_setpull(S3C64XX_GPC(3), S3C_GPIO_PULL_NONE);
//GPL13 SET ----GM8142_RST--------new6410
if( (gpio_request(S3C64XX_GPL(13), "GPL13_RST") == 0) &&
(gpio_direction_output(S3C64XX_GPL(13), 1) == 0))
{
gpio_export(S3C64XX_GPL(13), 0);
gpio_set_value(S3C64XX_GPL(13), 0); //RST LOW
udelay(400);
gpio_set_value(S3C64XX_GPL(13), 1); //RST HIGH
udelay(400);
}
else {
printk(KERN_ERR "GM8142: cluld not obtain gpio for 'GPK8_RST'\n");
}
//GPL14 SET----GM8142_SHDN
if( (gpio_request(S3C64XX_GPL(14), "GPL14_SHDN") == 0) &&
(gpio_direction_output(S3C64XX_GPL(14), 1) == 0))
{
gpio_export(S3C64XX_GPL(14), 0);
gpio_set_value(S3C64XX_GPL(14), 1); //SHDN=1，正常工作模式
if( gpio_get_value(S3C64XX_GPL(14)) == 0)
{
printk(KERN_ERR "GM8142: can't set GPL(14) SHDN = 1\n");
}
}
else {
printk(KERN_ERR "GM8142: cluld not obtain gpio for 'GPL14_SHDN'\n");
}
s3c_gpio_cfgpin(S3C64XX_GPN(4), S3C_GPIO_SFN(2)); //配置GPN4为外中断
s3c_gpio_setpull(S3C64XX_GPN(4), S3C_GPIO_PULL_NONE); //不上拉也不下拉，硬件默认拉高
//set_irq_type(S3C64XX_GPN(4), IRQ_TYPE_EDGE_BOTH); //发送和接收数据都会触发
set_irq_type(S3C64XX_GPN(4), IRQ_TYPE_LEVEL_LOW); //低电平触发
//set_irq_type(S3C64XX_GPN(4), IRQ_TYPE_EDGE_FALLING);
}
void s3c6410_mcp2515_init(void)
{
// printk("%s:%d\n",__FUNCTION__,__LINE__);
s3c_gpio_cfgpin(S3C64XX_GPC(0), S3C64XX_GPC0_SPI_MISO0);
s3c_gpio_cfgpin(S3C64XX_GPC(1), S3C64XX_GPC1_SPI_CLK0);
s3c_gpio_cfgpin(S3C64XX_GPC(2), S3C64XX_GPC2_SPI_MOSI0);
s3c_gpio_cfgpin(S3C64XX_GPC(3), S3C64XX_GPC3_SPI_nCS0);
s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_EINT_G2_7);
s3c_cs_config(S3C64XX_GPC(5), S3C64XX_GPC_OUTPUT(5),CS_LOW);
s3c_cs_set(S3C64XX_GPC(5),CS_LOW);
// printk("%s:%d\n",__FUNCTION__,__LINE__);
}
/* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
* The emulated CS is toggled by board specific mechanism, as it can
* be either some immediate GPIO or some signal out of some other
* chip in between ... or some yet another way.
* We simply do not assume anything about CS.
*/
static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
{
unsigned int base;
switch (pdev->id) {
case 0:
base = S3C64XX_GPC(0);
break;
case 1:
base = S3C64XX_GPC(4);
break;
default:
dev_err(&pdev->dev, "Invalid SPI Controller number!");
return -EINVAL;
}
s3c_gpio_cfgall_range(base, 3,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
return 0;
}
static int __init smdk6410_init(void)
{
int ret;
unsigned int *reg_GPHCON1;
unsigned int *reg_GPCCON;
reg_GPHCON1 = ioremap(0x7f0080e4,0x100);
reg_GPCCON = ioremap(0x7f008040,0x100);
s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C64XX_GPH6_I2S_V40_BCLK);
s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C64XX_GPH7_I2S_V40_CDCLK);
writel(0x50550000, reg_GPCCON);
writel(0x00000055, reg_GPHCON1);
s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S_V40_DO0);
s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S_V40_DO1);
s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S_V40_DO2);
/* pull-up-enable, pull-down-disable*/
s3c_gpio_setpull(S3C64XX_GPH(6), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPH(7), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPH(8), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPH(9), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPC(4), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPC(5), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPC(7), S3C_GPIO_PULL_UP);
smdk6410_snd_device = platform_device_alloc("soc-audio", -1);
if (!smdk6410_snd_device)
return -ENOMEM;
platform_set_drvdata(smdk6410_snd_device, &smdk6410_snd_devdata);
smdk6410_snd_devdata.dev = &smdk6410_snd_device->dev;
ret = platform_device_add(smdk6410_snd_device);
if (ret)
platform_device_put(smdk6410_snd_device);
return ret;
}
.ngpio = S3C64XX_GPIO_A_NR,
.label = "GPA",
},
}, {
.base = S3C64XX_GPB_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPB(0),
.ngpio = S3C64XX_GPIO_B_NR,
.label = "GPB",
},
}, {
.base = S3C64XX_GPC_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPC(0),
.ngpio = S3C64XX_GPIO_C_NR,
.label = "GPC",
},
}, {
.base = S3C64XX_GPD_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPD(0),
.ngpio = S3C64XX_GPIO_D_NR,
.label = "GPD",
},
}, {
.base = S3C64XX_GPE_BASE,
.config = &gpio_4bit_cfg_noint,
.chip = {
#include <linux/mfd/wm8994/pdata.h>
#include <linux/regulator/machine.h>
#include <sound/wm5100.h>
#include <sound/wm8996.h>
#include <sound/wm8962.h>
#include <sound/wm9081.h>
#include <plat/s3c64xx-spi.h>
#include <mach/crag6410.h>
static struct s3c64xx_spi_csinfo wm0010_spi_csinfo = {
.set_level = gpio_set_value,
.line = S3C64XX_GPC(3),
};
static struct spi_board_info wm1253_devs[] = {
[0] = {
.modalias = "wm0010",
.bus_num = 0,
.chip_select = 0,
.mode = SPI_MODE_0,
.controller_data = &wm0010_spi_csinfo,
},
};
static struct wm5100_pdata wm5100_pdata = {
.ldo_ena = S3C64XX_GPN(7),
.irq_flags = IRQF_TRIGGER_HIGH,
int s3c64xx_spi1_cfg_gpio(void)
{
s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
return 0;
}
/* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
* The emulated CS is toggled by board specific mechanism, as it can
* be either some immediate GPIO or some signal out of some other
* chip in between ... or some yet another way.
* We simply do not assume anything about CS.
*/
static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S3C64XX_GPC(0), S3C64XX_GPC0_SPI_MISO0);
s3c_gpio_cfgpin(S3C64XX_GPC(1), S3C64XX_GPC1_SPI_CLKO);
s3c_gpio_cfgpin(S3C64XX_GPC(2), S3C64XX_GPC2_SPI_MOSIO);
s3c_gpio_setpull(S3C64XX_GPC(0), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPC(1), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPC(2), S3C_GPIO_PULL_UP);
break;
case 1:
s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_SPI_MISO1);
s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_SPI_CLK1);
s3c_gpio_cfgpin(S3C64XX_GPC(6), S3C64XX_GPC6_SPI_MOSI1);
s3c_gpio_setpull(S3C64XX_GPC(4), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPC(5), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPC(6), S3C_GPIO_PULL_UP);
break;
default:
dev_err(&pdev->dev, "Invalid SPI Controller number!");
return -EINVAL;
}
return 0;
}
.resource = dm9000_resources,
.dev = {
.platform_data = &dm9000_setup,
}
};
#endif //#ifdef CONFIG_DM9000
/*add by fatfish for mcp251x*/
static void cs_set_level(unsigned line_id, int lvl) {
gpio_direction_output(line_id, lvl);
};
static struct s3c64xx_spi_csinfo s3c64xx_spi1_csinfo = {
.fb_delay=0x3,
.line=S3C64XX_GPC(7),
.set_level=cs_set_level,
};
static int mcp251x_ioSetup(struct spi_device *spi)
{
printk(KERN_INFO "mcp251x: setup gpio pins CS and External Int\n");
s3c_gpio_setpull(S3C64XX_GPL(8), S3C_GPIO_PULL_UP); // External interrupt from CAN controller
s3c_gpio_cfgpin(S3C64XX_GPL(8), S3C_GPIO_SFN(3)); // External interrupt from CAN controller (hopefully external interrupt)
//s3c_gpio_cfgpin(S3C64XX_GPL(8), S3C_GPIO_INPUT); // External interrupt from CAN controller
s3c_gpio_setpull(S3C64XX_GPC(7), S3C_GPIO_PULL_NONE); // Manual chip select pin as used in 6410_set_cs
s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C_GPIO_OUTPUT); // Manual chip select pin as used in 6410_set_cs
return 0;
}
static struct mcp251x_platform_data mcp251x_info = {
/*
* s3c6410_spi_probe - probe spi driver
* @pdev : platform device struct
*
* platform driver member function for probing
*/
static int s3c6410_spi_probe(struct platform_device *pdev)
{
struct s3c6410_spi *hw;
struct spi_master *master;
struct spi_board_info *bi;
struct resource *res;
int err = 0;
int i;
unsigned int spi_chcfg;
master = spi_alloc_master(&pdev->dev, sizeof(struct s3c6410_spi));
if (master == NULL) {
dev_err(&pdev->dev, "No memory for spi_master\n");
err = -ENOMEM;
goto err_nomem;
}
hw = spi_master_get_devdata(master);
memset(hw, 0, sizeof(struct s3c6410_spi));
hw->master = spi_master_get(master);
hw->master->num_chipselect = 2;
hw->pdata = pdev->dev.platform_data;
hw->dev = &pdev->dev;
hw->id = pdev->id;
hw->bits_per_word = 16;
if (hw->pdata == NULL) {
dev_err(&pdev->dev, "No platform data supplied\n");
err = -ENOENT;
goto err_no_pdata;
}
platform_set_drvdata(pdev, hw);
/* setup the state for the bitbang driver */
hw->bitbang.master = hw->master;
hw->bitbang.setup_transfer = s3c6410_spi_setupxfer;
hw->bitbang.chipselect = s3c6410_spi_chipsel;
hw->bitbang.txrx_bufs = s3c6410_spi_txrx;
hw->bitbang.master->setup = s3c6410_spi_setup;
init_completion(&hw->done);
/* find and map our resources */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL) {
dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
err = -ENOENT;
goto err_no_iores;
}
hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1,
pdev->name);
if (hw->ioarea == NULL) {
dev_err(&pdev->dev, "Cannot reserve region\n");
err = -ENXIO;
goto err_no_iores;
}
hw->regs = ioremap(res->start, (res->end - res->start)+1);
hw->regs += 0x1000 * hw->id;
if (hw->regs == NULL) {
dev_err(&pdev->dev, "Cannot map IO\n");
err = -ENXIO;
goto err_no_iomap;
}
hw->irq = platform_get_irq(pdev, 0);
if (hw->irq < 0) {
dev_err(&pdev->dev, "No IRQ specified\n");
err = -ENOENT;
goto err_no_irq;
}
err = request_irq(hw->irq, s3c6410_spi_irq, IRQF_DISABLED, pdev->name, hw);
if (err) {
dev_err(&pdev->dev, "Cannot claim IRQ\n");
goto err_no_irq;
}
hw->clk = clk_get(&pdev->dev, "spi");
if (IS_ERR(hw->clk)) {
dev_err(&pdev->dev, "No clock for device\n");
err = PTR_ERR(hw->clk);
goto err_no_clk;
}
printk("S3C6410 SPI Driver at 0x%x, irq %d\n", (unsigned int)hw->regs, hw->irq);
/* for the moment, permanently enable the clock */
#ifdef CONFIG_SPICLK_PCLK
clk_enable(hw->clk);
hw->in_clk = clk_get_rate(hw->clk);
#elif defined (CONFIG_SPICLK_EPLL)
writel((readl(S3C_PCLK_GATE)|S3C_CLKCON_PCLK_SPI0|S3C_CLKCON_PCLK_SPI1),S3C_PCLK_GATE);
writel((readl(S3C_SCLK_GATE)|S3C_CLKCON_SCLK_SPI0|S3C_CLKCON_SCLK_SPI1),S3C_SCLK_GATE);
writel(readl(S3C_CLK_SRC)|S3C_CLKSRC_MPLL_CLKSEL, S3C_CLK_SRC);
/* Set SPi Clock to DOUTMPLL*/
if(hw->id == 0) /* SPI_CHANNEL = 0 */
writel((readl(S3C_CLK_SRC)&~(0x3<<14))|(1<<14), S3C_CLK_SRC);
else /* SPI_CHANNEL = 1 */
writel((readl(S3C_CLK_SRC)&~(0x3<<16))|(1<<16), S3C_CLK_SRC);
/* CLK_DIV2 setting */
/* SPI Input Clock(88.87Mhz) = 266.66Mhz / (2 + 1)*/
writel(((readl(S3C_CLK_DIV2) & ~(0xff << 0)) | 2) , S3C_CLK_DIV2);
hw->in_clk = 266660000;
#elif defined (CONFIG_SPICLK_USBCLK)
writel((readl(S3C_PCLK_GATE)| S3C_CLKCON_PCLK_SPI0|S3C_CLKCON_PCLK_SPI1),S3C_PCLK_GATE);
writel((readl(S3C_SCLK_GATE)|S3C_CLKCON_SCLK_SPI0_48|S3C_CLKCON_SCLK_SPI1_48),S3C_SCLK_GATE);
hw->in_clk = 48000000;
#endif
printk("SPI: Source Clock = %ldMhz\n", hw->in_clk);
/* initialize the gpio */
if (hw->id == 0) {
s3c_gpio_cfgpin(S3C64XX_GPC(0), S3C64XX_GPC0_SPI_MISO0);
s3c_gpio_cfgpin(S3C64XX_GPC(1), S3C64XX_GPC1_SPI_CLK0);
s3c_gpio_cfgpin(S3C64XX_GPC(2), S3C64XX_GPC2_SPI_MOSI0);
s3c_gpio_cfgpin(S3C64XX_GPC(3), S3C64XX_GPC3_SPI_nCS0);
s3c_gpio_setpull(S3C64XX_GPC(0), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPC(1), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPC(2), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPC(3), S3C_GPIO_PULL_UP);
} else {
s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_SPI_MISO1);
s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_SPI_CLK1);
s3c_gpio_cfgpin(S3C64XX_GPC(6), S3C64XX_GPC6_SPI_MOSI1);
s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_SPI_nCS1);
s3c_gpio_setpull(S3C64XX_GPC(4), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPC(5), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPC(6), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPC(7), S3C_GPIO_PULL_UP);
}
/* SW Reset */
writel(readl(hw->regs + S3C_CH_CFG) | SPI_CH_SW_RST, hw->regs + S3C_CH_CFG);
udelay(100);
writel(readl(hw->regs + S3C_CH_CFG) & (~SPI_CH_SW_RST), hw->regs + S3C_CH_CFG);
udelay(100);
/* disable SPI Interrupt */
writel(SPI_INT_ALL_DISABLE, hw->regs + S3C_SPI_INT_EN);
/* Set transfer type (CPOL & CPHA set) */
spi_chcfg = readl(hw->regs + S3C_CH_CFG);
spi_chcfg &= ~SPI_CH_HSPD_EN;
spi_chcfg |= SPI_CH_FORMAT_B | SPI_CH_RISING | SPI_CH_MASTER;
writel(spi_chcfg, hw->regs + S3C_CH_CFG);
/* Set NSSOUT to start high after Reset */
s3c6410_spi_set_cs(hw, BITBANG_CS_INACTIVE);
/* register our spi controller */
err = spi_bitbang_start(&hw->bitbang);
if (err) {
dev_err(&pdev->dev, "Failed to register SPI master\n");
goto err_register;
}
/* register all the devices associated */
bi = hw->pdata->board_info;
for (i = 0; i < hw->pdata->board_size; i++, bi++) {
dev_info(hw->dev, "registering %s\n", bi->modalias);
bi->controller_data = hw;
spi_new_device(master, bi);
}
/* for suspend & resume */
test_hw = hw;
return 0;
err_register:
clk_disable(hw->clk);
clk_put(hw->clk);
err_no_clk:
free_irq(hw->irq, hw);
err_no_irq:
iounmap(hw->regs);
err_no_iomap:
release_resource(hw->ioarea);
kfree(hw->ioarea);
err_no_iores:
err_no_pdata:
spi_master_put(hw->master);;
err_nomem:
return err;
}
.platform_data = &dm9000_setup,
}
};
#endif //#ifdef CONFIG_DM9000
/*add by fatfish for mcp251x*/
static int request_cs_gpio;
static void cs_set_level(unsigned line_id, int lvl) {
//printk(KERN_INFO "SPI: cs set level\n");
gpio_direction_output(line_id, lvl);
};
static struct s3c64xx_spi_csinfo s3c64xx_spi1_csinfo = {
.fb_delay=0x3,
.line=S3C64XX_GPC(7),
.set_level=cs_set_level,
};
static void cfg_fpga_pro(int val)
{
gpio_direction_output(S3C64XX_GPP(12), val);
}
static void setup_pin_fpga(void)
{
int ret;
/* Initialize SPI GPIO for FPGA */
ret = gpio_request(S3C64XX_GPP(8), "fpga");
if (ret) {
printk(KERN_ERR "SPI: Setup CS-Pin0 Error\n");
static void s3c_cs_config(int pin, int mode, int pull)
{
s3c_gpio_cfgpin(pin, mode);
if(pull == CS_HIGH)
s3c_gpio_setpull(pin, S3C_GPIO_PULL_UP);
else
s3c_gpio_setpull(pin, S3C_GPIO_PULL_DOWN);
}
#endif
#if defined(CONFIG_SPI_CNTRLR_0)
static struct s3c_spi_pdata s3c_slv_pdata_0[] __initdata = {
[0] = { /* Slave-0 */
.cs_level = CS_FLOAT,
.cs_pin = S3C64XX_GPC(3),
.cs_mode = S3C64XX_GPC_OUTPUT(3),
.cs_set = s3c_cs_set,
.cs_config = s3c_cs_config,
.cs_suspend = s3c_cs_suspend,
.cs_resume = s3c_cs_resume,
},
[1] = { /* Slave-1 */
.cs_level = CS_FLOAT,
.cs_pin = S3C64XX_GPF(13),
.cs_mode = S3C64XX_GPF_OUTPUT(13),
.cs_set = s3c_cs_setF13,
.cs_config = s3c_cs_configF13,
.cs_suspend = s3c_cs_suspend,
.cs_resume = s3c_cs_resume,
},