void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
{
unsigned int gpio;
unsigned int end;
/* GPIO should be set on 4bit though 1-bit setting is comming. */
if (width == 1)
width = 4;
end = S5P64XX_GPH(2 + width);
/* Set all the necessary GPG pins to special-function 0 */
for (gpio = S5P64XX_GPH(0); gpio < end; gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
s3c_gpio_setpull(S5P64XX_GPG(6), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S5P64XX_GPG(6), S3C_GPIO_SFN(3));
}
}, {
.base = S5P64XX_GPC_BASE,
.config = &gpio_4bit_cfg_eint0111,
.config_slp = &gpio_cfg_slp,
.chip = {
.base = S5P64XX_GPC(0),
.ngpio = S5P64XX_GPIO_C_NR,
.to_irq = s3c_gpc_to_irq,
.label = "GPC",
},
}, {
.base = S5P64XX_GPG_BASE,
.config = &gpio_4bit_cfg_eint0111,
.config_slp = &gpio_cfg_slp,
.chip = {
.base = S5P64XX_GPG(0),
.ngpio = S5P64XX_GPIO_G_NR,
.to_irq = s3c_gpg_to_irq,
.label = "GPG",
},
},
};
static int s3c_gph_to_irq(struct gpio_chip *chip, unsigned offset)
{
return IRQ_EINT_GROUP(6, offset);
}
static struct s3c_gpio_chip gpio_4bit2[] = {
{
.base = S5P64XX_GPH_BASE + 0x4,
