static int smdkc110_mipi_cam_power(int onoff)
{
gpio_request(S5PC11X_GPH0(3), "GPH0");
s3c_gpio_setpull(S5PC11X_GPH0(3), S3C_GPIO_PULL_NONE);
gpio_direction_output(S5PC11X_GPH0(3), 0);
gpio_direction_output(S5PC11X_GPH0(3), 1);
gpio_free(S5PC11X_GPH0(3));
return 0;
}
/*
* External camera reset
* Because the most of cameras take i2c bus signal, so that
* you have to reset at the boot time for other i2c slave devices.
* This function also called at fimc_init_camera()
* Do optimization for cameras on your platform.
*/
static int smdkc110_cam0_power(int onoff)
{
/* Camera A */
gpio_request(S5PC11X_GPH0(2), "GPH0");
s3c_gpio_setpull(S5PC11X_GPH0(2), S3C_GPIO_PULL_NONE);
gpio_direction_output(S5PC11X_GPH0(2), 0);
gpio_direction_output(S5PC11X_GPH0(2), 1);
gpio_free(S5PC11X_GPH0(2));
return 0;
}
s3c_gpio_pull_t s3c_gpio_get_slp_cfgpin(unsigned int pin)
{
struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
void __iomem *reg;
unsigned long flags;
int offset;
u32 con;
int shift;
if (!chip)
return -EINVAL;
if((pin <= S5PC11X_GPH3(7)) && (pin >= S5PC11X_GPH0(0))) {
return -EINVAL;
}
reg = chip->base + 0x10;
offset = pin - chip->chip.base;
shift = offset * 2;
local_irq_save(flags);
con = __raw_readl(reg);
con >>= shift;
con &= 0x3;
local_irq_restore(flags);
return (__force s3c_gpio_pull_t)con;
}
/*
* External camera reset
* Because the most of cameras take i2c bus signal, so that
* you have to reset at the boot time for other i2c slave devices.
* This function also called at fimc_init_camera()
* Do optimization for cameras on your platform.
*/
void cam0_s5k4eagx_reset(int power_up)
{
#define S5PC11X_GPH0 S5PV210_GPH0
#define S5PC11X_GPH1 S5PV210_GPH1
#define S5PC11X_GPE1 S5PV210_GPE1
printk(KERN_INFO "s5k4eagx reset\n");
gpio_request(S5PC11X_GPE1(4), "GPE14");
gpio_direction_output(S5PC11X_GPE1(4), 1);
gpio_request(S5PC11X_GPH0(2), "GPH02");
gpio_direction_output(S5PC11X_GPH0(2), 1);
if(power_up)
{
//reset --> L
gpio_set_value(S5PC11X_GPH0(2), 0);
//STBY --> HIGH
gpio_set_value(S5PC11X_GPE1(4), 1);
mdelay(5);
//reset --> H
gpio_set_value(S5PC11X_GPH0(2), 1);
}
else //power down
{
//reset --> L
gpio_set_value(S5PC11X_GPH0(2), 0);
mdelay(5);
//STBY --> LOW
gpio_set_value(S5PC11X_GPE1(4), 0);
}
gpio_free(S5PC11X_GPE1(4));
gpio_free(S5PC11X_GPH0(2));
}
static irqreturn_t __s5p_hpd_irq(int irq, void *dev_id)
{
if(gpio_get_value(S5PC11X_GPH1(5)))
{
printk("\n cable inserted \n");
set_irq_type(IRQ_EINT13, IRQ_TYPE_EDGE_FALLING);
}
else
{
printk("\n cable removed\n");
set_irq_type(IRQ_EINT13,IRQ_TYPE_EDGE_RISING);
}
#if 0
spin_lock_irq(&slock_hpd);
#ifdef CONFIG_CPU_S5PC110
//mkh:
s5ptv_status.hpd_status = gpio_get_value(S5PC11X_GPH0(5))
? false:true;
#else
s5ptv_status.hpd_status = gpio_get_value(S5PC1XX_GPH0(5))
? false:true;
#endif
if(s5ptv_status.hpd_status){
set_irq_type(IRQ_EINT5, IRQ_TYPE_EDGE_RISING);
}else{
set_irq_type(IRQ_EINT5, IRQ_TYPE_EDGE_FALLING);
}
if (s5ptv_status.hdcp_en)
schedule_work(&ws_hpd);
spin_unlock_irq(&slock_hpd);
BASEPRINTK("hpd_status = %d\n", s5ptv_status.hpd_status);
#endif
return IRQ_HANDLED;
}
int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config)
{
struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
void __iomem *reg;
unsigned long flags;
int offset;
u32 con;
int shift;
if (!chip)
return -EINVAL;
if((pin <= S5PC11X_GPH3(7)) && (pin >= S5PC11X_GPH0(0))) {
return -EINVAL;
}
if(config > S3C_GPIO_PULL_UP)
{
return -EINVAL;
}
reg = chip->base + 0x14;
offset = pin - chip->chip.base;
shift = offset * 2;
local_irq_save(flags);
con = __raw_readl(reg);
con &= ~(3 << shift);
con |= config << shift;
__raw_writel(con, reg);
local_irq_restore(flags);
return 0;
}
static void setup_sdhci0_gpio_wp(void)
{
s3c_gpio_cfgpin(S5PC11X_GPH0(7), S3C_GPIO_INPUT);
s3c_gpio_setpull(S5PC11X_GPH0(7), S3C_GPIO_PULL_DOWN);
}
.ngpio = S5PC11X_GPIO_G2_NR,
.label = "GPG2",
},
}, {
.base = S5PC11X_GPG3_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC11X_GPG3(0),
.ngpio = S5PC11X_GPIO_G3_NR,
.label = "GPG3",
},
}, {
.base = S5PC11X_GPH0_BASE,
.config = &gpio_cfg_noint,
.chip = {
.base = S5PC11X_GPH0(0),
.ngpio = S5PC11X_GPIO_H0_NR,
.label = "GPH0",
},
}, {
.base = S5PC11X_GPH1_BASE,
.config = &gpio_cfg_noint,
.chip = {
.base = S5PC11X_GPH1(0),
.ngpio = S5PC11X_GPIO_H1_NR,
.label = "GPH1",
},
}, {
.base = S5PC11X_GPH2_BASE,
.config = &gpio_cfg_noint,
.chip = {
static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
{
int offs = eint_offset(irq);
int shift;
u32 ctrl, mask;
u32 newvalue = 0;
switch (type) {
case IRQ_TYPE_NONE:
printk(KERN_WARNING "No edge setting!\n");
break;
case IRQ_TYPE_EDGE_RISING:
newvalue = S5P_EXTINT_RISEEDGE;
break;
case IRQ_TYPE_EDGE_FALLING:
newvalue = S5P_EXTINT_FALLEDGE;
break;
case IRQ_TYPE_EDGE_BOTH:
newvalue = S5P_EXTINT_BOTHEDGE;
break;
case IRQ_TYPE_LEVEL_LOW:
newvalue = S5P_EXTINT_LOWLEV;
break;
case IRQ_TYPE_LEVEL_HIGH:
newvalue = S5P_EXTINT_HILEV;
break;
default:
printk(KERN_ERR "No such irq type %d", type);
return -1;
}
shift = (offs & 0x7) * 4;
mask = 0x7 << shift;
ctrl = __raw_readl(S5PC11X_EINTCON(eint_conf_reg(irq)));
ctrl &= ~mask;
ctrl |= newvalue << shift;
__raw_writel(ctrl, S5PC11X_EINTCON(eint_conf_reg(irq)));
#ifdef S5PC11X_ALIVEGPIO_STORE
ctrl = __raw_readl(S5PC11X_EINTCON(eint_conf_reg(irq)));
#endif
if((0 <= offs) && (offs < 8))
s3c_gpio_cfgpin(S5PC11X_GPH0(offs&0x7), 0xf<<((offs&0x7)*4));
else if((8 <= offs) && (offs < 16))
s3c_gpio_cfgpin(S5PC11X_GPH1(offs&0x7), 0xf<<((offs&0x7)*4));
else if((16 <= offs) && (offs < 24))
s3c_gpio_cfgpin(S5PC11X_GPH2(offs&0x7), 0xf<<((offs&0x7)*4));
else if((24 <= offs) && (offs < 32))
s3c_gpio_cfgpin(S5PC11X_GPH3(offs&0x7), 0xf<<((offs&0x7)*4));
else
printk(KERN_ERR "No such irq number %d", offs);
return 0;
}
